arch/arm/boot/dts/rk3036.dtsi

   1 /*
   2  * This file is dual-licensed: you can use it either under the terms
   3  * of the GPL or the X11 license, at your option. Note that this dual
   4  * licensing only applies to this file, and not this project as a
   5  * whole.
   6  *
   7  *  a) This file is free software; you can redistribute it and/or
   8  *     modify it under the terms of the GNU General Public License as
   9  *     published by the Free Software Foundation; either version 2 of the
  10  *     License, or (at your option) any later version.
  11  *
  12  *     This file is distributed in the hope that it will be useful,
  13  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *     GNU General Public License for more details.
  16  *
  17  * Or, alternatively,
  18  *
  19  *  b) Permission is hereby granted, free of charge, to any person
  20  *     obtaining a copy of this software and associated documentation
  21  *     files (the "Software"), to deal in the Software without
  22  *     restriction, including without limitation the rights to use,
  23  *     copy, modify, merge, publish, distribute, sublicense, and/or
  24  *     sell copies of the Software, and to permit persons to whom the
  25  *     Software is furnished to do so, subject to the following
  26  *     conditions:
  27  *
  28  *     The above copyright notice and this permission notice shall be
  29  *     included in all copies or substantial portions of the Software.
  30  *
  31  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  33  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  35  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  36  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  37  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  38  *     OTHER DEALINGS IN THE SOFTWARE.
  39  */
  40
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/interrupt-controller/irq.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/pinctrl/rockchip.h>
  45 #include <dt-bindings/clock/rk3036-cru.h>
  46 #include "skeleton.dtsi"
  47
  48 / {
  49         compatible = "rockchip,rk3036";
  50
  51         interrupt-parent = <&gic>;
  52
  53         aliases {
  54                 i2c0 = &i2c0;
  55                 i2c1 = &i2c1;
  56                 i2c2 = &i2c2;
  57                 mshc0 = &emmc;
  58                 mshc1 = &sdmmc;
  59                 mshc2 = &sdio;
  60                 serial0 = &uart0;
  61                 serial1 = &uart1;
  62                 serial2 = &uart2;
  63         };
  64
  65         memory {
  66                 device_type = "memory";
  67                 reg = <0x60000000 0x40000000>;
  68         };
  69
  70         cpus {
  71                 #address-cells = <1>;
  72                 #size-cells = <0>;
  73                 enable-method = "rockchip,rk3036-smp";
  74
  75                 cpu0: cpu@f00 {
  76                         device_type = "cpu";
  77                         compatible = "arm,cortex-a7";
  78                         reg = <0xf00>;
  79                         resets = <&cru SRST_CORE0>;
  80                         operating-points = <
  81                                 /* KHz    uV */
  82                                  816000 1000000
  83                         >;
  84                         clock-latency = <40000>;
  85                         clocks = <&cru ARMCLK>;
  86                 };
  87
  88                 cpu1: cpu@f01 {
  89                         device_type = "cpu";
  90                         compatible = "arm,cortex-a7";
  91                         reg = <0xf01>;
  92                         resets = <&cru SRST_CORE1>;
  93                 };
  94         };
  95
  96         amba {
  97                 compatible = "arm,amba-bus";
  98                 #address-cells = <1>;
  99                 #size-cells = <1>;
 100                 ranges;
 101
 102                 pdma: pdma@20078000 {
 103                         compatible = "arm,pl330", "arm,primecell";
 104                         reg = <0x20078000 0x4000>;
 105                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 106                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 107                         #dma-cells = <1>;
 108                         clocks = <&cru ACLK_DMAC2>;
 109                         clock-names = "apb_pclk";
 110                 };
 111         };
 112
 113         arm-pmu {
 114                 compatible = "arm,cortex-a7-pmu";
 115                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 116                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 117                 interrupt-affinity = <&cpu0>, <&cpu1>;
 118         };
 119
 120         timer {
 121                 compatible = "arm,armv7-timer";
 122                 arm,cpu-registers-not-fw-configured;
 123                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
 124                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
 125                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
 126                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 127                 clock-frequency = <24000000>;
 128         };
 129
 130         xin24m: oscillator {
 131                 compatible = "fixed-clock";
 132                 clock-frequency = <24000000>;
 133                 clock-output-names = "xin24m";
 134                 #clock-cells = <0>;
 135         };
 136
 137         bus_intmem@10080000 {
 138                 compatible = "mmio-sram";
 139                 reg = <0x10080000 0x2000>;
 140                 #address-cells = <1>;
 141                 #size-cells = <1>;
 142                 ranges = <0 0x10080000 0x2000>;
 143
 144                 smp-sram@0 {
 145                         compatible = "rockchip,rk3066-smp-sram";
 146                         reg = <0x00 0x10>;
 147                 };
 148         };
 149
 150         gic: interrupt-controller@10139000 {
 151                 compatible = "arm,gic-400";
 152                 interrupt-controller;
 153                 #interrupt-cells = <3>;
 154                 #address-cells = <0>;
 155
 156                 reg = <0x10139000 0x1000>,
 157                       <0x1013a000 0x1000>,
 158                       <0x1013c000 0x2000>,
 159                       <0x1013e000 0x2000>;
 160                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 161         };
 162
 163         usb_otg: usb@10180000 {
 164                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 165                                 "snps,dwc2";
 166                 reg = <0x10180000 0x40000>;
 167                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 168                 clocks = <&cru HCLK_OTG0>;
 169                 clock-names = "otg";
 170                 dr_mode = "otg";
 171                 g-np-tx-fifo-size = <16>;
 172                 g-rx-fifo-size = <275>;
 173                 g-tx-fifo-size = <256 128 128 64 64 32>;
 174                 g-use-dma;
 175                 status = "disabled";
 176         };
 177
 178         usb_host: usb@101c0000 {
 179                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 180                                 "snps,dwc2";
 181                 reg = <0x101c0000 0x40000>;
 182                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 183                 clocks = <&cru HCLK_OTG1>;
 184                 clock-names = "otg";
 185                 dr_mode = "host";
 186                 status = "disabled";
 187         };
 188
 189         emac: ethernet@10200000 {
 190                 compatible = "rockchip,rk3036-emac", "snps,arc-emac";
 191                 reg = <0x10200000 0x4000>;
 192                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 193                 #address-cells = <1>;
 194                 #size-cells = <0>;
 195                 rockchip,grf = <&grf>;
 196                 clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>;
 197                 clock-names = "hclk", "macref", "macclk";
 198                 /*
 199                  * Fix the emac parent clock is DPLL instead of APLL.
 200                  * since that will cause some unstable things if the cpufreq
 201                  * is working. (e.g: the accurate 50MHz what mac_ref need)
 202                  */
 203                 assigned-clocks = <&cru SCLK_MACPLL>;
 204                 assigned-clock-parents = <&cru PLL_DPLL>;
 205                 max-speed = <100>;
 206                 phy-mode = "rmii";
 207                 status = "disabled";
 208         };
 209
 210         sdmmc: dwmmc@10214000 {
 211                 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
 212                 reg = <0x10214000 0x4000>;
 213                 clock-frequency = <37500000>;
 214                 clock-freq-min-max = <400000 37500000>;
 215                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 216                 clock-names = "biu", "ciu";
 217                 fifo-depth = <0x100>;
 218                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 219                 status = "disabled";
 220         };
 221
 222         sdio: dwmmc@10218000 {
 223                 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
 224                 reg = <0x10218000 0x4000>;
 225                 clock-freq-min-max = <400000 37500000>;
 226                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 227                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 228                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 229                 fifo-depth = <0x100>;
 230                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 231                 status = "disabled";
 232         };
 233
 234         emmc: dwmmc@1021c000 {
 235                 compatible = "rockchip,rk3288-dw-mshc";
 236                 reg = <0x1021c000 0x4000>;
 237                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 238                 broken-cd;
 239                 bus-width = <8>;
 240                 cap-mmc-highspeed;
 241                 clock-frequency = <37500000>;
 242                 clock-freq-min-max = <400000 37500000>;
 243                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 244                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 245                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 246                 default-sample-phase = <158>;
 247                 disable-wp;
 248                 dmas = <&pdma 12>;
 249                 dma-names = "rx-tx";
 250                 fifo-depth = <0x100>;
 251                 mmc-ddr-1_8v;
 252                 non-removable;
 253                 num-slots = <1>;
 254                 pinctrl-names = "default";
 255                 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
 256                 status = "disabled";
 257         };
 258
 259         i2s: i2s@10220000 {
 260                 compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
 261                 reg = <0x10220000 0x4000>;
 262                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 263                 #address-cells = <1>;
 264                 #size-cells = <0>;
 265                 clock-names = "i2s_hclk", "i2s_clk";
 266                 clocks = <&cru HCLK_I2S>, <&cru SCLK_I2S>;
 267                 dmas = <&pdma 0>, <&pdma 1>;
 268                 dma-names = "tx", "rx";
 269                 pinctrl-names = "default";
 270                 pinctrl-0 = <&i2s_bus>;
 271                 status = "disabled";
 272         };
 273
 274         cru: clock-controller@20000000 {
 275                 compatible = "rockchip,rk3036-cru";
 276                 reg = <0x20000000 0x1000>;
 277                 rockchip,grf = <&grf>;
 278                 #clock-cells = <1>;
 279                 #reset-cells = <1>;
 280                 assigned-clocks = <&cru PLL_GPLL>;
 281                 assigned-clock-rates = <594000000>;
 282         };
 283
 284         grf: syscon@20008000 {
 285                 compatible = "rockchip,rk3036-grf", "syscon";
 286                 reg = <0x20008000 0x1000>;
 287         };
 288
 289         acodec: acodec-ana@20030000 {
 290                 compatible = "rk3036-codec";
 291                 reg = <0x20030000 0x4000>;
 292                 rockchip,grf = <&grf>;
 293                 clock-names = "acodec_pclk";
 294                 clocks = <&cru PCLK_ACODEC>;
 295                 status = "disabled";
 296         };
 297
 298         timer: timer@20044000 {
 299                 compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
 300                 reg = <0x20044000 0x20>;
 301                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 302                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 303                 clock-names = "timer", "pclk";
 304         };
 305
 306         pwm0: pwm@20050000 {
 307                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 308                 reg = <0x20050000 0x10>;
 309                 #pwm-cells = <3>;
 310                 clocks = <&cru PCLK_PWM>;
 311                 clock-names = "pwm";
 312                 pinctrl-names = "default";
 313                 pinctrl-0 = <&pwm0_pin>;
 314                 status = "disabled";
 315         };
 316
 317         pwm1: pwm@20050010 {
 318                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 319                 reg = <0x20050010 0x10>;
 320                 #pwm-cells = <3>;
 321                 clocks = <&cru PCLK_PWM>;
 322                 clock-names = "pwm";
 323                 pinctrl-names = "default";
 324                 pinctrl-0 = <&pwm1_pin>;
 325                 status = "disabled";
 326         };
 327
 328         pwm2: pwm@20050020 {
 329                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 330                 reg = <0x20050020 0x10>;
 331                 #pwm-cells = <3>;
 332                 clocks = <&cru PCLK_PWM>;
 333                 clock-names = "pwm";
 334                 pinctrl-names = "default";
 335                 pinctrl-0 = <&pwm2_pin>;
 336                 status = "disabled";
 337         };
 338
 339         pwm3: pwm@20050030 {
 340                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 341                 reg = <0x20050030 0x10>;
 342                 #pwm-cells = <2>;
 343                 clocks = <&cru PCLK_PWM>;
 344                 clock-names = "pwm";
 345                 pinctrl-names = "default";
 346                 pinctrl-0 = <&pwm3_pin>;
 347                 status = "disabled";
 348         };
 349
 350         i2c1: i2c@20056000 {
 351                 compatible = "rockchip,rk3288-i2c";
 352                 reg = <0x20056000 0x1000>;
 353                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 354                 #address-cells = <1>;
 355                 #size-cells = <0>;
 356                 clock-names = "i2c";
 357                 clocks = <&cru PCLK_I2C1>;
 358                 pinctrl-names = "default";
 359                 pinctrl-0 = <&i2c1_xfer>;
 360                 status = "disabled";
 361         };
 362
 363         i2c2: i2c@2005a000 {
 364                 compatible = "rockchip,rk3288-i2c";
 365                 reg = <0x2005a000 0x1000>;
 366                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 367                 #address-cells = <1>;
 368                 #size-cells = <0>;
 369                 clock-names = "i2c";
 370                 clocks = <&cru PCLK_I2C2>;
 371                 pinctrl-names = "default";
 372                 pinctrl-0 = <&i2c2_xfer>;
 373                 status = "disabled";
 374         };
 375
 376         uart0: serial@20060000 {
 377                 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
 378                 reg = <0x20060000 0x100>;
 379                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 380                 reg-shift = <2>;
 381                 reg-io-width = <4>;
 382                 clock-frequency = <24000000>;
 383                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 384                 clock-names = "baudclk", "apb_pclk";
 385                 pinctrl-names = "default";
 386                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 387                 status = "disabled";
 388         };
 389
 390         uart1: serial@20064000 {
 391                 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
 392                 reg = <0x20064000 0x100>;
 393                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 394                 reg-shift = <2>;
 395                 reg-io-width = <4>;
 396                 clock-frequency = <24000000>;
 397                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 398                 clock-names = "baudclk", "apb_pclk";
 399                 pinctrl-names = "default";
 400                 pinctrl-0 = <&uart1_xfer>;
 401                 status = "disabled";
 402         };
 403
 404         uart2: serial@20068000 {
 405                 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
 406                 reg = <0x20068000 0x100>;
 407                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 408                 reg-shift = <2>;
 409                 reg-io-width = <4>;
 410                 clock-frequency = <24000000>;
 411                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 412                 clock-names = "baudclk", "apb_pclk";
 413                 pinctrl-names = "default";
 414                 pinctrl-0 = <&uart2_xfer>;
 415                 status = "disabled";
 416         };
 417
 418         i2c0: i2c@20072000 {
 419                 compatible = "rockchip,rk3288-i2c";
 420                 reg = <0x20072000 0x1000>;
 421                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 422                 #address-cells = <1>;
 423                 #size-cells = <0>;
 424                 clock-names = "i2c";
 425                 clocks = <&cru PCLK_I2C0>;
 426                 pinctrl-names = "default";
 427                 pinctrl-0 = <&i2c0_xfer>;
 428                 status = "disabled";
 429         };
 430
 431         pinctrl: pinctrl {
 432                 compatible = "rockchip,rk3036-pinctrl";
 433                 rockchip,grf = <&grf>;
 434                 #address-cells = <1>;
 435                 #size-cells = <1>;
 436                 ranges;
 437
 438                 gpio0: gpio0@2007c000 {
 439                         compatible = "rockchip,gpio-bank";
 440                         reg = <0x2007c000 0x100>;
 441                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 442                         clocks = <&cru PCLK_GPIO0>;
 443
 444                         gpio-controller;
 445                         #gpio-cells = <2>;
 446
 447                         interrupt-controller;
 448                         #interrupt-cells = <2>;
 449                 };
 450
 451                 gpio1: gpio1@20080000 {
 452                         compatible = "rockchip,gpio-bank";
 453                         reg = <0x20080000 0x100>;
 454                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 455                         clocks = <&cru PCLK_GPIO1>;
 456
 457                         gpio-controller;
 458                         #gpio-cells = <2>;
 459
 460                         interrupt-controller;
 461                         #interrupt-cells = <2>;
 462                 };
 463
 464                 gpio2: gpio2@20084000 {
 465                         compatible = "rockchip,gpio-bank";
 466                         reg = <0x20084000 0x100>;
 467                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 468                         clocks = <&cru PCLK_GPIO2>;
 469
 470                         gpio-controller;
 471                         #gpio-cells = <2>;
 472
 473                         interrupt-controller;
 474                         #interrupt-cells = <2>;
 475                 };
 476
 477                 pcfg_pull_default: pcfg_pull_default {
 478                         bias-pull-pin-default;
 479                 };
 480
 481                 pcfg_pull_none: pcfg-pull-none {
 482                         bias-disable;
 483                 };
 484
 485                 pwm0 {
 486                         pwm0_pin: pwm0-pin {
 487                                 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
 488                         };
 489                 };
 490
 491                 pwm1 {
 492                         pwm1_pin: pwm1-pin {
 493                                 rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>;
 494                         };
 495                 };
 496
 497                 pwm2 {
 498                         pwm2_pin: pwm2-pin {
 499                                 rockchip,pins = <0 1 2 &pcfg_pull_none>;
 500                         };
 501                 };
 502
 503                 pwm3 {
 504                         pwm3_pin: pwm3-pin {
 505                                 rockchip,pins = <0 27 1 &pcfg_pull_none>;
 506                         };
 507                 };
 508
 509                 sdmmc {
 510                         sdmmc_clk: sdmmc-clk {
 511                                 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>;
 512                         };
 513
 514                         sdmmc_cmd: sdmmc-cmd {
 515                                 rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_default>;
 516                         };
 517
 518                         sdmmc_cd: sdmcc-cd {
 519                                 rockchip,pins = <1 17 RK_FUNC_1 &pcfg_pull_default>;
 520                         };
 521
 522                         sdmmc_bus1: sdmmc-bus1 {
 523                                 rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>;
 524                         };
 525
 526                         sdmmc_bus4: sdmmc-bus4 {
 527                                 rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>,
 528                                                 <1 19 RK_FUNC_1 &pcfg_pull_default>,
 529                                                 <1 20 RK_FUNC_1 &pcfg_pull_default>,
 530                                                 <1 21 RK_FUNC_1 &pcfg_pull_default>;
 531                         };
 532                 };
 533
 534                 sdio {
 535                         sdio_bus1: sdio-bus1 {
 536                                 rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>;
 537                         };
 538
 539                         sdio_bus4: sdio-bus4 {
 540                                 rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>,
 541                                                 <0 12 RK_FUNC_1 &pcfg_pull_default>,
 542                                                 <0 13 RK_FUNC_1 &pcfg_pull_default>,
 543                                                 <0 14 RK_FUNC_1 &pcfg_pull_default>;
 544                         };
 545
 546                         sdio_cmd: sdio-cmd {
 547                                 rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_default>;
 548                         };
 549
 550                         sdio_clk: sdio-clk {
 551                                 rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_none>;
 552                         };
 553                 };
 554
 555                 emmc {
 556                         /*
 557                          * We run eMMC at max speed; bump up drive strength.
 558                          * We also have external pulls, so disable the internal ones.
 559                          */
 560                         emmc_clk: emmc-clk {
 561                                 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
 562                         };
 563
 564                         emmc_cmd: emmc-cmd {
 565                                 rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_default>;
 566                         };
 567
 568                         emmc_bus8: emmc-bus8 {
 569                                 rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_default>,
 570                                                 <1 25 RK_FUNC_2 &pcfg_pull_default>,
 571                                                 <1 26 RK_FUNC_2 &pcfg_pull_default>,
 572                                                 <1 27 RK_FUNC_2 &pcfg_pull_default>,
 573                                                 <1 28 RK_FUNC_2 &pcfg_pull_default>,
 574                                                 <1 29 RK_FUNC_2 &pcfg_pull_default>,
 575                                                 <1 30 RK_FUNC_2 &pcfg_pull_default>,
 576                                                 <1 31 RK_FUNC_2 &pcfg_pull_default>;
 577                         };
 578                 };
 579
 580                 emac {
 581                         emac_xfer: emac-xfer {
 582                                 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_default>, /* crs_dvalid */
 583                                                 <2 13 RK_FUNC_1 &pcfg_pull_default>, /* tx_en */
 584                                                 <2 14 RK_FUNC_1 &pcfg_pull_default>, /* mac_clk */
 585                                                 <2 15 RK_FUNC_1 &pcfg_pull_default>, /* rx_err */
 586                                                 <2 16 RK_FUNC_1 &pcfg_pull_default>, /* rxd1 */
 587                                                 <2 17 RK_FUNC_1 &pcfg_pull_default>, /* rxd0 */
 588                                                 <2 18 RK_FUNC_1 &pcfg_pull_default>, /* txd1 */
 589                                                 <2 19 RK_FUNC_1 &pcfg_pull_default>; /* txd0 */
 590                         };
 591
 592                         emac_mdio: emac-mdio {
 593                                 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_default>, /* mac_md */
 594                                                 <2 25 RK_FUNC_1 &pcfg_pull_default>; /* mac_mdclk */
 595                         };
 596                 };
 597
 598                 i2c0 {
 599                         i2c0_xfer: i2c0-xfer {
 600                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
 601                                                 <0 1 RK_FUNC_1 &pcfg_pull_none>;
 602                         };
 603                 };
 604
 605                 i2c1 {
 606                         i2c1_xfer: i2c1-xfer {
 607                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
 608                                                 <0 3 RK_FUNC_1 &pcfg_pull_none>;
 609                         };
 610                 };
 611
 612                 i2c2 {
 613                         i2c2_xfer: i2c2-xfer {
 614                                 rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>,
 615                                                 <2 21 RK_FUNC_1 &pcfg_pull_none>;
 616                         };
 617                 };
 618
 619                 i2s {
 620                         i2s_bus: i2s-bus {
 621                                 rockchip,pins = <1 0 RK_FUNC_1 &pcfg_pull_none>,
 622                                                 <1 1 RK_FUNC_1 &pcfg_pull_none>,
 623                                                 <1 2 RK_FUNC_1 &pcfg_pull_none>,
 624                                                 <1 3 RK_FUNC_1 &pcfg_pull_none>,
 625                                                 <1 4 RK_FUNC_1 &pcfg_pull_none>,
 626                                                 <1 5 RK_FUNC_1 &pcfg_pull_none>;
 627                         };
 628                 };
 629
 630                 uart0 {
 631                         uart0_xfer: uart0-xfer {
 632                                 rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_default>,
 633                                                 <0 17 RK_FUNC_1 &pcfg_pull_none>;
 634                         };
 635
 636                         uart0_cts: uart0-cts {
 637                                 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_default>;
 638                         };
 639
 640                         uart0_rts: uart0-rts {
 641                                 rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>;
 642                         };
 643                 };
 644
 645                 uart1 {
 646                         uart1_xfer: uart1-xfer {
 647                                 rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_default>,
 648                                                 <2 23 RK_FUNC_1 &pcfg_pull_none>;
 649                         };
 650                         /* no rts / cts for uart1 */
 651                 };
 652
 653                 uart2 {
 654                         uart2_xfer: uart2-xfer {
 655                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_default>,
 656                                                 <1 19 RK_FUNC_2 &pcfg_pull_none>;
 657                         };
 658                         /* no rts / cts for uart2 */
 659                 };
 660         };
 661 };