arch/arm/boot/dts/r8a7794-alt.dts

   1 /*
   2  * Device Tree Source for the Alt board
   3  *
   4  * Copyright (C) 2014 Renesas Electronics Corporation
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 /dts-v1/;
  12 #include "r8a7794.dtsi"
  13 #include <dt-bindings/gpio/gpio.h>
  14
  15 / {
  16         model = "Alt";
  17         compatible = "renesas,alt", "renesas,r8a7794";
  18
  19         aliases {
  20                 serial0 = &scif2;
  21                 i2c10 = &gpioi2c4;
  22                 i2c12 = &i2cexio4;
  23         };
  24
  25         chosen {
  26                 bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
  27                 stdout-path = "serial0:115200n8";
  28         };
  29
  30         memory@40000000 {
  31                 device_type = "memory";
  32                 reg = <0 0x40000000 0 0x40000000>;
  33         };
  34
  35         d3_3v: regulator-d3-3v {
  36                 compatible = "regulator-fixed";
  37                 regulator-name = "D3.3V";
  38                 regulator-min-microvolt = <3300000>;
  39                 regulator-max-microvolt = <3300000>;
  40                 regulator-boot-on;
  41                 regulator-always-on;
  42         };
  43
  44         vcc_sdhi0: regulator-vcc-sdhi0 {
  45                 compatible = "regulator-fixed";
  46
  47                 regulator-name = "SDHI0 Vcc";
  48                 regulator-min-microvolt = <3300000>;
  49                 regulator-max-microvolt = <3300000>;
  50
  51                 gpio = <&gpio2 26 GPIO_ACTIVE_HIGH>;
  52                 enable-active-high;
  53         };
  54
  55         vccq_sdhi0: regulator-vccq-sdhi0 {
  56                 compatible = "regulator-gpio";
  57
  58                 regulator-name = "SDHI0 VccQ";
  59                 regulator-min-microvolt = <1800000>;
  60                 regulator-max-microvolt = <3300000>;
  61
  62                 gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>;
  63                 gpios-states = <1>;
  64                 states = <3300000 1
  65                           1800000 0>;
  66         };
  67
  68         vcc_sdhi1: regulator-vcc-sdhi1 {
  69                 compatible = "regulator-fixed";
  70
  71                 regulator-name = "SDHI1 Vcc";
  72                 regulator-min-microvolt = <3300000>;
  73                 regulator-max-microvolt = <3300000>;
  74
  75                 gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>;
  76                 enable-active-high;
  77         };
  78
  79         vccq_sdhi1: regulator-vccq-sdhi1 {
  80                 compatible = "regulator-gpio";
  81
  82                 regulator-name = "SDHI1 VccQ";
  83                 regulator-min-microvolt = <1800000>;
  84                 regulator-max-microvolt = <3300000>;
  85
  86                 gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
  87                 gpios-states = <1>;
  88                 states = <3300000 1
  89                           1800000 0>;
  90         };
  91
  92         lbsc {
  93                 #address-cells = <1>;
  94                 #size-cells = <1>;
  95         };
  96
  97         vga-encoder {
  98                 compatible = "adi,adv7123";
  99
 100                 ports {
 101                         #address-cells = <1>;
 102                         #size-cells = <0>;
 103
 104                         port@0 {
 105                                 reg = <0>;
 106                                 adv7123_in: endpoint {
 107                                         remote-endpoint = <&du_out_rgb1>;
 108                                 };
 109                         };
 110                         port@1 {
 111                                 reg = <1>;
 112                                 adv7123_out: endpoint {
 113                                         remote-endpoint = <&vga_in>;
 114                                 };
 115                         };
 116                 };
 117         };
 118
 119         vga {
 120                 compatible = "vga-connector";
 121
 122                 port {
 123                         vga_in: endpoint {
 124                                 remote-endpoint = <&adv7123_out>;
 125                         };
 126                 };
 127         };
 128
 129         x2_clk: x2-clock {
 130                 compatible = "fixed-clock";
 131                 #clock-cells = <0>;
 132                 clock-frequency = <74250000>;
 133         };
 134
 135         x13_clk: x13-clock {
 136                 compatible = "fixed-clock";
 137                 #clock-cells = <0>;
 138                 clock-frequency = <148500000>;
 139         };
 140
 141         gpioi2c4: i2c-10 {
 142                 #address-cells = <1>;
 143                 #size-cells = <0>;
 144                 compatible = "i2c-gpio";
 145                 status = "disabled";
 146                 sda-gpios = <&gpio4 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 147                 scl-gpios = <&gpio4 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 148                 i2c-gpio,delay-us = <5>;
 149         };
 150
 151         /*
 152          * I2C4 is routed to EXIO connector B, pins 73 (SCL) + 74 (SDA).
 153          * A fallback to GPIO is provided.
 154          */
 155         i2cexio4: i2c-14 {
 156                 compatible = "i2c-demux-pinctrl";
 157                 i2c-parent = <&i2c4>, <&gpioi2c4>;
 158                 i2c-bus-name = "i2c-exio4";
 159                 #address-cells = <1>;
 160                 #size-cells = <0>;
 161         };
 162 };
 163
 164 &du {
 165         pinctrl-0 = <&du_pins>;
 166         pinctrl-names = "default";
 167         status = "okay";
 168
 169         clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
 170                  <&x13_clk>, <&x2_clk>;
 171         clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
 172
 173         ports {
 174                 port@1 {
 175                         endpoint {
 176                                 remote-endpoint = <&adv7123_in>;
 177                         };
 178                 };
 179         };
 180 };
 181
 182 &extal_clk {
 183         clock-frequency = <20000000>;
 184 };
 185
 186 &pfc {
 187         pinctrl-0 = <&scif_clk_pins>;
 188         pinctrl-names = "default";
 189
 190         du_pins: du {
 191                 groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_clk0_out";
 192                 function = "du1";
 193         };
 194
 195         scif2_pins: scif2 {
 196                 groups = "scif2_data";
 197                 function = "scif2";
 198         };
 199
 200         scif_clk_pins: scif_clk {
 201                 groups = "scif_clk";
 202                 function = "scif_clk";
 203         };
 204
 205         ether_pins: ether {
 206                 groups = "eth_link", "eth_mdio", "eth_rmii";
 207                 function = "eth";
 208         };
 209
 210         phy1_pins: phy1 {
 211                 groups = "intc_irq8";
 212                 function = "intc";
 213         };
 214
 215         i2c1_pins: i2c1 {
 216                 groups = "i2c1";
 217                 function = "i2c1";
 218         };
 219
 220         i2c4_pins: i2c4 {
 221                 groups = "i2c4";
 222                 function = "i2c4";
 223         };
 224
 225         vin0_pins: vin0 {
 226                 groups = "vin0_data8", "vin0_clk";
 227                 function = "vin0";
 228         };
 229
 230         mmcif0_pins: mmcif0 {
 231                 groups = "mmc_data8", "mmc_ctrl";
 232                 function = "mmc";
 233         };
 234
 235         sdhi0_pins: sd0 {
 236                 groups = "sdhi0_data4", "sdhi0_ctrl";
 237                 function = "sdhi0";
 238                 power-source = <3300>;
 239         };
 240
 241         sdhi0_pins_uhs: sd0_uhs {
 242                 groups = "sdhi0_data4", "sdhi0_ctrl";
 243                 function = "sdhi0";
 244                 power-source = <1800>;
 245         };
 246
 247         sdhi1_pins: sd1 {
 248                 groups = "sdhi1_data4", "sdhi1_ctrl";
 249                 function = "sdhi1";
 250                 power-source = <3300>;
 251         };
 252
 253         sdhi1_pins_uhs: sd1_uhs {
 254                 groups = "sdhi1_data4", "sdhi1_ctrl";
 255                 function = "sdhi1";
 256                 power-source = <1800>;
 257         };
 258 };
 259
 260 &cmt0 {
 261         status = "okay";
 262 };
 263
 264 &pfc {
 265         qspi_pins: qspi {
 266                 groups = "qspi_ctrl", "qspi_data4";
 267                 function = "qspi";
 268         };
 269 };
 270
 271 &ether {
 272         pinctrl-0 = <&ether_pins &phy1_pins>;
 273         pinctrl-names = "default";
 274
 275         phy-handle = <&phy1>;
 276         renesas,ether-link-active-low;
 277         status = "okay";
 278
 279         phy1: ethernet-phy@1 {
 280                 reg = <1>;
 281                 interrupt-parent = <&irqc0>;
 282                 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
 283                 micrel,led-mode = <1>;
 284         };
 285 };
 286
 287 &mmcif0 {
 288         pinctrl-0 = <&mmcif0_pins>;
 289         pinctrl-names = "default";
 290
 291         vmmc-supply = <&d3_3v>;
 292         vqmmc-supply = <&d3_3v>;
 293         bus-width = <8>;
 294         non-removable;
 295         status = "okay";
 296 };
 297
 298 &sdhi0 {
 299         pinctrl-0 = <&sdhi0_pins>;
 300         pinctrl-1 = <&sdhi0_pins_uhs>;
 301         pinctrl-names = "default", "state_uhs";
 302
 303         vmmc-supply = <&vcc_sdhi0>;
 304         vqmmc-supply = <&vccq_sdhi0>;
 305         cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
 306         wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
 307         sd-uhs-sdr50;
 308         sd-uhs-sdr104;
 309         status = "okay";
 310 };
 311
 312 &sdhi1 {
 313         pinctrl-0 = <&sdhi1_pins>;
 314         pinctrl-1 = <&sdhi1_pins_uhs>;
 315         pinctrl-names = "default", "state_uhs";
 316
 317         vmmc-supply = <&vcc_sdhi1>;
 318         vqmmc-supply = <&vccq_sdhi1>;
 319         cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
 320         wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
 321         sd-uhs-sdr50;
 322         status = "okay";
 323 };
 324
 325 &i2c1 {
 326         pinctrl-0 = <&i2c1_pins>;
 327         pinctrl-names = "default";
 328
 329         status = "okay";
 330         clock-frequency = <400000>;
 331
 332         composite-in@20 {
 333                 compatible = "adi,adv7180";
 334                 reg = <0x20>;
 335                 remote = <&vin0>;
 336
 337                 port {
 338                         adv7180: endpoint {
 339                                 bus-width = <8>;
 340                                 remote-endpoint = <&vin0ep>;
 341                         };
 342                 };
 343         };
 344 };
 345
 346 &i2c4 {
 347         pinctrl-0 = <&i2c4_pins>;
 348         pinctrl-names = "i2c-exio4";
 349 };
 350
 351 &vin0 {
 352         status = "okay";
 353         pinctrl-0 = <&vin0_pins>;
 354         pinctrl-names = "default";
 355
 356         port {
 357                 #address-cells = <1>;
 358                 #size-cells = <0>;
 359
 360                 vin0ep: endpoint {
 361                         remote-endpoint = <&adv7180>;
 362                         bus-width = <8>;
 363                 };
 364         };
 365 };
 366
 367 &scif2 {
 368         pinctrl-0 = <&scif2_pins>;
 369         pinctrl-names = "default";
 370
 371         status = "okay";
 372 };
 373
 374 &scif_clk {
 375         clock-frequency = <14745600>;
 376 };
 377
 378 &qspi {
 379         pinctrl-0 = <&qspi_pins>;
 380         pinctrl-names = "default";
 381
 382         status = "okay";
 383
 384         flash@0 {
 385                 compatible = "spansion,s25fl512s", "jedec,spi-nor";
 386                 reg = <0>;
 387                 spi-max-frequency = <30000000>;
 388                 spi-tx-bus-width = <4>;
 389                 spi-rx-bus-width = <4>;
 390                 spi-cpol;
 391                 spi-cpha;
 392                 m25p,fast-read;
 393
 394                 partitions {
 395                         compatible = "fixed-partitions";
 396                         #address-cells = <1>;
 397                         #size-cells = <1>;
 398
 399                         partition@0 {
 400                                 label = "loader";
 401                                 reg = <0x00000000 0x00040000>;
 402                                 read-only;
 403                         };
 404                         partition@40000 {
 405                                 label = "system";
 406                                 reg = <0x00040000 0x00040000>;
 407                                 read-only;
 408                         };
 409                         partition@80000 {
 410                                 label = "user";
 411                                 reg = <0x00080000 0x03f80000>;
 412                         };
 413                 };
 414         };
 415 };