arch/arm/boot/dts/r8a7793.dtsi

   1 /*
   2  * Device Tree Source for the r8a7793 SoC
   3  *
   4  * Copyright (C) 2014-2015 Renesas Electronics Corporation
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 #include <dt-bindings/clock/r8a7793-clock.h>
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13 #include <dt-bindings/interrupt-controller/irq.h>
  14 #include <dt-bindings/power/r8a7793-sysc.h>
  15
  16 / {
  17         compatible = "renesas,r8a7793";
  18         interrupt-parent = <&gic>;
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         aliases {
  23                 i2c0 = &i2c0;
  24                 i2c1 = &i2c1;
  25                 i2c2 = &i2c2;
  26                 i2c3 = &i2c3;
  27                 i2c4 = &i2c4;
  28                 i2c5 = &i2c5;
  29                 i2c6 = &i2c6;
  30                 i2c7 = &i2c7;
  31                 i2c8 = &i2c8;
  32                 spi0 = &qspi;
  33         };
  34
  35         cpus {
  36                 #address-cells = <1>;
  37                 #size-cells = <0>;
  38
  39                 cpu0: cpu@0 {
  40                         device_type = "cpu";
  41                         compatible = "arm,cortex-a15";
  42                         reg = <0>;
  43                         clock-frequency = <1500000000>;
  44                         voltage-tolerance = <1>; /* 1% */
  45                         clocks = <&cpg_clocks R8A7793_CLK_Z>;
  46                         clock-latency = <300000>; /* 300 us */
  47                         power-domains = <&sysc R8A7793_PD_CA15_CPU0>;
  48
  49                         /* kHz - uV - OPPs unknown yet */
  50                         operating-points = <1500000 1000000>,
  51                                            <1312500 1000000>,
  52                                            <1125000 1000000>,
  53                                            < 937500 1000000>,
  54                                            < 750000 1000000>,
  55                                            < 375000 1000000>;
  56                         next-level-cache = <&L2_CA15>;
  57                 };
  58         };
  59
  60         thermal-zones {
  61                 cpu_thermal: cpu-thermal {
  62                         polling-delay-passive   = <0>;
  63                         polling-delay           = <0>;
  64
  65                         thermal-sensors = <&thermal>;
  66
  67                         trips {
  68                                 cpu-crit {
  69                                         temperature     = <115000>;
  70                                         hysteresis      = <0>;
  71                                         type            = "critical";
  72                                 };
  73                         };
  74                         cooling-maps {
  75                         };
  76                 };
  77         };
  78
  79         L2_CA15: cache-controller@0 {
  80                 compatible = "cache";
  81                 power-domains = <&sysc R8A7793_PD_CA15_SCU>;
  82                 cache-unified;
  83                 cache-level = <2>;
  84         };
  85
  86         gic: interrupt-controller@f1001000 {
  87                 compatible = "arm,gic-400";
  88                 #interrupt-cells = <3>;
  89                 #address-cells = <0>;
  90                 interrupt-controller;
  91                 reg = <0 0xf1001000 0 0x1000>,
  92                         <0 0xf1002000 0 0x1000>,
  93                         <0 0xf1004000 0 0x2000>,
  94                         <0 0xf1006000 0 0x2000>;
  95                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  96         };
  97
  98         gpio0: gpio@e6050000 {
  99                 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
 100                 reg = <0 0xe6050000 0 0x50>;
 101                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 102                 #gpio-cells = <2>;
 103                 gpio-controller;
 104                 gpio-ranges = <&pfc 0 0 32>;
 105                 #interrupt-cells = <2>;
 106                 interrupt-controller;
 107                 clocks = <&mstp9_clks R8A7793_CLK_GPIO0>;
 108                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 109         };
 110
 111         gpio1: gpio@e6051000 {
 112                 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
 113                 reg = <0 0xe6051000 0 0x50>;
 114                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 115                 #gpio-cells = <2>;
 116                 gpio-controller;
 117                 gpio-ranges = <&pfc 0 32 26>;
 118                 #interrupt-cells = <2>;
 119                 interrupt-controller;
 120                 clocks = <&mstp9_clks R8A7793_CLK_GPIO1>;
 121                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 122         };
 123
 124         gpio2: gpio@e6052000 {
 125                 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
 126                 reg = <0 0xe6052000 0 0x50>;
 127                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 128                 #gpio-cells = <2>;
 129                 gpio-controller;
 130                 gpio-ranges = <&pfc 0 64 32>;
 131                 #interrupt-cells = <2>;
 132                 interrupt-controller;
 133                 clocks = <&mstp9_clks R8A7793_CLK_GPIO2>;
 134                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 135         };
 136
 137         gpio3: gpio@e6053000 {
 138                 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
 139                 reg = <0 0xe6053000 0 0x50>;
 140                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 141                 #gpio-cells = <2>;
 142                 gpio-controller;
 143                 gpio-ranges = <&pfc 0 96 32>;
 144                 #interrupt-cells = <2>;
 145                 interrupt-controller;
 146                 clocks = <&mstp9_clks R8A7793_CLK_GPIO3>;
 147                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 148         };
 149
 150         gpio4: gpio@e6054000 {
 151                 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
 152                 reg = <0 0xe6054000 0 0x50>;
 153                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 154                 #gpio-cells = <2>;
 155                 gpio-controller;
 156                 gpio-ranges = <&pfc 0 128 32>;
 157                 #interrupt-cells = <2>;
 158                 interrupt-controller;
 159                 clocks = <&mstp9_clks R8A7793_CLK_GPIO4>;
 160                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 161         };
 162
 163         gpio5: gpio@e6055000 {
 164                 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
 165                 reg = <0 0xe6055000 0 0x50>;
 166                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 167                 #gpio-cells = <2>;
 168                 gpio-controller;
 169                 gpio-ranges = <&pfc 0 160 32>;
 170                 #interrupt-cells = <2>;
 171                 interrupt-controller;
 172                 clocks = <&mstp9_clks R8A7793_CLK_GPIO5>;
 173                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 174         };
 175
 176         gpio6: gpio@e6055400 {
 177                 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
 178                 reg = <0 0xe6055400 0 0x50>;
 179                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 180                 #gpio-cells = <2>;
 181                 gpio-controller;
 182                 gpio-ranges = <&pfc 0 192 32>;
 183                 #interrupt-cells = <2>;
 184                 interrupt-controller;
 185                 clocks = <&mstp9_clks R8A7793_CLK_GPIO6>;
 186                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 187         };
 188
 189         gpio7: gpio@e6055800 {
 190                 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
 191                 reg = <0 0xe6055800 0 0x50>;
 192                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 193                 #gpio-cells = <2>;
 194                 gpio-controller;
 195                 gpio-ranges = <&pfc 0 224 26>;
 196                 #interrupt-cells = <2>;
 197                 interrupt-controller;
 198                 clocks = <&mstp9_clks R8A7793_CLK_GPIO7>;
 199                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 200         };
 201
 202         thermal: thermal@e61f0000 {
 203                 compatible =    "renesas,thermal-r8a7793",
 204                                 "renesas,rcar-gen2-thermal",
 205                                 "renesas,rcar-thermal";
 206                 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
 207                 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 208                 clocks = <&mstp5_clks R8A7793_CLK_THERMAL>;
 209                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 210                 #thermal-sensor-cells = <0>;
 211         };
 212
 213         timer {
 214                 compatible = "arm,armv7-timer";
 215                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 216                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 217                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 218                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 219         };
 220
 221         cmt0: timer@ffca0000 {
 222                 compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2";
 223                 reg = <0 0xffca0000 0 0x1004>;
 224                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 225                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 226                 clocks = <&mstp1_clks R8A7793_CLK_CMT0>;
 227                 clock-names = "fck";
 228                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 229
 230                 renesas,channels-mask = <0x60>;
 231
 232                 status = "disabled";
 233         };
 234
 235         cmt1: timer@e6130000 {
 236                 compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2";
 237                 reg = <0 0xe6130000 0 0x1004>;
 238                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 239                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 240                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 241                              <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 242                              <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
 243                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
 244                              <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
 245                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 246                 clocks = <&mstp3_clks R8A7793_CLK_CMT1>;
 247                 clock-names = "fck";
 248                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 249
 250                 renesas,channels-mask = <0xff>;
 251
 252                 status = "disabled";
 253         };
 254
 255         irqc0: interrupt-controller@e61c0000 {
 256                 compatible = "renesas,irqc-r8a7793", "renesas,irqc";
 257                 #interrupt-cells = <2>;
 258                 interrupt-controller;
 259                 reg = <0 0xe61c0000 0 0x200>;
 260                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 261                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 262                              <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 263                              <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 264                              <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 265                              <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 266                              <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 267                              <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 268                              <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 269                              <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 270                 clocks = <&mstp4_clks R8A7793_CLK_IRQC>;
 271                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 272         };
 273
 274         dmac0: dma-controller@e6700000 {
 275                 compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
 276                 reg = <0 0xe6700000 0 0x20000>;
 277                 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
 278                               GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
 279                               GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
 280                               GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
 281                               GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
 282                               GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
 283                               GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
 284                               GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
 285                               GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
 286                               GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
 287                               GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
 288                               GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
 289                               GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
 290                               GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
 291                               GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
 292                               GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
 293                 interrupt-names = "error",
 294                                 "ch0", "ch1", "ch2", "ch3",
 295                                 "ch4", "ch5", "ch6", "ch7",
 296                                 "ch8", "ch9", "ch10", "ch11",
 297                                 "ch12", "ch13", "ch14";
 298                 clocks = <&mstp2_clks R8A7793_CLK_SYS_DMAC0>;
 299                 clock-names = "fck";
 300                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 301                 #dma-cells = <1>;
 302                 dma-channels = <15>;
 303         };
 304
 305         dmac1: dma-controller@e6720000 {
 306                 compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
 307                 reg = <0 0xe6720000 0 0x20000>;
 308                 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
 309                               GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
 310                               GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
 311                               GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
 312                               GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
 313                               GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
 314                               GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
 315                               GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
 316                               GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
 317                               GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
 318                               GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
 319                               GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
 320                               GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
 321                               GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
 322                               GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
 323                               GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
 324                 interrupt-names = "error",
 325                                 "ch0", "ch1", "ch2", "ch3",
 326                                 "ch4", "ch5", "ch6", "ch7",
 327                                 "ch8", "ch9", "ch10", "ch11",
 328                                 "ch12", "ch13", "ch14";
 329                 clocks = <&mstp2_clks R8A7793_CLK_SYS_DMAC1>;
 330                 clock-names = "fck";
 331                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 332                 #dma-cells = <1>;
 333                 dma-channels = <15>;
 334         };
 335
 336         audma0: dma-controller@ec700000 {
 337                 compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
 338                 reg = <0 0xec700000 0 0x10000>;
 339                 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
 340                               GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
 341                               GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
 342                               GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
 343                               GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
 344                               GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
 345                               GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
 346                               GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
 347                               GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
 348                               GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
 349                               GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
 350                               GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
 351                               GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
 352                               GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
 353                 interrupt-names = "error",
 354                                 "ch0", "ch1", "ch2", "ch3",
 355                                 "ch4", "ch5", "ch6", "ch7",
 356                                 "ch8", "ch9", "ch10", "ch11",
 357                                 "ch12";
 358                 clocks = <&mstp5_clks R8A7793_CLK_AUDIO_DMAC0>;
 359                 clock-names = "fck";
 360                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 361                 #dma-cells = <1>;
 362                 dma-channels = <13>;
 363         };
 364
 365         audma1: dma-controller@ec720000 {
 366                 compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
 367                 reg = <0 0xec720000 0 0x10000>;
 368                 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
 369                               GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
 370                               GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
 371                               GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
 372                               GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
 373                               GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
 374                               GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
 375                               GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
 376                               GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
 377                               GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
 378                               GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
 379                               GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
 380                               GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
 381                               GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
 382                 interrupt-names = "error",
 383                                 "ch0", "ch1", "ch2", "ch3",
 384                                 "ch4", "ch5", "ch6", "ch7",
 385                                 "ch8", "ch9", "ch10", "ch11",
 386                                 "ch12";
 387                 clocks = <&mstp5_clks R8A7793_CLK_AUDIO_DMAC1>;
 388                 clock-names = "fck";
 389                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 390                 #dma-cells = <1>;
 391                 dma-channels = <13>;
 392         };
 393
 394         /* The memory map in the User's Manual maps the cores to bus numbers */
 395         i2c0: i2c@e6508000 {
 396                 #address-cells = <1>;
 397                 #size-cells = <0>;
 398                 compatible = "renesas,i2c-r8a7793";
 399                 reg = <0 0xe6508000 0 0x40>;
 400                 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
 401                 clocks = <&mstp9_clks R8A7793_CLK_I2C0>;
 402                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 403                 i2c-scl-internal-delay-ns = <6>;
 404                 status = "disabled";
 405         };
 406
 407         i2c1: i2c@e6518000 {
 408                 #address-cells = <1>;
 409                 #size-cells = <0>;
 410                 compatible = "renesas,i2c-r8a7793";
 411                 reg = <0 0xe6518000 0 0x40>;
 412                 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
 413                 clocks = <&mstp9_clks R8A7793_CLK_I2C1>;
 414                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 415                 i2c-scl-internal-delay-ns = <6>;
 416                 status = "disabled";
 417         };
 418
 419         i2c2: i2c@e6530000 {
 420                 #address-cells = <1>;
 421                 #size-cells = <0>;
 422                 compatible = "renesas,i2c-r8a7793";
 423                 reg = <0 0xe6530000 0 0x40>;
 424                 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
 425                 clocks = <&mstp9_clks R8A7793_CLK_I2C2>;
 426                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 427                 i2c-scl-internal-delay-ns = <6>;
 428                 status = "disabled";
 429         };
 430
 431         i2c3: i2c@e6540000 {
 432                 #address-cells = <1>;
 433                 #size-cells = <0>;
 434                 compatible = "renesas,i2c-r8a7793";
 435                 reg = <0 0xe6540000 0 0x40>;
 436                 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
 437                 clocks = <&mstp9_clks R8A7793_CLK_I2C3>;
 438                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 439                 i2c-scl-internal-delay-ns = <6>;
 440                 status = "disabled";
 441         };
 442
 443         i2c4: i2c@e6520000 {
 444                 #address-cells = <1>;
 445                 #size-cells = <0>;
 446                 compatible = "renesas,i2c-r8a7793";
 447                 reg = <0 0xe6520000 0 0x40>;
 448                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 449                 clocks = <&mstp9_clks R8A7793_CLK_I2C4>;
 450                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 451                 i2c-scl-internal-delay-ns = <6>;
 452                 status = "disabled";
 453         };
 454
 455         i2c5: i2c@e6528000 {
 456                 /* doesn't need pinmux */
 457                 #address-cells = <1>;
 458                 #size-cells = <0>;
 459                 compatible = "renesas,i2c-r8a7793";
 460                 reg = <0 0xe6528000 0 0x40>;
 461                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 462                 clocks = <&mstp9_clks R8A7793_CLK_I2C5>;
 463                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 464                 i2c-scl-internal-delay-ns = <110>;
 465                 status = "disabled";
 466         };
 467
 468         i2c6: i2c@e60b0000 {
 469                 /* doesn't need pinmux */
 470                 #address-cells = <1>;
 471                 #size-cells = <0>;
 472                 compatible = "renesas,iic-r8a7793", "renesas,rmobile-iic";
 473                 reg = <0 0xe60b0000 0 0x425>;
 474                 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
 475                 clocks = <&mstp9_clks R8A7793_CLK_IICDVFS>;
 476                 dmas = <&dmac0 0x77>, <&dmac0 0x78>;
 477                 dma-names = "tx", "rx";
 478                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 479                 status = "disabled";
 480         };
 481
 482         i2c7: i2c@e6500000 {
 483                 #address-cells = <1>;
 484                 #size-cells = <0>;
 485                 compatible = "renesas,iic-r8a7793", "renesas,rmobile-iic";
 486                 reg = <0 0xe6500000 0 0x425>;
 487                 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
 488                 clocks = <&mstp3_clks R8A7793_CLK_IIC0>;
 489                 dmas = <&dmac0 0x61>, <&dmac0 0x62>;
 490                 dma-names = "tx", "rx";
 491                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 492                 status = "disabled";
 493         };
 494
 495         i2c8: i2c@e6510000 {
 496                 #address-cells = <1>;
 497                 #size-cells = <0>;
 498                 compatible = "renesas,iic-r8a7793", "renesas,rmobile-iic";
 499                 reg = <0 0xe6510000 0 0x425>;
 500                 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
 501                 clocks = <&mstp3_clks R8A7793_CLK_IIC1>;
 502                 dmas = <&dmac0 0x65>, <&dmac0 0x66>;
 503                 dma-names = "tx", "rx";
 504                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 505                 status = "disabled";
 506         };
 507
 508         pfc: pfc@e6060000 {
 509                 compatible = "renesas,pfc-r8a7793";
 510                 reg = <0 0xe6060000 0 0x250>;
 511         };
 512
 513         sdhi0: sd@ee100000 {
 514                 compatible = "renesas,sdhi-r8a7793";
 515                 reg = <0 0xee100000 0 0x328>;
 516                 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
 517                 clocks = <&mstp3_clks R8A7793_CLK_SDHI0>;
 518                 dmas = <&dmac0 0xcd>, <&dmac0 0xce>;
 519                 dma-names = "tx", "rx";
 520                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 521                 status = "disabled";
 522         };
 523
 524         sdhi1: sd@ee140000 {
 525                 compatible = "renesas,sdhi-r8a7793";
 526                 reg = <0 0xee140000 0 0x100>;
 527                 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
 528                 clocks = <&mstp3_clks R8A7793_CLK_SDHI1>;
 529                 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>;
 530                 dma-names = "tx", "rx";
 531                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 532                 status = "disabled";
 533         };
 534
 535         sdhi2: sd@ee160000 {
 536                 compatible = "renesas,sdhi-r8a7793";
 537                 reg = <0 0xee160000 0 0x100>;
 538                 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
 539                 clocks = <&mstp3_clks R8A7793_CLK_SDHI2>;
 540                 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>;
 541                 dma-names = "tx", "rx";
 542                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 543                 status = "disabled";
 544         };
 545
 546         scifa0: serial@e6c40000 {
 547                 compatible = "renesas,scifa-r8a7793",
 548                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 549                 reg = <0 0xe6c40000 0 64>;
 550                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 551                 clocks = <&mstp2_clks R8A7793_CLK_SCIFA0>;
 552                 clock-names = "fck";
 553                 dmas = <&dmac0 0x21>, <&dmac0 0x22>;
 554                 dma-names = "tx", "rx";
 555                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 556                 status = "disabled";
 557         };
 558
 559         scifa1: serial@e6c50000 {
 560                 compatible = "renesas,scifa-r8a7793",
 561                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 562                 reg = <0 0xe6c50000 0 64>;
 563                 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 564                 clocks = <&mstp2_clks R8A7793_CLK_SCIFA1>;
 565                 clock-names = "fck";
 566                 dmas = <&dmac0 0x25>, <&dmac0 0x26>;
 567                 dma-names = "tx", "rx";
 568                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 569                 status = "disabled";
 570         };
 571
 572         scifa2: serial@e6c60000 {
 573                 compatible = "renesas,scifa-r8a7793",
 574                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 575                 reg = <0 0xe6c60000 0 64>;
 576                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
 577                 clocks = <&mstp2_clks R8A7793_CLK_SCIFA2>;
 578                 clock-names = "fck";
 579                 dmas = <&dmac0 0x27>, <&dmac0 0x28>;
 580                 dma-names = "tx", "rx";
 581                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 582                 status = "disabled";
 583         };
 584
 585         scifa3: serial@e6c70000 {
 586                 compatible = "renesas,scifa-r8a7793",
 587                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 588                 reg = <0 0xe6c70000 0 64>;
 589                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 590                 clocks = <&mstp11_clks R8A7793_CLK_SCIFA3>;
 591                 clock-names = "fck";
 592                 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>;
 593                 dma-names = "tx", "rx";
 594                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 595                 status = "disabled";
 596         };
 597
 598         scifa4: serial@e6c78000 {
 599                 compatible = "renesas,scifa-r8a7793",
 600                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 601                 reg = <0 0xe6c78000 0 64>;
 602                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 603                 clocks = <&mstp11_clks R8A7793_CLK_SCIFA4>;
 604                 clock-names = "fck";
 605                 dmas = <&dmac0 0x1f>, <&dmac0 0x20>;
 606                 dma-names = "tx", "rx";
 607                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 608                 status = "disabled";
 609         };
 610
 611         scifa5: serial@e6c80000 {
 612                 compatible = "renesas,scifa-r8a7793",
 613                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 614                 reg = <0 0xe6c80000 0 64>;
 615                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 616                 clocks = <&mstp11_clks R8A7793_CLK_SCIFA5>;
 617                 clock-names = "fck";
 618                 dmas = <&dmac0 0x23>, <&dmac0 0x24>;
 619                 dma-names = "tx", "rx";
 620                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 621                 status = "disabled";
 622         };
 623
 624         scifb0: serial@e6c20000 {
 625                 compatible = "renesas,scifb-r8a7793",
 626                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 627                 reg = <0 0xe6c20000 0 64>;
 628                 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
 629                 clocks = <&mstp2_clks R8A7793_CLK_SCIFB0>;
 630                 clock-names = "fck";
 631                 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
 632                 dma-names = "tx", "rx";
 633                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 634                 status = "disabled";
 635         };
 636
 637         scifb1: serial@e6c30000 {
 638                 compatible = "renesas,scifb-r8a7793",
 639                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 640                 reg = <0 0xe6c30000 0 64>;
 641                 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 642                 clocks = <&mstp2_clks R8A7793_CLK_SCIFB1>;
 643                 clock-names = "fck";
 644                 dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
 645                 dma-names = "tx", "rx";
 646                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 647                 status = "disabled";
 648         };
 649
 650         scifb2: serial@e6ce0000 {
 651                 compatible = "renesas,scifb-r8a7793",
 652                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 653                 reg = <0 0xe6ce0000 0 64>;
 654                 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
 655                 clocks = <&mstp2_clks R8A7793_CLK_SCIFB2>;
 656                 clock-names = "fck";
 657                 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
 658                 dma-names = "tx", "rx";
 659                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 660                 status = "disabled";
 661         };
 662
 663         scif0: serial@e6e60000 {
 664                 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
 665                              "renesas,scif";
 666                 reg = <0 0xe6e60000 0 64>;
 667                 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 668                 clocks = <&mstp7_clks R8A7793_CLK_SCIF0>, <&zs_clk>,
 669                          <&scif_clk>;
 670                 clock-names = "fck", "brg_int", "scif_clk";
 671                 dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
 672                 dma-names = "tx", "rx";
 673                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 674                 status = "disabled";
 675         };
 676
 677         scif1: serial@e6e68000 {
 678                 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
 679                              "renesas,scif";
 680                 reg = <0 0xe6e68000 0 64>;
 681                 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 682                 clocks = <&mstp7_clks R8A7793_CLK_SCIF1>, <&zs_clk>,
 683                          <&scif_clk>;
 684                 clock-names = "fck", "brg_int", "scif_clk";
 685                 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
 686                 dma-names = "tx", "rx";
 687                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 688                 status = "disabled";
 689         };
 690
 691         scif2: serial@e6e58000 {
 692                 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
 693                              "renesas,scif";
 694                 reg = <0 0xe6e58000 0 64>;
 695                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 696                 clocks = <&mstp7_clks R8A7793_CLK_SCIF2>, <&zs_clk>,
 697                          <&scif_clk>;
 698                 clock-names = "fck", "brg_int", "scif_clk";
 699                 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
 700                 dma-names = "tx", "rx";
 701                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 702                 status = "disabled";
 703         };
 704
 705         scif3: serial@e6ea8000 {
 706                 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
 707                              "renesas,scif";
 708                 reg = <0 0xe6ea8000 0 64>;
 709                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 710                 clocks = <&mstp7_clks R8A7793_CLK_SCIF3>, <&zs_clk>,
 711                          <&scif_clk>;
 712                 clock-names = "fck", "brg_int", "scif_clk";
 713                 dmas = <&dmac0 0x2f>, <&dmac0 0x30>;
 714                 dma-names = "tx", "rx";
 715                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 716                 status = "disabled";
 717         };
 718
 719         scif4: serial@e6ee0000 {
 720                 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
 721                              "renesas,scif";
 722                 reg = <0 0xe6ee0000 0 64>;
 723                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 724                 clocks = <&mstp7_clks R8A7793_CLK_SCIF4>, <&zs_clk>,
 725                          <&scif_clk>;
 726                 clock-names = "fck", "brg_int", "scif_clk";
 727                 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>;
 728                 dma-names = "tx", "rx";
 729                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 730                 status = "disabled";
 731         };
 732
 733         scif5: serial@e6ee8000 {
 734                 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
 735                              "renesas,scif";
 736                 reg = <0 0xe6ee8000 0 64>;
 737                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 738                 clocks = <&mstp7_clks R8A7793_CLK_SCIF5>, <&zs_clk>,
 739                          <&scif_clk>;
 740                 clock-names = "fck", "brg_int", "scif_clk";
 741                 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>;
 742                 dma-names = "tx", "rx";
 743                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 744                 status = "disabled";
 745         };
 746
 747         hscif0: serial@e62c0000 {
 748                 compatible = "renesas,hscif-r8a7793",
 749                              "renesas,rcar-gen2-hscif", "renesas,hscif";
 750                 reg = <0 0xe62c0000 0 96>;
 751                 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 752                 clocks = <&mstp7_clks R8A7793_CLK_HSCIF0>, <&zs_clk>,
 753                          <&scif_clk>;
 754                 clock-names = "fck", "brg_int", "scif_clk";
 755                 dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
 756                 dma-names = "tx", "rx";
 757                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 758                 status = "disabled";
 759         };
 760
 761         hscif1: serial@e62c8000 {
 762                 compatible = "renesas,hscif-r8a7793",
 763                              "renesas,rcar-gen2-hscif", "renesas,hscif";
 764                 reg = <0 0xe62c8000 0 96>;
 765                 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 766                 clocks = <&mstp7_clks R8A7793_CLK_HSCIF1>, <&zs_clk>,
 767                          <&scif_clk>;
 768                 clock-names = "fck", "brg_int", "scif_clk";
 769                 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
 770                 dma-names = "tx", "rx";
 771                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 772                 status = "disabled";
 773         };
 774
 775         hscif2: serial@e62d0000 {
 776                 compatible = "renesas,hscif-r8a7793",
 777                              "renesas,rcar-gen2-hscif", "renesas,hscif";
 778                 reg = <0 0xe62d0000 0 96>;
 779                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 780                 clocks = <&mstp7_clks R8A7793_CLK_HSCIF2>, <&zs_clk>,
 781                          <&scif_clk>;
 782                 clock-names = "fck", "brg_int", "scif_clk";
 783                 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>;
 784                 dma-names = "tx", "rx";
 785                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 786                 status = "disabled";
 787         };
 788
 789         ether: ethernet@ee700000 {
 790                 compatible = "renesas,ether-r8a7793";
 791                 reg = <0 0xee700000 0 0x400>;
 792                 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
 793                 clocks = <&mstp8_clks R8A7793_CLK_ETHER>;
 794                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 795                 phy-mode = "rmii";
 796                 #address-cells = <1>;
 797                 #size-cells = <0>;
 798                 status = "disabled";
 799         };
 800
 801         qspi: spi@e6b10000 {
 802                 compatible = "renesas,qspi-r8a7793", "renesas,qspi";
 803                 reg = <0 0xe6b10000 0 0x2c>;
 804                 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 805                 clocks = <&mstp9_clks R8A7793_CLK_QSPI_MOD>;
 806                 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
 807                 dma-names = "tx", "rx";
 808                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 809                 num-cs = <1>;
 810                 #address-cells = <1>;
 811                 #size-cells = <0>;
 812                 status = "disabled";
 813         };
 814
 815         du: display@feb00000 {
 816                 compatible = "renesas,du-r8a7793";
 817                 reg = <0 0xfeb00000 0 0x40000>,
 818                       <0 0xfeb90000 0 0x1c>;
 819                 reg-names = "du", "lvds.0";
 820                 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
 821                              <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
 822                 clocks = <&mstp7_clks R8A7793_CLK_DU0>,
 823                          <&mstp7_clks R8A7793_CLK_DU1>,
 824                          <&mstp7_clks R8A7793_CLK_LVDS0>;
 825                 clock-names = "du.0", "du.1", "lvds.0";
 826                 status = "disabled";
 827
 828                 ports {
 829                         #address-cells = <1>;
 830                         #size-cells = <0>;
 831
 832                         port@0 {
 833                                 reg = <0>;
 834                                 du_out_rgb: endpoint {
 835                                 };
 836                         };
 837                         port@1 {
 838                                 reg = <1>;
 839                                 du_out_lvds0: endpoint {
 840                                 };
 841                         };
 842                 };
 843         };
 844
 845         can0: can@e6e80000 {
 846                 compatible = "renesas,can-r8a7793", "renesas,rcar-gen2-can";
 847                 reg = <0 0xe6e80000 0 0x1000>;
 848                 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
 849                 clocks = <&mstp9_clks R8A7793_CLK_RCAN0>,
 850                          <&cpg_clocks R8A7793_CLK_RCAN>, <&can_clk>;
 851                 clock-names = "clkp1", "clkp2", "can_clk";
 852                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 853                 status = "disabled";
 854         };
 855
 856         can1: can@e6e88000 {
 857                 compatible = "renesas,can-r8a7793", "renesas,rcar-gen2-can";
 858                 reg = <0 0xe6e88000 0 0x1000>;
 859                 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
 860                 clocks = <&mstp9_clks R8A7793_CLK_RCAN1>,
 861                          <&cpg_clocks R8A7793_CLK_RCAN>, <&can_clk>;
 862                 clock-names = "clkp1", "clkp2", "can_clk";
 863                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 864                 status = "disabled";
 865         };
 866
 867         clocks {
 868                 #address-cells = <2>;
 869                 #size-cells = <2>;
 870                 ranges;
 871
 872                 /* External root clock */
 873                 extal_clk: extal {
 874                         compatible = "fixed-clock";
 875                         #clock-cells = <0>;
 876                         /* This value must be overridden by the board. */
 877                         clock-frequency = <0>;
 878                 };
 879
 880                 /*
 881                  * The external audio clocks are configured as 0 Hz fixed frequency clocks by
 882                  * default. Boards that provide audio clocks should override them.
 883                  */
 884                 audio_clk_a: audio_clk_a {
 885                         compatible = "fixed-clock";
 886                         #clock-cells = <0>;
 887                         clock-frequency = <0>;
 888                 };
 889                 audio_clk_b: audio_clk_b {
 890                         compatible = "fixed-clock";
 891                         #clock-cells = <0>;
 892                         clock-frequency = <0>;
 893                 };
 894                 audio_clk_c: audio_clk_c {
 895                         compatible = "fixed-clock";
 896                         #clock-cells = <0>;
 897                         clock-frequency = <0>;
 898                 };
 899
 900                 /* External USB clock - can be overridden by the board */
 901                 usb_extal_clk: usb_extal {
 902                         compatible = "fixed-clock";
 903                         #clock-cells = <0>;
 904                         clock-frequency = <48000000>;
 905                 };
 906
 907                 /* External CAN clock */
 908                 can_clk: can {
 909                         compatible = "fixed-clock";
 910                         #clock-cells = <0>;
 911                         /* This value must be overridden by the board. */
 912                         clock-frequency = <0>;
 913                 };
 914
 915                 /* External SCIF clock */
 916                 scif_clk: scif {
 917                         compatible = "fixed-clock";
 918                         #clock-cells = <0>;
 919                         /* This value must be overridden by the board. */
 920                         clock-frequency = <0>;
 921                 };
 922
 923                 /* Special CPG clocks */
 924                 cpg_clocks: cpg_clocks@e6150000 {
 925                         compatible = "renesas,r8a7793-cpg-clocks",
 926                                      "renesas,rcar-gen2-cpg-clocks";
 927                         reg = <0 0xe6150000 0 0x1000>;
 928                         clocks = <&extal_clk &usb_extal_clk>;
 929                         #clock-cells = <1>;
 930                         clock-output-names = "main", "pll0", "pll1", "pll3",
 931                                              "lb", "qspi", "sdh", "sd0", "z",
 932                                              "rcan", "adsp";
 933                         #power-domain-cells = <0>;
 934                 };
 935
 936                 /* Variable factor clocks */
 937                 sd2_clk: sd2@e6150078 {
 938                         compatible = "renesas,r8a7793-div6-clock",
 939                                      "renesas,cpg-div6-clock";
 940                         reg = <0 0xe6150078 0 4>;
 941                         clocks = <&pll1_div2_clk>;
 942                         #clock-cells = <0>;
 943                 };
 944                 sd3_clk: sd3@e615026c {
 945                         compatible = "renesas,r8a7793-div6-clock",
 946                                      "renesas,cpg-div6-clock";
 947                         reg = <0 0xe615026c 0 4>;
 948                         clocks = <&pll1_div2_clk>;
 949                         #clock-cells = <0>;
 950                 };
 951                 mmc0_clk: mmc0@e6150240 {
 952                         compatible = "renesas,r8a7793-div6-clock",
 953                                      "renesas,cpg-div6-clock";
 954                         reg = <0 0xe6150240 0 4>;
 955                         clocks = <&pll1_div2_clk>;
 956                         #clock-cells = <0>;
 957                 };
 958
 959                 /* Fixed factor clocks */
 960                 pll1_div2_clk: pll1_div2 {
 961                         compatible = "fixed-factor-clock";
 962                         clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
 963                         #clock-cells = <0>;
 964                         clock-div = <2>;
 965                         clock-mult = <1>;
 966                 };
 967                 zg_clk: zg {
 968                         compatible = "fixed-factor-clock";
 969                         clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
 970                         #clock-cells = <0>;
 971                         clock-div = <5>;
 972                         clock-mult = <1>;
 973                 };
 974                 zx_clk: zx {
 975                         compatible = "fixed-factor-clock";
 976                         clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
 977                         #clock-cells = <0>;
 978                         clock-div = <3>;
 979                         clock-mult = <1>;
 980                 };
 981                 zs_clk: zs {
 982                         compatible = "fixed-factor-clock";
 983                         clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
 984                         #clock-cells = <0>;
 985                         clock-div = <6>;
 986                         clock-mult = <1>;
 987                 };
 988                 hp_clk: hp {
 989                         compatible = "fixed-factor-clock";
 990                         clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
 991                         #clock-cells = <0>;
 992                         clock-div = <12>;
 993                         clock-mult = <1>;
 994                 };
 995                 p_clk: p {
 996                         compatible = "fixed-factor-clock";
 997                         clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
 998                         #clock-cells = <0>;
 999                         clock-div = <24>;
1000                         clock-mult = <1>;
1001                 };
1002                 m2_clk: m2 {
1003                         compatible = "fixed-factor-clock";
1004                         clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
1005                         #clock-cells = <0>;
1006                         clock-div = <8>;
1007                         clock-mult = <1>;
1008                 };
1009                 rclk_clk: rclk {
1010                         compatible = "fixed-factor-clock";
1011                         clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
1012                         #clock-cells = <0>;
1013                         clock-div = <(48 * 1024)>;
1014                         clock-mult = <1>;
1015                 };
1016                 mp_clk: mp {
1017                         compatible = "fixed-factor-clock";
1018                         clocks = <&pll1_div2_clk>;
1019                         #clock-cells = <0>;
1020                         clock-div = <15>;
1021                         clock-mult = <1>;
1022                 };
1023                 cp_clk: cp {
1024                         compatible = "fixed-factor-clock";
1025                         clocks = <&extal_clk>;
1026                         #clock-cells = <0>;
1027                         clock-div = <2>;
1028                         clock-mult = <1>;
1029                 };
1030
1031                 /* Gate clocks */
1032                 mstp1_clks: mstp1_clks@e6150134 {
1033                         compatible = "renesas,r8a7793-mstp-clocks",
1034                                      "renesas,cpg-mstp-clocks";
1035                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
1036                         clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1037                                  <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>,
1038                                  <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
1039                                  <&zs_clk>, <&zs_clk>, <&zs_clk>;
1040                         #clock-cells = <1>;
1041                         clock-indices = <
1042                                 R8A7793_CLK_VCP0 R8A7793_CLK_VPC0
1043                                 R8A7793_CLK_SSP1 R8A7793_CLK_TMU1
1044                                 R8A7793_CLK_3DG R8A7793_CLK_2DDMAC
1045                                 R8A7793_CLK_FDP1_1 R8A7793_CLK_FDP1_0
1046                                 R8A7793_CLK_TMU3 R8A7793_CLK_TMU2
1047                                 R8A7793_CLK_CMT0 R8A7793_CLK_TMU0
1048                                 R8A7793_CLK_VSP1_DU1 R8A7793_CLK_VSP1_DU0
1049                                 R8A7793_CLK_VSP1_S
1050                         >;
1051                         clock-output-names =
1052                                 "vcp0", "vpc0", "ssp_dev", "tmu1",
1053                                 "pvrsrvkm", "tddmac", "fdp1", "fdp0",
1054                                 "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
1055                                 "vsp1-du0", "vsps";
1056                 };
1057                 mstp2_clks: mstp2_clks@e6150138 {
1058                         compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1059                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1060                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
1061                                  <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>;
1062                         #clock-cells = <1>;
1063                         clock-indices = <
1064                                 R8A7793_CLK_SCIFA2 R8A7793_CLK_SCIFA1 R8A7793_CLK_SCIFA0
1065                                 R8A7793_CLK_SCIFB0 R8A7793_CLK_SCIFB1 R8A7793_CLK_SCIFB2
1066                                 R8A7793_CLK_SYS_DMAC1 R8A7793_CLK_SYS_DMAC0
1067                         >;
1068                         clock-output-names =
1069                                 "scifa2", "scifa1", "scifa0", "scifb0",
1070                                 "scifb1", "scifb2", "sys-dmac1", "sys-dmac0";
1071                 };
1072                 mstp3_clks: mstp3_clks@e615013c {
1073                         compatible = "renesas,r8a7793-mstp-clocks",
1074                                      "renesas,cpg-mstp-clocks";
1075                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1076                         clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>,
1077                                  <&cpg_clocks R8A7793_CLK_SD0>, <&mmc0_clk>,
1078                                  <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>,
1079                                  <&rclk_clk>, <&hp_clk>, <&hp_clk>;
1080                         #clock-cells = <1>;
1081                         clock-indices = <
1082                                 R8A7793_CLK_TPU0 R8A7793_CLK_SDHI2
1083                                 R8A7793_CLK_SDHI1 R8A7793_CLK_SDHI0
1084                                 R8A7793_CLK_MMCIF0 R8A7793_CLK_IIC0
1085                                 R8A7793_CLK_PCIEC R8A7793_CLK_IIC1
1086                                 R8A7793_CLK_SSUSB R8A7793_CLK_CMT1
1087                                 R8A7793_CLK_USBDMAC0 R8A7793_CLK_USBDMAC1
1088                         >;
1089                         clock-output-names =
1090                                 "tpu0", "sdhi2", "sdhi1", "sdhi0", "mmcif0",
1091                                 "i2c7", "pciec", "i2c8", "ssusb", "cmt1",
1092                                 "usbdmac0", "usbdmac1";
1093                 };
1094                 mstp4_clks: mstp4_clks@e6150140 {
1095                         compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1096                         reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1097                         clocks = <&cp_clk>;
1098                         #clock-cells = <1>;
1099                         clock-indices = <R8A7793_CLK_IRQC>;
1100                         clock-output-names = "irqc";
1101                 };
1102                 mstp5_clks: mstp5_clks@e6150144 {
1103                         compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1104                         reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1105                         clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>;
1106                         #clock-cells = <1>;
1107                         clock-indices = <R8A7793_CLK_AUDIO_DMAC0 R8A7793_CLK_AUDIO_DMAC1
1108                                          R8A7793_CLK_THERMAL>;
1109                         clock-output-names = "audmac0", "audmac1", "thermal";
1110                 };
1111                 mstp7_clks: mstp7_clks@e615014c {
1112                         compatible = "renesas,r8a7793-mstp-clocks",
1113                                      "renesas,cpg-mstp-clocks";
1114                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
1115                         clocks = <&mp_clk>,  <&hp_clk>, <&zs_clk>, <&p_clk>,
1116                                  <&p_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1117                                  <&p_clk>, <&p_clk>, <&p_clk>, <&zx_clk>,
1118                                  <&zx_clk>, <&zx_clk>;
1119                         #clock-cells = <1>;
1120                         clock-indices = <
1121                                 R8A7793_CLK_EHCI R8A7793_CLK_HSUSB
1122                                 R8A7793_CLK_HSCIF2 R8A7793_CLK_SCIF5
1123                                 R8A7793_CLK_SCIF4 R8A7793_CLK_HSCIF1
1124                                 R8A7793_CLK_HSCIF0 R8A7793_CLK_SCIF3
1125                                 R8A7793_CLK_SCIF2 R8A7793_CLK_SCIF1
1126                                 R8A7793_CLK_SCIF0 R8A7793_CLK_DU1
1127                                 R8A7793_CLK_DU0 R8A7793_CLK_LVDS0
1128                         >;
1129                         clock-output-names =
1130                                 "ehci", "hsusb", "hscif2", "scif5", "scif4",
1131                                 "hscif1", "hscif0", "scif3", "scif2",
1132                                 "scif1", "scif0", "du1", "du0", "lvds0";
1133                 };
1134                 mstp8_clks: mstp8_clks@e6150990 {
1135                         compatible = "renesas,r8a7793-mstp-clocks",
1136                                      "renesas,cpg-mstp-clocks";
1137                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1138                         clocks = <&zx_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
1139                                  <&p_clk>, <&zs_clk>, <&zs_clk>;
1140                         #clock-cells = <1>;
1141                         clock-indices = <
1142                                 R8A7793_CLK_IPMMU_SGX R8A7793_CLK_VIN2
1143                                 R8A7793_CLK_VIN1 R8A7793_CLK_VIN0
1144                                 R8A7793_CLK_ETHER R8A7793_CLK_SATA1
1145                                 R8A7793_CLK_SATA0
1146                         >;
1147                         clock-output-names =
1148                                 "ipmmu_sgx", "vin2", "vin1", "vin0", "ether",
1149                                 "sata1", "sata0";
1150                 };
1151                 mstp9_clks: mstp9_clks@e6150994 {
1152                         compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1153                         reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
1154                         clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1155                                  <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1156                                  <&p_clk>, <&p_clk>,
1157                                  <&cpg_clocks R8A7793_CLK_QSPI>, <&hp_clk>,
1158                                  <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
1159                                  <&hp_clk>, <&hp_clk>;
1160                         #clock-cells = <1>;
1161                         clock-indices = <
1162                                 R8A7793_CLK_GPIO7 R8A7793_CLK_GPIO6
1163                                 R8A7793_CLK_GPIO5 R8A7793_CLK_GPIO4
1164                                 R8A7793_CLK_GPIO3 R8A7793_CLK_GPIO2
1165                                 R8A7793_CLK_GPIO1 R8A7793_CLK_GPIO0
1166                                 R8A7793_CLK_QSPI_MOD R8A7793_CLK_RCAN1
1167                                 R8A7793_CLK_RCAN0 R8A7793_CLK_I2C5
1168                                 R8A7793_CLK_IICDVFS R8A7793_CLK_I2C4
1169                                 R8A7793_CLK_I2C3 R8A7793_CLK_I2C2
1170                                 R8A7793_CLK_I2C1 R8A7793_CLK_I2C0
1171                         >;
1172                         clock-output-names =
1173                                 "gpio7", "gpio6", "gpio5", "gpio4",
1174                                 "gpio3", "gpio2", "gpio1", "gpio0",
1175                                 "rcan1", "rcan0", "qspi_mod", "i2c5",
1176                                 "i2c6", "i2c4", "i2c3", "i2c2", "i2c1",
1177                                 "i2c0";
1178                 };
1179                 mstp10_clks: mstp10_clks@e6150998 {
1180                         compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1181                         reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1182                         clocks = <&p_clk>,
1183                                 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1184                                 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1185                                 <&p_clk>,
1186                                 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1187                                 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1188                                 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1189                                 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1190                                 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1191                                 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1192                                 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>;
1193
1194                         #clock-cells = <1>;
1195                         clock-indices = <
1196                                 R8A7793_CLK_SSI_ALL
1197                                 R8A7793_CLK_SSI9 R8A7793_CLK_SSI8 R8A7793_CLK_SSI7 R8A7793_CLK_SSI6 R8A7793_CLK_SSI5
1198                                 R8A7793_CLK_SSI4 R8A7793_CLK_SSI3 R8A7793_CLK_SSI2 R8A7793_CLK_SSI1 R8A7793_CLK_SSI0
1199                                 R8A7793_CLK_SCU_ALL
1200                                 R8A7793_CLK_SCU_DVC1 R8A7793_CLK_SCU_DVC0
1201                                 R8A7793_CLK_SCU_CTU1_MIX1 R8A7793_CLK_SCU_CTU0_MIX0
1202                                 R8A7793_CLK_SCU_SRC9 R8A7793_CLK_SCU_SRC8 R8A7793_CLK_SCU_SRC7 R8A7793_CLK_SCU_SRC6 R8A7793_CLK_SCU_SRC5
1203                                 R8A7793_CLK_SCU_SRC4 R8A7793_CLK_SCU_SRC3 R8A7793_CLK_SCU_SRC2 R8A7793_CLK_SCU_SRC1 R8A7793_CLK_SCU_SRC0
1204                         >;
1205                         clock-output-names =
1206                                 "ssi-all",
1207                                 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
1208                                 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
1209                                 "scu-all",
1210                                 "scu-dvc1", "scu-dvc0",
1211                                 "scu-ctu1-mix1", "scu-ctu0-mix0",
1212                                 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
1213                                 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
1214                 };
1215                 mstp11_clks: mstp11_clks@e615099c {
1216                         compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1217                         reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
1218                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
1219                         #clock-cells = <1>;
1220                         clock-indices = <
1221                                 R8A7793_CLK_SCIFA3 R8A7793_CLK_SCIFA4 R8A7793_CLK_SCIFA5
1222                         >;
1223                         clock-output-names = "scifa3", "scifa4", "scifa5";
1224                 };
1225         };
1226
1227         sysc: system-controller@e6180000 {
1228                 compatible = "renesas,r8a7793-sysc";
1229                 reg = <0 0xe6180000 0 0x0200>;
1230                 #power-domain-cells = <1>;
1231         };
1232
1233         ipmmu_sy0: mmu@e6280000 {
1234                 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1235                 reg = <0 0xe6280000 0 0x1000>;
1236                 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
1237                              <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
1238                 #iommu-cells = <1>;
1239                 status = "disabled";
1240         };
1241
1242         ipmmu_sy1: mmu@e6290000 {
1243                 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1244                 reg = <0 0xe6290000 0 0x1000>;
1245                 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1246                 #iommu-cells = <1>;
1247                 status = "disabled";
1248         };
1249
1250         ipmmu_ds: mmu@e6740000 {
1251                 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1252                 reg = <0 0xe6740000 0 0x1000>;
1253                 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1254                              <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1255                 #iommu-cells = <1>;
1256                 status = "disabled";
1257         };
1258
1259         ipmmu_mp: mmu@ec680000 {
1260                 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1261                 reg = <0 0xec680000 0 0x1000>;
1262                 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1263                 #iommu-cells = <1>;
1264                 status = "disabled";
1265         };
1266
1267         ipmmu_mx: mmu@fe951000 {
1268                 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1269                 reg = <0 0xfe951000 0 0x1000>;
1270                 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
1271                              <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1272                 #iommu-cells = <1>;
1273                 status = "disabled";
1274         };
1275
1276         ipmmu_rt: mmu@ffc80000 {
1277                 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1278                 reg = <0 0xffc80000 0 0x1000>;
1279                 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1280                 #iommu-cells = <1>;
1281                 status = "disabled";
1282         };
1283
1284         ipmmu_gp: mmu@e62a0000 {
1285                 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1286                 reg = <0 0xe62a0000 0 0x1000>;
1287                 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1288                              <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
1289                 #iommu-cells = <1>;
1290                 status = "disabled";
1291         };
1292
1293         rcar_sound: sound@ec500000 {
1294                 /*
1295                  * #sound-dai-cells is required
1296                  *
1297                  * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
1298                  * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
1299                  */
1300                 compatible =  "renesas,rcar_sound-r8a7793", "renesas,rcar_sound-gen2";
1301                 reg =   <0 0xec500000 0 0x1000>, /* SCU */
1302                         <0 0xec5a0000 0 0x100>,  /* ADG */
1303                         <0 0xec540000 0 0x1000>, /* SSIU */
1304                         <0 0xec541000 0 0x280>,  /* SSI */
1305                         <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
1306                 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1307
1308                 clocks = <&mstp10_clks R8A7793_CLK_SSI_ALL>,
1309                         <&mstp10_clks R8A7793_CLK_SSI9>, <&mstp10_clks R8A7793_CLK_SSI8>,
1310                         <&mstp10_clks R8A7793_CLK_SSI7>, <&mstp10_clks R8A7793_CLK_SSI6>,
1311                         <&mstp10_clks R8A7793_CLK_SSI5>, <&mstp10_clks R8A7793_CLK_SSI4>,
1312                         <&mstp10_clks R8A7793_CLK_SSI3>, <&mstp10_clks R8A7793_CLK_SSI2>,
1313                         <&mstp10_clks R8A7793_CLK_SSI1>, <&mstp10_clks R8A7793_CLK_SSI0>,
1314                         <&mstp10_clks R8A7793_CLK_SCU_SRC9>, <&mstp10_clks R8A7793_CLK_SCU_SRC8>,
1315                         <&mstp10_clks R8A7793_CLK_SCU_SRC7>, <&mstp10_clks R8A7793_CLK_SCU_SRC6>,
1316                         <&mstp10_clks R8A7793_CLK_SCU_SRC5>, <&mstp10_clks R8A7793_CLK_SCU_SRC4>,
1317                         <&mstp10_clks R8A7793_CLK_SCU_SRC3>, <&mstp10_clks R8A7793_CLK_SCU_SRC2>,
1318                         <&mstp10_clks R8A7793_CLK_SCU_SRC1>, <&mstp10_clks R8A7793_CLK_SCU_SRC0>,
1319                         <&mstp10_clks R8A7793_CLK_SCU_DVC0>, <&mstp10_clks R8A7793_CLK_SCU_DVC1>,
1320                         <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1321                 clock-names = "ssi-all",
1322                                 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1323                                 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1324                                 "src.9", "src.8", "src.7", "src.6", "src.5",
1325                                 "src.4", "src.3", "src.2", "src.1", "src.0",
1326                                 "dvc.0", "dvc.1",
1327                                 "clk_a", "clk_b", "clk_c", "clk_i";
1328                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
1329
1330                 status = "disabled";
1331
1332                 rcar_sound,dvc {
1333                         dvc0: dvc@0 {
1334                                 dmas = <&audma0 0xbc>;
1335                                 dma-names = "tx";
1336                         };
1337                         dvc1: dvc@1 {
1338                                 dmas = <&audma0 0xbe>;
1339                                 dma-names = "tx";
1340                         };
1341                 };
1342
1343                 rcar_sound,src {
1344                         src0: src@0 {
1345                                 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1346                                 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1347                                 dma-names = "rx", "tx";
1348                         };
1349                         src1: src@1 {
1350                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1351                                 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1352                                 dma-names = "rx", "tx";
1353                         };
1354                         src2: src@2 {
1355                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1356                                 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1357                                 dma-names = "rx", "tx";
1358                         };
1359                         src3: src@3 {
1360                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1361                                 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1362                                 dma-names = "rx", "tx";
1363                         };
1364                         src4: src@4 {
1365                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1366                                 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1367                                 dma-names = "rx", "tx";
1368                         };
1369                         src5: src@5 {
1370                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1371                                 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1372                                 dma-names = "rx", "tx";
1373                         };
1374                         src6: src@6 {
1375                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1376                                 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1377                                 dma-names = "rx", "tx";
1378                         };
1379                         src7: src@7 {
1380                                 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1381                                 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1382                                 dma-names = "rx", "tx";
1383                         };
1384                         src8: src@8 {
1385                                 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1386                                 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1387                                 dma-names = "rx", "tx";
1388                         };
1389                         src9: src@9 {
1390                                 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1391                                 dmas = <&audma0 0x97>, <&audma1 0xba>;
1392                                 dma-names = "rx", "tx";
1393                         };
1394                 };
1395
1396                 rcar_sound,ssi {
1397                         ssi0: ssi@0 {
1398                                 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1399                                 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
1400                                 dma-names = "rx", "tx", "rxu", "txu";
1401                         };
1402                         ssi1: ssi@1 {
1403                                  interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1404                                 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
1405                                 dma-names = "rx", "tx", "rxu", "txu";
1406                         };
1407                         ssi2: ssi@2 {
1408                                 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1409                                 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
1410                                 dma-names = "rx", "tx", "rxu", "txu";
1411                         };
1412                         ssi3: ssi@3 {
1413                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1414                                 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
1415                                 dma-names = "rx", "tx", "rxu", "txu";
1416                         };
1417                         ssi4: ssi@4 {
1418                                 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1419                                 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
1420                                 dma-names = "rx", "tx", "rxu", "txu";
1421                         };
1422                         ssi5: ssi@5 {
1423                                 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1424                                 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
1425                                 dma-names = "rx", "tx", "rxu", "txu";
1426                         };
1427                         ssi6: ssi@6 {
1428                                 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1429                                 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
1430                                 dma-names = "rx", "tx", "rxu", "txu";
1431                         };
1432                         ssi7: ssi@7 {
1433                                 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1434                                 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
1435                                 dma-names = "rx", "tx", "rxu", "txu";
1436                         };
1437                         ssi8: ssi@8 {
1438                                 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1439                                 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
1440                                 dma-names = "rx", "tx", "rxu", "txu";
1441                         };
1442                         ssi9: ssi@9 {
1443                                 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1444                                 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
1445                                 dma-names = "rx", "tx", "rxu", "txu";
1446                         };
1447                 };
1448         };
1449 };