arch/arm/boot/dts/r8a7792.dtsi

   1 /*
   2  * Device Tree Source for the r8a7792 SoC
   3  *
   4  * Copyright (C) 2016 Cogent Embedded Inc.
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 #include <dt-bindings/clock/r8a7792-clock.h>
  12 #include <dt-bindings/interrupt-controller/irq.h>
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/power/r8a7792-sysc.h>
  15
  16 / {
  17         compatible = "renesas,r8a7792";
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20
  21         aliases {
  22                 i2c0 = &i2c0;
  23                 i2c1 = &i2c1;
  24                 i2c2 = &i2c2;
  25                 i2c3 = &i2c3;
  26                 i2c4 = &i2c4;
  27                 i2c5 = &i2c5;
  28                 spi0 = &qspi;
  29                 vin0 = &vin0;
  30                 vin1 = &vin1;
  31                 vin2 = &vin2;
  32                 vin3 = &vin3;
  33                 vin4 = &vin4;
  34                 vin5 = &vin5;
  35         };
  36
  37         cpus {
  38                 #address-cells = <1>;
  39                 #size-cells = <0>;
  40                 enable-method = "renesas,apmu";
  41
  42                 cpu0: cpu@0 {
  43                         device_type = "cpu";
  44                         compatible = "arm,cortex-a15";
  45                         reg = <0>;
  46                         clock-frequency = <1000000000>;
  47                         clocks = <&cpg_clocks R8A7792_CLK_Z>;
  48                         power-domains = <&sysc R8A7792_PD_CA15_CPU0>;
  49                         next-level-cache = <&L2_CA15>;
  50                 };
  51
  52                 cpu1: cpu@1 {
  53                         device_type = "cpu";
  54                         compatible = "arm,cortex-a15";
  55                         reg = <1>;
  56                         clock-frequency = <1000000000>;
  57                         power-domains = <&sysc R8A7792_PD_CA15_CPU1>;
  58                         next-level-cache = <&L2_CA15>;
  59                 };
  60
  61                 L2_CA15: cache-controller@0 {
  62                         compatible = "cache";
  63                         reg = <0>;
  64                         cache-unified;
  65                         cache-level = <2>;
  66                         power-domains = <&sysc R8A7792_PD_CA15_SCU>;
  67                 };
  68         };
  69
  70         soc {
  71                 compatible = "simple-bus";
  72                 interrupt-parent = <&gic>;
  73
  74                 #address-cells = <2>;
  75                 #size-cells = <2>;
  76                 ranges;
  77
  78                 apmu@e6152000 {
  79                         compatible = "renesas,r8a7792-apmu", "renesas,apmu";
  80                         reg = <0 0xe6152000 0 0x188>;
  81                         cpus = <&cpu0 &cpu1>;
  82                 };
  83
  84                 gic: interrupt-controller@f1001000 {
  85                         compatible = "arm,gic-400";
  86                         #interrupt-cells = <3>;
  87                         interrupt-controller;
  88                         reg = <0 0xf1001000 0 0x1000>,
  89                               <0 0xf1002000 0 0x1000>,
  90                               <0 0xf1004000 0 0x2000>,
  91                               <0 0xf1006000 0 0x2000>;
  92                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
  93                                       IRQ_TYPE_LEVEL_HIGH)>;
  94                 };
  95
  96                 irqc: interrupt-controller@e61c0000 {
  97                         compatible = "renesas,irqc-r8a7792", "renesas,irqc";
  98                         #interrupt-cells = <2>;
  99                         interrupt-controller;
 100                         reg = <0 0xe61c0000 0 0x200>;
 101                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 102                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 103                                      <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 104                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 105                         clocks = <&mstp4_clks R8A7792_CLK_IRQC>;
 106                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 107                 };
 108
 109                 timer {
 110                         compatible = "arm,armv7-timer";
 111                         interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
 112                                       IRQ_TYPE_LEVEL_LOW)>,
 113                                      <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
 114                                       IRQ_TYPE_LEVEL_LOW)>,
 115                                      <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
 116                                       IRQ_TYPE_LEVEL_LOW)>,
 117                                      <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
 118                                       IRQ_TYPE_LEVEL_LOW)>;
 119                 };
 120
 121                 rst: reset-controller@e6160000 {
 122                         compatible = "renesas,r8a7792-rst";
 123                         reg = <0 0xe6160000 0 0x0100>;
 124                 };
 125
 126                 sysc: system-controller@e6180000 {
 127                         compatible = "renesas,r8a7792-sysc";
 128                         reg = <0 0xe6180000 0 0x0200>;
 129                         #power-domain-cells = <1>;
 130                 };
 131
 132                 pfc: pin-controller@e6060000 {
 133                         compatible = "renesas,pfc-r8a7792";
 134                         reg = <0 0xe6060000 0 0x144>;
 135                 };
 136
 137                 gpio0: gpio@e6050000 {
 138                         compatible = "renesas,gpio-r8a7792",
 139                                      "renesas,gpio-rcar";
 140                         reg = <0 0xe6050000 0 0x50>;
 141                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 142                         #gpio-cells = <2>;
 143                         gpio-controller;
 144                         gpio-ranges = <&pfc 0 0 29>;
 145                         #interrupt-cells = <2>;
 146                         interrupt-controller;
 147                         clocks = <&mstp9_clks R8A7792_CLK_GPIO0>;
 148                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 149                 };
 150
 151                 gpio1: gpio@e6051000 {
 152                         compatible = "renesas,gpio-r8a7792",
 153                                      "renesas,gpio-rcar";
 154                         reg = <0 0xe6051000 0 0x50>;
 155                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 156                         #gpio-cells = <2>;
 157                         gpio-controller;
 158                         gpio-ranges = <&pfc 0 32 23>;
 159                         #interrupt-cells = <2>;
 160                         interrupt-controller;
 161                         clocks = <&mstp9_clks R8A7792_CLK_GPIO1>;
 162                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 163                 };
 164
 165                 gpio2: gpio@e6052000 {
 166                         compatible = "renesas,gpio-r8a7792",
 167                                      "renesas,gpio-rcar";
 168                         reg = <0 0xe6052000 0 0x50>;
 169                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 170                         #gpio-cells = <2>;
 171                         gpio-controller;
 172                         gpio-ranges = <&pfc 0 64 32>;
 173                         #interrupt-cells = <2>;
 174                         interrupt-controller;
 175                         clocks = <&mstp9_clks R8A7792_CLK_GPIO2>;
 176                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 177                 };
 178
 179                 gpio3: gpio@e6053000 {
 180                         compatible = "renesas,gpio-r8a7792",
 181                                      "renesas,gpio-rcar";
 182                         reg = <0 0xe6053000 0 0x50>;
 183                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 184                         #gpio-cells = <2>;
 185                         gpio-controller;
 186                         gpio-ranges = <&pfc 0 96 28>;
 187                         #interrupt-cells = <2>;
 188                         interrupt-controller;
 189                         clocks = <&mstp9_clks R8A7792_CLK_GPIO3>;
 190                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 191                 };
 192
 193                 gpio4: gpio@e6054000 {
 194                         compatible = "renesas,gpio-r8a7792",
 195                                      "renesas,gpio-rcar";
 196                         reg = <0 0xe6054000 0 0x50>;
 197                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 198                         #gpio-cells = <2>;
 199                         gpio-controller;
 200                         gpio-ranges = <&pfc 0 128 17>;
 201                         #interrupt-cells = <2>;
 202                         interrupt-controller;
 203                         clocks = <&mstp9_clks R8A7792_CLK_GPIO4>;
 204                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 205                 };
 206
 207                 gpio5: gpio@e6055000 {
 208                         compatible = "renesas,gpio-r8a7792",
 209                                      "renesas,gpio-rcar";
 210                         reg = <0 0xe6055000 0 0x50>;
 211                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 212                         #gpio-cells = <2>;
 213                         gpio-controller;
 214                         gpio-ranges = <&pfc 0 160 17>;
 215                         #interrupt-cells = <2>;
 216                         interrupt-controller;
 217                         clocks = <&mstp9_clks R8A7792_CLK_GPIO5>;
 218                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 219                 };
 220
 221                 gpio6: gpio@e6055100 {
 222                         compatible = "renesas,gpio-r8a7792",
 223                                      "renesas,gpio-rcar";
 224                         reg = <0 0xe6055100 0 0x50>;
 225                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 226                         #gpio-cells = <2>;
 227                         gpio-controller;
 228                         gpio-ranges = <&pfc 0 192 17>;
 229                         #interrupt-cells = <2>;
 230                         interrupt-controller;
 231                         clocks = <&mstp9_clks R8A7792_CLK_GPIO6>;
 232                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 233                 };
 234
 235                 gpio7: gpio@e6055200 {
 236                         compatible = "renesas,gpio-r8a7792",
 237                                      "renesas,gpio-rcar";
 238                         reg = <0 0xe6055200 0 0x50>;
 239                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 240                         #gpio-cells = <2>;
 241                         gpio-controller;
 242                         gpio-ranges = <&pfc 0 224 17>;
 243                         #interrupt-cells = <2>;
 244                         interrupt-controller;
 245                         clocks = <&mstp9_clks R8A7792_CLK_GPIO7>;
 246                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 247                 };
 248
 249                 gpio8: gpio@e6055300 {
 250                         compatible = "renesas,gpio-r8a7792",
 251                                      "renesas,gpio-rcar";
 252                         reg = <0 0xe6055300 0 0x50>;
 253                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 254                         #gpio-cells = <2>;
 255                         gpio-controller;
 256                         gpio-ranges = <&pfc 0 256 17>;
 257                         #interrupt-cells = <2>;
 258                         interrupt-controller;
 259                         clocks = <&mstp9_clks R8A7792_CLK_GPIO8>;
 260                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 261                 };
 262
 263                 gpio9: gpio@e6055400 {
 264                         compatible = "renesas,gpio-r8a7792",
 265                                      "renesas,gpio-rcar";
 266                         reg = <0 0xe6055400 0 0x50>;
 267                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 268                         #gpio-cells = <2>;
 269                         gpio-controller;
 270                         gpio-ranges = <&pfc 0 288 17>;
 271                         #interrupt-cells = <2>;
 272                         interrupt-controller;
 273                         clocks = <&mstp9_clks R8A7792_CLK_GPIO9>;
 274                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 275                 };
 276
 277                 gpio10: gpio@e6055500 {
 278                         compatible = "renesas,gpio-r8a7792",
 279                                      "renesas,gpio-rcar";
 280                         reg = <0 0xe6055500 0 0x50>;
 281                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 282                         #gpio-cells = <2>;
 283                         gpio-controller;
 284                         gpio-ranges = <&pfc 0 320 32>;
 285                         #interrupt-cells = <2>;
 286                         interrupt-controller;
 287                         clocks = <&mstp9_clks R8A7792_CLK_GPIO10>;
 288                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 289                 };
 290
 291                 gpio11: gpio@e6055600 {
 292                         compatible = "renesas,gpio-r8a7792",
 293                                      "renesas,gpio-rcar";
 294                         reg = <0 0xe6055600 0 0x50>;
 295                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 296                         #gpio-cells = <2>;
 297                         gpio-controller;
 298                         gpio-ranges = <&pfc 0 352 30>;
 299                         #interrupt-cells = <2>;
 300                         interrupt-controller;
 301                         clocks = <&mstp9_clks R8A7792_CLK_GPIO11>;
 302                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 303                 };
 304
 305                 dmac0: dma-controller@e6700000 {
 306                         compatible = "renesas,dmac-r8a7792",
 307                                      "renesas,rcar-dmac";
 308                         reg = <0 0xe6700000 0 0x20000>;
 309                         interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
 310                                       GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
 311                                       GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
 312                                       GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
 313                                       GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
 314                                       GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
 315                                       GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
 316                                       GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
 317                                       GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
 318                                       GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
 319                                       GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
 320                                       GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
 321                                       GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
 322                                       GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
 323                                       GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
 324                                       GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
 325                         interrupt-names = "error",
 326                                           "ch0", "ch1", "ch2", "ch3",
 327                                           "ch4", "ch5", "ch6", "ch7",
 328                                           "ch8", "ch9", "ch10", "ch11",
 329                                           "ch12", "ch13", "ch14";
 330                         clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC0>;
 331                         clock-names = "fck";
 332                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 333                         #dma-cells = <1>;
 334                         dma-channels = <15>;
 335                 };
 336
 337                 dmac1: dma-controller@e6720000 {
 338                         compatible = "renesas,dmac-r8a7792",
 339                                      "renesas,rcar-dmac";
 340                         reg = <0 0xe6720000 0 0x20000>;
 341                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
 342                                       GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
 343                                       GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
 344                                       GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
 345                                       GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
 346                                       GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
 347                                       GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
 348                                       GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
 349                                       GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
 350                                       GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
 351                                       GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
 352                                       GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
 353                                       GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
 354                                       GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
 355                                       GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
 356                                       GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
 357                         interrupt-names = "error",
 358                                           "ch0", "ch1", "ch2", "ch3",
 359                                           "ch4", "ch5", "ch6", "ch7",
 360                                           "ch8", "ch9", "ch10", "ch11",
 361                                           "ch12", "ch13", "ch14";
 362                         clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC1>;
 363                         clock-names = "fck";
 364                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 365                         #dma-cells = <1>;
 366                         dma-channels = <15>;
 367                 };
 368
 369                 scif0: serial@e6e60000 {
 370                         compatible = "renesas,scif-r8a7792",
 371                                      "renesas,rcar-gen2-scif", "renesas,scif";
 372                         reg = <0 0xe6e60000 0 64>;
 373                         interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 374                         clocks = <&mstp7_clks R8A7792_CLK_SCIF0>, <&zs_clk>,
 375                                  <&scif_clk>;
 376                         clock-names = "fck", "brg_int", "scif_clk";
 377                         dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
 378                                <&dmac1 0x29>, <&dmac1 0x2a>;
 379                         dma-names = "tx", "rx", "tx", "rx";
 380                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 381                         status = "disabled";
 382                 };
 383
 384                 scif1: serial@e6e68000 {
 385                         compatible = "renesas,scif-r8a7792",
 386                                      "renesas,rcar-gen2-scif", "renesas,scif";
 387                         reg = <0 0xe6e68000 0 64>;
 388                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 389                         clocks = <&mstp7_clks R8A7792_CLK_SCIF1>, <&zs_clk>,
 390                                  <&scif_clk>;
 391                         clock-names = "fck", "brg_int", "scif_clk";
 392                         dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
 393                                <&dmac1 0x2d>, <&dmac1 0x2e>;
 394                         dma-names = "tx", "rx", "tx", "rx";
 395                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 396                         status = "disabled";
 397                 };
 398
 399                 scif2: serial@e6e58000 {
 400                         compatible = "renesas,scif-r8a7792",
 401                                      "renesas,rcar-gen2-scif", "renesas,scif";
 402                         reg = <0 0xe6e58000 0 64>;
 403                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 404                         clocks = <&mstp7_clks R8A7792_CLK_SCIF2>, <&zs_clk>,
 405                                  <&scif_clk>;
 406                         clock-names = "fck", "brg_int", "scif_clk";
 407                         dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
 408                                <&dmac1 0x2b>, <&dmac1 0x2c>;
 409                         dma-names = "tx", "rx", "tx", "rx";
 410                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 411                         status = "disabled";
 412                 };
 413
 414                 scif3: serial@e6ea8000 {
 415                         compatible = "renesas,scif-r8a7792",
 416                                      "renesas,rcar-gen2-scif", "renesas,scif";
 417                         reg = <0 0xe6ea8000 0 64>;
 418                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 419                         clocks = <&mstp7_clks R8A7792_CLK_SCIF3>, <&zs_clk>,
 420                                  <&scif_clk>;
 421                         clock-names = "fck", "brg_int", "scif_clk";
 422                         dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
 423                                <&dmac1 0x2f>, <&dmac1 0x30>;
 424                         dma-names = "tx", "rx", "tx", "rx";
 425                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 426                         status = "disabled";
 427                 };
 428
 429                 hscif0: serial@e62c0000 {
 430                         compatible = "renesas,hscif-r8a7792",
 431                                      "renesas,rcar-gen2-hscif", "renesas,hscif";
 432                         reg = <0 0xe62c0000 0 96>;
 433                         interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 434                         clocks = <&mstp7_clks R8A7792_CLK_HSCIF0>, <&zs_clk>,
 435                                  <&scif_clk>;
 436                         clock-names = "fck", "brg_int", "scif_clk";
 437                         dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
 438                                <&dmac1 0x39>, <&dmac1 0x3a>;
 439                         dma-names = "tx", "rx", "tx", "rx";
 440                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 441                         status = "disabled";
 442                 };
 443
 444                 hscif1: serial@e62c8000 {
 445                         compatible = "renesas,hscif-r8a7792",
 446                                      "renesas,rcar-gen2-hscif", "renesas,hscif";
 447                         reg = <0 0xe62c8000 0 96>;
 448                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 449                         clocks = <&mstp7_clks R8A7792_CLK_HSCIF1>, <&zs_clk>,
 450                                  <&scif_clk>;
 451                         clock-names = "fck", "brg_int", "scif_clk";
 452                         dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
 453                                <&dmac1 0x4d>, <&dmac1 0x4e>;
 454                         dma-names = "tx", "rx", "tx", "rx";
 455                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 456                         status = "disabled";
 457                 };
 458
 459                 sdhi0: sd@ee100000 {
 460                         compatible = "renesas,sdhi-r8a7792";
 461                         reg = <0 0xee100000 0 0x328>;
 462                         interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
 463                         dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
 464                                <&dmac1 0xcd>, <&dmac1 0xce>;
 465                         dma-names = "tx", "rx", "tx", "rx";
 466                         clocks = <&mstp3_clks R8A7792_CLK_SDHI0>;
 467                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 468                         status = "disabled";
 469                 };
 470
 471                 jpu: jpeg-codec@fe980000 {
 472                         compatible = "renesas,jpu-r8a7792",
 473                                      "renesas,rcar-gen2-jpu";
 474                         reg = <0 0xfe980000 0 0x10300>;
 475                         interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
 476                         clocks = <&mstp1_clks R8A7792_CLK_JPU>;
 477                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 478                 };
 479
 480                 avb: ethernet@e6800000 {
 481                         compatible = "renesas,etheravb-r8a7792",
 482                                      "renesas,etheravb-rcar-gen2";
 483                         reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
 484                         interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
 485                         clocks = <&mstp8_clks R8A7792_CLK_ETHERAVB>;
 486                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 487                         #address-cells = <1>;
 488                         #size-cells = <0>;
 489                         status = "disabled";
 490                 };
 491
 492                 /* I2C doesn't need pinmux */
 493                 i2c0: i2c@e6508000 {
 494                         compatible = "renesas,i2c-r8a7792";
 495                         reg = <0 0xe6508000 0 0x40>;
 496                         interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
 497                         clocks = <&mstp9_clks R8A7792_CLK_I2C0>;
 498                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 499                         i2c-scl-internal-delay-ns = <6>;
 500                         #address-cells = <1>;
 501                         #size-cells = <0>;
 502                         status = "disabled";
 503                 };
 504
 505                 i2c1: i2c@e6518000 {
 506                         compatible = "renesas,i2c-r8a7792";
 507                         reg = <0 0xe6518000 0 0x40>;
 508                         interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
 509                         clocks = <&mstp9_clks R8A7792_CLK_I2C1>;
 510                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 511                         i2c-scl-internal-delay-ns = <6>;
 512                         #address-cells = <1>;
 513                         #size-cells = <0>;
 514                         status = "disabled";
 515                 };
 516
 517                 i2c2: i2c@e6530000 {
 518                         compatible = "renesas,i2c-r8a7792";
 519                         reg = <0 0xe6530000 0 0x40>;
 520                         interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
 521                         clocks = <&mstp9_clks R8A7792_CLK_I2C2>;
 522                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 523                         i2c-scl-internal-delay-ns = <6>;
 524                         #address-cells = <1>;
 525                         #size-cells = <0>;
 526                         status = "disabled";
 527                 };
 528
 529                 i2c3: i2c@e6540000 {
 530                         compatible = "renesas,i2c-r8a7792";
 531                         reg = <0 0xe6540000 0 0x40>;
 532                         interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
 533                         clocks = <&mstp9_clks R8A7792_CLK_I2C3>;
 534                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 535                         i2c-scl-internal-delay-ns = <6>;
 536                         #address-cells = <1>;
 537                         #size-cells = <0>;
 538                         status = "disabled";
 539                 };
 540
 541                 i2c4: i2c@e6520000 {
 542                         compatible = "renesas,i2c-r8a7792";
 543                         reg = <0 0xe6520000 0 0x40>;
 544                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 545                         clocks = <&mstp9_clks R8A7792_CLK_I2C4>;
 546                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 547                         i2c-scl-internal-delay-ns = <6>;
 548                         #address-cells = <1>;
 549                         #size-cells = <0>;
 550                         status = "disabled";
 551                 };
 552
 553                 i2c5: i2c@e6528000 {
 554                         compatible = "renesas,i2c-r8a7792";
 555                         reg = <0 0xe6528000 0 0x40>;
 556                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 557                         clocks = <&mstp9_clks R8A7792_CLK_I2C5>;
 558                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 559                         i2c-scl-internal-delay-ns = <110>;
 560                         #address-cells = <1>;
 561                         #size-cells = <0>;
 562                         status = "disabled";
 563                 };
 564
 565                 qspi: spi@e6b10000 {
 566                         compatible = "renesas,qspi-r8a7792", "renesas,qspi";
 567                         reg = <0 0xe6b10000 0 0x2c>;
 568                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 569                         clocks = <&mstp9_clks R8A7792_CLK_QSPI_MOD>;
 570                         dmas = <&dmac0 0x17>, <&dmac0 0x18>,
 571                                <&dmac1 0x17>, <&dmac1 0x18>;
 572                         dma-names = "tx", "rx", "tx", "rx";
 573                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 574                         num-cs = <1>;
 575                         #address-cells = <1>;
 576                         #size-cells = <0>;
 577                         status = "disabled";
 578                 };
 579
 580                 du: display@feb00000 {
 581                         compatible = "renesas,du-r8a7792";
 582                         reg = <0 0xfeb00000 0 0x40000>;
 583                         reg-names = "du";
 584                         interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
 585                                      <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
 586                         clocks = <&mstp7_clks R8A7792_CLK_DU0>,
 587                                  <&mstp7_clks R8A7792_CLK_DU1>;
 588                         clock-names = "du.0", "du.1";
 589                         status = "disabled";
 590
 591                         ports {
 592                                 #address-cells = <1>;
 593                                 #size-cells = <0>;
 594
 595                                 port@0 {
 596                                         reg = <0>;
 597                                         du_out_rgb0: endpoint {
 598                                         };
 599                                 };
 600                                 port@1 {
 601                                         reg = <1>;
 602                                         du_out_rgb1: endpoint {
 603                                         };
 604                                 };
 605                         };
 606                 };
 607
 608                 can0: can@e6e80000 {
 609                         compatible = "renesas,can-r8a7792",
 610                                      "renesas,rcar-gen2-can";
 611                         reg = <0 0xe6e80000 0 0x1000>;
 612                         interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
 613                         clocks = <&mstp9_clks R8A7792_CLK_CAN0>,
 614                                  <&rcan_clk>, <&can_clk>;
 615                         clock-names = "clkp1", "clkp2", "can_clk";
 616                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 617                         status = "disabled";
 618                 };
 619
 620                 can1: can@e6e88000 {
 621                         compatible = "renesas,can-r8a7792",
 622                                      "renesas,rcar-gen2-can";
 623                         reg = <0 0xe6e88000 0 0x1000>;
 624                         interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
 625                         clocks = <&mstp9_clks R8A7792_CLK_CAN1>,
 626                                  <&rcan_clk>, <&can_clk>;
 627                         clock-names = "clkp1", "clkp2", "can_clk";
 628                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 629                         status = "disabled";
 630                 };
 631
 632                 vin0: video@e6ef0000 {
 633                         compatible = "renesas,vin-r8a7792",
 634                                      "renesas,rcar-gen2-vin";
 635                         reg = <0 0xe6ef0000 0 0x1000>;
 636                         interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
 637                         clocks = <&mstp8_clks R8A7792_CLK_VIN0>;
 638                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 639                         status = "disabled";
 640                 };
 641
 642                 vin1: video@e6ef1000 {
 643                         compatible = "renesas,vin-r8a7792",
 644                                      "renesas,rcar-gen2-vin";
 645                         reg = <0 0xe6ef1000 0 0x1000>;
 646                         interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
 647                         clocks = <&mstp8_clks R8A7792_CLK_VIN1>;
 648                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 649                         status = "disabled";
 650                 };
 651
 652                 vin2: video@e6ef2000 {
 653                         compatible = "renesas,vin-r8a7792",
 654                                      "renesas,rcar-gen2-vin";
 655                         reg = <0 0xe6ef2000 0 0x1000>;
 656                         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
 657                         clocks = <&mstp8_clks R8A7792_CLK_VIN2>;
 658                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 659                         status = "disabled";
 660                 };
 661
 662                 vin3: video@e6ef3000 {
 663                         compatible = "renesas,vin-r8a7792",
 664                                      "renesas,rcar-gen2-vin";
 665                         reg = <0 0xe6ef3000 0 0x1000>;
 666                         interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
 667                         clocks = <&mstp8_clks R8A7792_CLK_VIN3>;
 668                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 669                         status = "disabled";
 670                 };
 671
 672                 vin4: video@e6ef4000 {
 673                         compatible = "renesas,vin-r8a7792",
 674                                      "renesas,rcar-gen2-vin";
 675                         reg = <0 0xe6ef4000 0 0x1000>;
 676                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 677                         clocks = <&mstp8_clks R8A7792_CLK_VIN4>;
 678                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 679                         status = "disabled";
 680                 };
 681
 682                 vin5: video@e6ef5000 {
 683                         compatible = "renesas,vin-r8a7792",
 684                                      "renesas,rcar-gen2-vin";
 685                         reg = <0 0xe6ef5000 0 0x1000>;
 686                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 687                         clocks = <&mstp8_clks R8A7792_CLK_VIN5>;
 688                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 689                         status = "disabled";
 690                 };
 691
 692                 vsp1@fe928000 {
 693                         compatible = "renesas,vsp1";
 694                         reg = <0 0xfe928000 0 0x8000>;
 695                         interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
 696                         clocks = <&mstp1_clks R8A7792_CLK_VSP1_SY>;
 697                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 698                 };
 699
 700                 vsp1@fe930000 {
 701                         compatible = "renesas,vsp1";
 702                         reg = <0 0xfe930000 0 0x8000>;
 703                         interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
 704                         clocks = <&mstp1_clks R8A7792_CLK_VSP1DU0>;
 705                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 706                 };
 707
 708                 vsp1@fe938000 {
 709                         compatible = "renesas,vsp1";
 710                         reg = <0 0xfe938000 0 0x8000>;
 711                         interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
 712                         clocks = <&mstp1_clks R8A7792_CLK_VSP1DU1>;
 713                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 714                 };
 715
 716                 /* Special CPG clocks */
 717                 cpg_clocks: cpg_clocks@e6150000 {
 718                         compatible = "renesas,r8a7792-cpg-clocks",
 719                                      "renesas,rcar-gen2-cpg-clocks";
 720                         reg = <0 0xe6150000 0 0x1000>;
 721                         clocks = <&extal_clk>;
 722                         #clock-cells = <1>;
 723                         clock-output-names = "main", "pll0", "pll1", "pll3",
 724                                              "lb", "qspi", "z";
 725                         #power-domain-cells = <0>;
 726                 };
 727
 728                 /* Fixed factor clocks */
 729                 pll1_div2_clk: pll1_div2 {
 730                         compatible = "fixed-factor-clock";
 731                         clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
 732                         #clock-cells = <0>;
 733                         clock-div = <2>;
 734                         clock-mult = <1>;
 735                 };
 736                 zx_clk: zx {
 737                         compatible = "fixed-factor-clock";
 738                         clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
 739                         #clock-cells = <0>;
 740                         clock-div = <3>;
 741                         clock-mult = <1>;
 742                 };
 743                 zs_clk: zs {
 744                         compatible = "fixed-factor-clock";
 745                         clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
 746                         #clock-cells = <0>;
 747                         clock-div = <6>;
 748                         clock-mult = <1>;
 749                 };
 750                 hp_clk: hp {
 751                         compatible = "fixed-factor-clock";
 752                         clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
 753                         #clock-cells = <0>;
 754                         clock-div = <12>;
 755                         clock-mult = <1>;
 756                 };
 757                 p_clk: p {
 758                         compatible = "fixed-factor-clock";
 759                         clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
 760                         #clock-cells = <0>;
 761                         clock-div = <24>;
 762                         clock-mult = <1>;
 763                 };
 764                 cp_clk: cp {
 765                         compatible = "fixed-factor-clock";
 766                         clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
 767                         #clock-cells = <0>;
 768                         clock-div = <48>;
 769                         clock-mult = <1>;
 770                 };
 771                 m2_clk: m2 {
 772                         compatible = "fixed-factor-clock";
 773                         clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
 774                         #clock-cells = <0>;
 775                         clock-div = <8>;
 776                         clock-mult = <1>;
 777                 };
 778                 sd_clk: sd {
 779                         compatible = "fixed-factor-clock";
 780                         clocks = <&pll1_div2_clk>;
 781                         #clock-cells = <0>;
 782                         clock-div = <8>;
 783                         clock-mult = <1>;
 784                 };
 785                 rcan_clk: rcan {
 786                         compatible = "fixed-factor-clock";
 787                         clocks = <&pll1_div2_clk>;
 788                         #clock-cells = <0>;
 789                         clock-div = <49>;
 790                         clock-mult = <1>;
 791                 };
 792                 zg_clk: zg {
 793                         compatible = "fixed-factor-clock";
 794                         clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
 795                         #clock-cells = <0>;
 796                         clock-div = <5>;
 797                         clock-mult = <1>;
 798                 };
 799
 800                 /* Gate clocks */
 801                 mstp1_clks: mstp1_clks@e6150134 {
 802                         compatible = "renesas,r8a7792-mstp-clocks",
 803                                      "renesas,cpg-mstp-clocks";
 804                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
 805                         clocks = <&m2_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
 806                         #clock-cells = <1>;
 807                         clock-indices = <
 808                                 R8A7792_CLK_JPU
 809                                 R8A7792_CLK_VSP1DU1 R8A7792_CLK_VSP1DU0
 810                                 R8A7792_CLK_VSP1_SY
 811                         >;
 812                         clock-output-names = "jpu", "vsp1du1", "vsp1du0",
 813                                              "vsp1-sy";
 814                 };
 815                 mstp2_clks: mstp2_clks@e6150138 {
 816                         compatible = "renesas,r8a7792-mstp-clocks",
 817                                      "renesas,cpg-mstp-clocks";
 818                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
 819                         clocks = <&zs_clk>, <&zs_clk>;
 820                         #clock-cells = <1>;
 821                         clock-indices = <
 822                                 R8A7792_CLK_SYS_DMAC1 R8A7792_CLK_SYS_DMAC0
 823                         >;
 824                         clock-output-names = "sys-dmac1", "sys-dmac0";
 825                 };
 826                 mstp3_clks: mstp3_clks@e615013c {
 827                         compatible = "renesas,r8a7792-mstp-clocks",
 828                                      "renesas,cpg-mstp-clocks";
 829                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
 830                         clocks = <&sd_clk>;
 831                         #clock-cells = <1>;
 832                         renesas,clock-indices = <R8A7792_CLK_SDHI0>;
 833                         clock-output-names = "sdhi0";
 834                 };
 835                 mstp4_clks: mstp4_clks@e6150140 {
 836                         compatible = "renesas,r8a7792-mstp-clocks",
 837                                      "renesas,cpg-mstp-clocks";
 838                         reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
 839                         clocks = <&cp_clk>;
 840                         #clock-cells = <1>;
 841                         clock-indices = <R8A7792_CLK_IRQC>;
 842                         clock-output-names = "irqc";
 843                 };
 844                 mstp7_clks: mstp7_clks@e615014c {
 845                         compatible = "renesas,r8a7792-mstp-clocks",
 846                                      "renesas,cpg-mstp-clocks";
 847                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
 848                         clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>,
 849                                  <&p_clk>, <&p_clk>, <&zx_clk>, <&zx_clk>;
 850                         #clock-cells = <1>;
 851                         clock-indices = <
 852                                 R8A7792_CLK_HSCIF1 R8A7792_CLK_HSCIF0
 853                                 R8A7792_CLK_SCIF3 R8A7792_CLK_SCIF2
 854                                 R8A7792_CLK_SCIF1 R8A7792_CLK_SCIF0
 855                                 R8A7792_CLK_DU1 R8A7792_CLK_DU0
 856                         >;
 857                         clock-output-names = "hscif1", "hscif0", "scif3",
 858                                              "scif2", "scif1", "scif0",
 859                                              "du1", "du0";
 860                 };
 861                 mstp8_clks: mstp8_clks@e6150990 {
 862                         compatible = "renesas,r8a7792-mstp-clocks",
 863                                      "renesas,cpg-mstp-clocks";
 864                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
 865                         clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
 866                                  <&zg_clk>, <&zg_clk>, <&hp_clk>;
 867                         #clock-cells = <1>;
 868                         clock-indices = <
 869                                 R8A7792_CLK_VIN5 R8A7792_CLK_VIN4
 870                                 R8A7792_CLK_VIN3 R8A7792_CLK_VIN2
 871                                 R8A7792_CLK_VIN1 R8A7792_CLK_VIN0
 872                                 R8A7792_CLK_ETHERAVB
 873                         >;
 874                         clock-output-names = "vin5", "vin4", "vin3", "vin2",
 875                                              "vin1", "vin0", "etheravb";
 876                 };
 877                 mstp9_clks: mstp9_clks@e6150994 {
 878                         compatible = "renesas,r8a7792-mstp-clocks",
 879                                      "renesas,cpg-mstp-clocks";
 880                         reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
 881                         clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
 882                                  <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
 883                                  <&cp_clk>, <&cp_clk>, <&p_clk>, <&p_clk>,
 884                                  <&cpg_clocks R8A7792_CLK_QSPI>,
 885                                  <&cp_clk>, <&cp_clk>, <&hp_clk>, <&hp_clk>,
 886                                  <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
 887                         #clock-cells = <1>;
 888                         clock-indices = <
 889                                 R8A7792_CLK_GPIO7 R8A7792_CLK_GPIO6
 890                                 R8A7792_CLK_GPIO5 R8A7792_CLK_GPIO4
 891                                 R8A7792_CLK_GPIO3 R8A7792_CLK_GPIO2
 892                                 R8A7792_CLK_GPIO1 R8A7792_CLK_GPIO0
 893                                 R8A7792_CLK_GPIO11 R8A7792_CLK_GPIO10
 894                                 R8A7792_CLK_CAN1 R8A7792_CLK_CAN0
 895                                 R8A7792_CLK_QSPI_MOD
 896                                 R8A7792_CLK_GPIO9 R8A7792_CLK_GPIO8
 897                                 R8A7792_CLK_I2C5 R8A7792_CLK_I2C4
 898                                 R8A7792_CLK_I2C3 R8A7792_CLK_I2C2
 899                                 R8A7792_CLK_I2C1 R8A7792_CLK_I2C0
 900                         >;
 901                         clock-output-names =
 902                                 "gpio7", "gpio6", "gpio5", "gpio4",
 903                                 "gpio3", "gpio2", "gpio1", "gpio0",
 904                                 "gpio11", "gpio10", "can1", "can0",
 905                                 "qspi_mod", "gpio9", "gpio8",
 906                                 "i2c5", "i2c4", "i2c3", "i2c2",
 907                                 "i2c1", "i2c0";
 908                 };
 909         };
 910
 911         /* External root clock */
 912         extal_clk: extal {
 913                 compatible = "fixed-clock";
 914                 #clock-cells = <0>;
 915                 /* This value must be overridden by the board. */
 916                 clock-frequency = <0>;
 917         };
 918
 919         /* External SCIF clock */
 920         scif_clk: scif {
 921                 compatible = "fixed-clock";
 922                 #clock-cells = <0>;
 923                 /* This value must be overridden by the board. */
 924                 clock-frequency = <0>;
 925         };
 926
 927         /* External CAN clock */
 928         can_clk: can {
 929                 compatible = "fixed-clock";
 930                 #clock-cells = <0>;
 931                 /* This value must be overridden by the board. */
 932                 clock-frequency = <0>;
 933         };
 934 };