arch/arm/boot/dts/r8a7791.dtsi

   1 /*
   2  * Device Tree Source for the r8a7791 SoC
   3  *
   4  * Copyright (C) 2013 Renesas Electronics Corporation
   5  * Copyright (C) 2013-2014 Renesas Solutions Corp.
   6  * Copyright (C) 2014 Cogent Embedded Inc.
   7  *
   8  * This file is licensed under the terms of the GNU General Public License
   9  * version 2.  This program is licensed "as is" without any warranty of any
  10  * kind, whether express or implied.
  11  */
  12
  13 #include <dt-bindings/clock/r8a7791-clock.h>
  14 #include <dt-bindings/interrupt-controller/arm-gic.h>
  15 #include <dt-bindings/interrupt-controller/irq.h>
  16
  17 / {
  18         compatible = "renesas,r8a7791";
  19         interrupt-parent = <&gic>;
  20         #address-cells = <2>;
  21         #size-cells = <2>;
  22
  23         aliases {
  24                 i2c0 = &i2c0;
  25                 i2c1 = &i2c1;
  26                 i2c2 = &i2c2;
  27                 i2c3 = &i2c3;
  28                 i2c4 = &i2c4;
  29                 i2c5 = &i2c5;
  30                 i2c6 = &i2c6;
  31                 i2c7 = &i2c7;
  32                 i2c8 = &i2c8;
  33                 spi0 = &qspi;
  34                 spi1 = &msiof0;
  35                 spi2 = &msiof1;
  36                 spi3 = &msiof2;
  37         };
  38
  39         cpus {
  40                 #address-cells = <1>;
  41                 #size-cells = <0>;
  42
  43                 cpu0: cpu@0 {
  44                         device_type = "cpu";
  45                         compatible = "arm,cortex-a15";
  46                         reg = <0>;
  47                         clock-frequency = <1500000000>;
  48                         voltage-tolerance = <1>; /* 1% */
  49                         clocks = <&cpg_clocks R8A7791_CLK_Z>;
  50                         clock-latency = <300000>; /* 300 us */
  51
  52                         /* kHz - uV - OPPs unknown yet */
  53                         operating-points = <1500000 1000000>,
  54                                            <1312500 1000000>,
  55                                            <1125000 1000000>,
  56                                            < 937500 1000000>,
  57                                            < 750000 1000000>,
  58                                            < 375000 1000000>;
  59                 };
  60
  61                 cpu1: cpu@1 {
  62                         device_type = "cpu";
  63                         compatible = "arm,cortex-a15";
  64                         reg = <1>;
  65                         clock-frequency = <1500000000>;
  66                 };
  67         };
  68
  69         gic: interrupt-controller@f1001000 {
  70                 compatible = "arm,cortex-a15-gic";
  71                 #interrupt-cells = <3>;
  72                 #address-cells = <0>;
  73                 interrupt-controller;
  74                 reg = <0 0xf1001000 0 0x1000>,
  75                         <0 0xf1002000 0 0x1000>,
  76                         <0 0xf1004000 0 0x2000>,
  77                         <0 0xf1006000 0 0x2000>;
  78                 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  79         };
  80
  81         gpio0: gpio@e6050000 {
  82                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
  83                 reg = <0 0xe6050000 0 0x50>;
  84                 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
  85                 #gpio-cells = <2>;
  86                 gpio-controller;
  87                 gpio-ranges = <&pfc 0 0 32>;
  88                 #interrupt-cells = <2>;
  89                 interrupt-controller;
  90                 clocks = <&mstp9_clks R8A7791_CLK_GPIO0>;
  91         };
  92
  93         gpio1: gpio@e6051000 {
  94                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
  95                 reg = <0 0xe6051000 0 0x50>;
  96                 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
  97                 #gpio-cells = <2>;
  98                 gpio-controller;
  99                 gpio-ranges = <&pfc 0 32 32>;
 100                 #interrupt-cells = <2>;
 101                 interrupt-controller;
 102                 clocks = <&mstp9_clks R8A7791_CLK_GPIO1>;
 103         };
 104
 105         gpio2: gpio@e6052000 {
 106                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 107                 reg = <0 0xe6052000 0 0x50>;
 108                 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
 109                 #gpio-cells = <2>;
 110                 gpio-controller;
 111                 gpio-ranges = <&pfc 0 64 32>;
 112                 #interrupt-cells = <2>;
 113                 interrupt-controller;
 114                 clocks = <&mstp9_clks R8A7791_CLK_GPIO2>;
 115         };
 116
 117         gpio3: gpio@e6053000 {
 118                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 119                 reg = <0 0xe6053000 0 0x50>;
 120                 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
 121                 #gpio-cells = <2>;
 122                 gpio-controller;
 123                 gpio-ranges = <&pfc 0 96 32>;
 124                 #interrupt-cells = <2>;
 125                 interrupt-controller;
 126                 clocks = <&mstp9_clks R8A7791_CLK_GPIO3>;
 127         };
 128
 129         gpio4: gpio@e6054000 {
 130                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 131                 reg = <0 0xe6054000 0 0x50>;
 132                 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
 133                 #gpio-cells = <2>;
 134                 gpio-controller;
 135                 gpio-ranges = <&pfc 0 128 32>;
 136                 #interrupt-cells = <2>;
 137                 interrupt-controller;
 138                 clocks = <&mstp9_clks R8A7791_CLK_GPIO4>;
 139         };
 140
 141         gpio5: gpio@e6055000 {
 142                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 143                 reg = <0 0xe6055000 0 0x50>;
 144                 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
 145                 #gpio-cells = <2>;
 146                 gpio-controller;
 147                 gpio-ranges = <&pfc 0 160 32>;
 148                 #interrupt-cells = <2>;
 149                 interrupt-controller;
 150                 clocks = <&mstp9_clks R8A7791_CLK_GPIO5>;
 151         };
 152
 153         gpio6: gpio@e6055400 {
 154                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 155                 reg = <0 0xe6055400 0 0x50>;
 156                 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
 157                 #gpio-cells = <2>;
 158                 gpio-controller;
 159                 gpio-ranges = <&pfc 0 192 32>;
 160                 #interrupt-cells = <2>;
 161                 interrupt-controller;
 162                 clocks = <&mstp9_clks R8A7791_CLK_GPIO6>;
 163         };
 164
 165         gpio7: gpio@e6055800 {
 166                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 167                 reg = <0 0xe6055800 0 0x50>;
 168                 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
 169                 #gpio-cells = <2>;
 170                 gpio-controller;
 171                 gpio-ranges = <&pfc 0 224 26>;
 172                 #interrupt-cells = <2>;
 173                 interrupt-controller;
 174                 clocks = <&mstp9_clks R8A7791_CLK_GPIO7>;
 175         };
 176
 177         thermal@e61f0000 {
 178                 compatible = "renesas,thermal-r8a7791", "renesas,rcar-thermal";
 179                 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
 180                 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
 181                 clocks = <&mstp5_clks R8A7791_CLK_THERMAL>;
 182         };
 183
 184         timer {
 185                 compatible = "arm,armv7-timer";
 186                 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 187                              <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 188                              <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 189                              <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 190         };
 191
 192         cmt0: timer@ffca0000 {
 193                 compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
 194                 reg = <0 0xffca0000 0 0x1004>;
 195                 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
 196                              <0 143 IRQ_TYPE_LEVEL_HIGH>;
 197                 clocks = <&mstp1_clks R8A7791_CLK_CMT0>;
 198                 clock-names = "fck";
 199
 200                 renesas,channels-mask = <0x60>;
 201
 202                 status = "disabled";
 203         };
 204
 205         cmt1: timer@e6130000 {
 206                 compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
 207                 reg = <0 0xe6130000 0 0x1004>;
 208                 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
 209                              <0 121 IRQ_TYPE_LEVEL_HIGH>,
 210                              <0 122 IRQ_TYPE_LEVEL_HIGH>,
 211                              <0 123 IRQ_TYPE_LEVEL_HIGH>,
 212                              <0 124 IRQ_TYPE_LEVEL_HIGH>,
 213                              <0 125 IRQ_TYPE_LEVEL_HIGH>,
 214                              <0 126 IRQ_TYPE_LEVEL_HIGH>,
 215                              <0 127 IRQ_TYPE_LEVEL_HIGH>;
 216                 clocks = <&mstp3_clks R8A7791_CLK_CMT1>;
 217                 clock-names = "fck";
 218
 219                 renesas,channels-mask = <0xff>;
 220
 221                 status = "disabled";
 222         };
 223
 224         irqc0: interrupt-controller@e61c0000 {
 225                 compatible = "renesas,irqc-r8a7791", "renesas,irqc";
 226                 #interrupt-cells = <2>;
 227                 interrupt-controller;
 228                 reg = <0 0xe61c0000 0 0x200>;
 229                 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
 230                              <0 1 IRQ_TYPE_LEVEL_HIGH>,
 231                              <0 2 IRQ_TYPE_LEVEL_HIGH>,
 232                              <0 3 IRQ_TYPE_LEVEL_HIGH>,
 233                              <0 12 IRQ_TYPE_LEVEL_HIGH>,
 234                              <0 13 IRQ_TYPE_LEVEL_HIGH>,
 235                              <0 14 IRQ_TYPE_LEVEL_HIGH>,
 236                              <0 15 IRQ_TYPE_LEVEL_HIGH>,
 237                              <0 16 IRQ_TYPE_LEVEL_HIGH>,
 238                              <0 17 IRQ_TYPE_LEVEL_HIGH>;
 239         };
 240
 241         /* The memory map in the User's Manual maps the cores to bus numbers */
 242         i2c0: i2c@e6508000 {
 243                 #address-cells = <1>;
 244                 #size-cells = <0>;
 245                 compatible = "renesas,i2c-r8a7791";
 246                 reg = <0 0xe6508000 0 0x40>;
 247                 interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
 248                 clocks = <&mstp9_clks R8A7791_CLK_I2C0>;
 249                 status = "disabled";
 250         };
 251
 252         i2c1: i2c@e6518000 {
 253                 #address-cells = <1>;
 254                 #size-cells = <0>;
 255                 compatible = "renesas,i2c-r8a7791";
 256                 reg = <0 0xe6518000 0 0x40>;
 257                 interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
 258                 clocks = <&mstp9_clks R8A7791_CLK_I2C1>;
 259                 status = "disabled";
 260         };
 261
 262         i2c2: i2c@e6530000 {
 263                 #address-cells = <1>;
 264                 #size-cells = <0>;
 265                 compatible = "renesas,i2c-r8a7791";
 266                 reg = <0 0xe6530000 0 0x40>;
 267                 interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
 268                 clocks = <&mstp9_clks R8A7791_CLK_I2C2>;
 269                 status = "disabled";
 270         };
 271
 272         i2c3: i2c@e6540000 {
 273                 #address-cells = <1>;
 274                 #size-cells = <0>;
 275                 compatible = "renesas,i2c-r8a7791";
 276                 reg = <0 0xe6540000 0 0x40>;
 277                 interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
 278                 clocks = <&mstp9_clks R8A7791_CLK_I2C3>;
 279                 status = "disabled";
 280         };
 281
 282         i2c4: i2c@e6520000 {
 283                 #address-cells = <1>;
 284                 #size-cells = <0>;
 285                 compatible = "renesas,i2c-r8a7791";
 286                 reg = <0 0xe6520000 0 0x40>;
 287                 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
 288                 clocks = <&mstp9_clks R8A7791_CLK_I2C4>;
 289                 status = "disabled";
 290         };
 291
 292         i2c5: i2c@e6528000 {
 293                 /* doesn't need pinmux */
 294                 #address-cells = <1>;
 295                 #size-cells = <0>;
 296                 compatible = "renesas,i2c-r8a7791";
 297                 reg = <0 0xe6528000 0 0x40>;
 298                 interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
 299                 clocks = <&mstp9_clks R8A7791_CLK_I2C5>;
 300                 status = "disabled";
 301         };
 302
 303         i2c6: i2c@e60b0000 {
 304                 /* doesn't need pinmux */
 305                 #address-cells = <1>;
 306                 #size-cells = <0>;
 307                 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
 308                 reg = <0 0xe60b0000 0 0x425>;
 309                 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
 310                 clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>;
 311                 status = "disabled";
 312         };
 313
 314         i2c7: i2c@e6500000 {
 315                 #address-cells = <1>;
 316                 #size-cells = <0>;
 317                 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
 318                 reg = <0 0xe6500000 0 0x425>;
 319                 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
 320                 clocks = <&mstp3_clks R8A7791_CLK_IIC0>;
 321                 status = "disabled";
 322         };
 323
 324         i2c8: i2c@e6510000 {
 325                 #address-cells = <1>;
 326                 #size-cells = <0>;
 327                 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
 328                 reg = <0 0xe6510000 0 0x425>;
 329                 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
 330                 clocks = <&mstp3_clks R8A7791_CLK_IIC1>;
 331                 status = "disabled";
 332         };
 333
 334         pfc: pfc@e6060000 {
 335                 compatible = "renesas,pfc-r8a7791";
 336                 reg = <0 0xe6060000 0 0x250>;
 337                 #gpio-range-cells = <3>;
 338         };
 339
 340         sdhi0: sd@ee100000 {
 341                 compatible = "renesas,sdhi-r8a7791";
 342                 reg = <0 0xee100000 0 0x200>;
 343                 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
 344                 clocks = <&mstp3_clks R8A7791_CLK_SDHI0>;
 345                 status = "disabled";
 346         };
 347
 348         sdhi1: sd@ee140000 {
 349                 compatible = "renesas,sdhi-r8a7791";
 350                 reg = <0 0xee140000 0 0x100>;
 351                 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
 352                 clocks = <&mstp3_clks R8A7791_CLK_SDHI1>;
 353                 status = "disabled";
 354         };
 355
 356         sdhi2: sd@ee160000 {
 357                 compatible = "renesas,sdhi-r8a7791";
 358                 reg = <0 0xee160000 0 0x100>;
 359                 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
 360                 clocks = <&mstp3_clks R8A7791_CLK_SDHI2>;
 361                 status = "disabled";
 362         };
 363
 364         scifa0: serial@e6c40000 {
 365                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 366                 reg = <0 0xe6c40000 0 64>;
 367                 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
 368                 clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>;
 369                 clock-names = "sci_ick";
 370                 status = "disabled";
 371         };
 372
 373         scifa1: serial@e6c50000 {
 374                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 375                 reg = <0 0xe6c50000 0 64>;
 376                 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
 377                 clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>;
 378                 clock-names = "sci_ick";
 379                 status = "disabled";
 380         };
 381
 382         scifa2: serial@e6c60000 {
 383                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 384                 reg = <0 0xe6c60000 0 64>;
 385                 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
 386                 clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>;
 387                 clock-names = "sci_ick";
 388                 status = "disabled";
 389         };
 390
 391         scifa3: serial@e6c70000 {
 392                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 393                 reg = <0 0xe6c70000 0 64>;
 394                 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
 395                 clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>;
 396                 clock-names = "sci_ick";
 397                 status = "disabled";
 398         };
 399
 400         scifa4: serial@e6c78000 {
 401                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 402                 reg = <0 0xe6c78000 0 64>;
 403                 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
 404                 clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>;
 405                 clock-names = "sci_ick";
 406                 status = "disabled";
 407         };
 408
 409         scifa5: serial@e6c80000 {
 410                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 411                 reg = <0 0xe6c80000 0 64>;
 412                 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 413                 clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>;
 414                 clock-names = "sci_ick";
 415                 status = "disabled";
 416         };
 417
 418         scifb0: serial@e6c20000 {
 419                 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
 420                 reg = <0 0xe6c20000 0 64>;
 421                 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
 422                 clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>;
 423                 clock-names = "sci_ick";
 424                 status = "disabled";
 425         };
 426
 427         scifb1: serial@e6c30000 {
 428                 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
 429                 reg = <0 0xe6c30000 0 64>;
 430                 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
 431                 clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>;
 432                 clock-names = "sci_ick";
 433                 status = "disabled";
 434         };
 435
 436         scifb2: serial@e6ce0000 {
 437                 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
 438                 reg = <0 0xe6ce0000 0 64>;
 439                 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
 440                 clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>;
 441                 clock-names = "sci_ick";
 442                 status = "disabled";
 443         };
 444
 445         scif0: serial@e6e60000 {
 446                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 447                 reg = <0 0xe6e60000 0 64>;
 448                 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
 449                 clocks = <&mstp7_clks R8A7791_CLK_SCIF0>;
 450                 clock-names = "sci_ick";
 451                 status = "disabled";
 452         };
 453
 454         scif1: serial@e6e68000 {
 455                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 456                 reg = <0 0xe6e68000 0 64>;
 457                 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
 458                 clocks = <&mstp7_clks R8A7791_CLK_SCIF1>;
 459                 clock-names = "sci_ick";
 460                 status = "disabled";
 461         };
 462
 463         scif2: serial@e6e58000 {
 464                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 465                 reg = <0 0xe6e58000 0 64>;
 466                 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 467                 clocks = <&mstp7_clks R8A7791_CLK_SCIF2>;
 468                 clock-names = "sci_ick";
 469                 status = "disabled";
 470         };
 471
 472         scif3: serial@e6ea8000 {
 473                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 474                 reg = <0 0xe6ea8000 0 64>;
 475                 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 476                 clocks = <&mstp7_clks R8A7791_CLK_SCIF3>;
 477                 clock-names = "sci_ick";
 478                 status = "disabled";
 479         };
 480
 481         scif4: serial@e6ee0000 {
 482                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 483                 reg = <0 0xe6ee0000 0 64>;
 484                 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
 485                 clocks = <&mstp7_clks R8A7791_CLK_SCIF4>;
 486                 clock-names = "sci_ick";
 487                 status = "disabled";
 488         };
 489
 490         scif5: serial@e6ee8000 {
 491                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 492                 reg = <0 0xe6ee8000 0 64>;
 493                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 494                 clocks = <&mstp7_clks R8A7791_CLK_SCIF5>;
 495                 clock-names = "sci_ick";
 496                 status = "disabled";
 497         };
 498
 499         hscif0: serial@e62c0000 {
 500                 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
 501                 reg = <0 0xe62c0000 0 96>;
 502                 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
 503                 clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>;
 504                 clock-names = "sci_ick";
 505                 status = "disabled";
 506         };
 507
 508         hscif1: serial@e62c8000 {
 509                 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
 510                 reg = <0 0xe62c8000 0 96>;
 511                 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
 512                 clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>;
 513                 clock-names = "sci_ick";
 514                 status = "disabled";
 515         };
 516
 517         hscif2: serial@e62d0000 {
 518                 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
 519                 reg = <0 0xe62d0000 0 96>;
 520                 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
 521                 clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>;
 522                 clock-names = "sci_ick";
 523                 status = "disabled";
 524         };
 525
 526         ether: ethernet@ee700000 {
 527                 compatible = "renesas,ether-r8a7791";
 528                 reg = <0 0xee700000 0 0x400>;
 529                 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
 530                 clocks = <&mstp8_clks R8A7791_CLK_ETHER>;
 531                 phy-mode = "rmii";
 532                 #address-cells = <1>;
 533                 #size-cells = <0>;
 534                 status = "disabled";
 535         };
 536
 537         sata0: sata@ee300000 {
 538                 compatible = "renesas,sata-r8a7791";
 539                 reg = <0 0xee300000 0 0x2000>;
 540                 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
 541                 clocks = <&mstp8_clks R8A7791_CLK_SATA0>;
 542                 status = "disabled";
 543         };
 544
 545         sata1: sata@ee500000 {
 546                 compatible = "renesas,sata-r8a7791";
 547                 reg = <0 0xee500000 0 0x2000>;
 548                 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
 549                 clocks = <&mstp8_clks R8A7791_CLK_SATA1>;
 550                 status = "disabled";
 551         };
 552
 553         clocks {
 554                 #address-cells = <2>;
 555                 #size-cells = <2>;
 556                 ranges;
 557
 558                 /* External root clock */
 559                 extal_clk: extal_clk {
 560                         compatible = "fixed-clock";
 561                         #clock-cells = <0>;
 562                         /* This value must be overriden by the board. */
 563                         clock-frequency = <0>;
 564                         clock-output-names = "extal";
 565                 };
 566
 567                 /*
 568                  * The external audio clocks are configured as 0 Hz fixed frequency clocks by
 569                  * default. Boards that provide audio clocks should override them.
 570                  */
 571                 audio_clk_a: audio_clk_a {
 572                         compatible = "fixed-clock";
 573                         #clock-cells = <0>;
 574                         clock-frequency = <0>;
 575                         clock-output-names = "audio_clk_a";
 576                 };
 577                 audio_clk_b: audio_clk_b {
 578                         compatible = "fixed-clock";
 579                         #clock-cells = <0>;
 580                         clock-frequency = <0>;
 581                         clock-output-names = "audio_clk_b";
 582                 };
 583                 audio_clk_c: audio_clk_c {
 584                         compatible = "fixed-clock";
 585                         #clock-cells = <0>;
 586                         clock-frequency = <0>;
 587                         clock-output-names = "audio_clk_c";
 588                 };
 589
 590                 /* External PCIe clock - can be overridden by the board */
 591                 pcie_bus_clk: pcie_bus_clk {
 592                         compatible = "fixed-clock";
 593                         #clock-cells = <0>;
 594                         clock-frequency = <100000000>;
 595                         clock-output-names = "pcie_bus";
 596                         status = "disabled";
 597                 };
 598
 599                 /* Special CPG clocks */
 600                 cpg_clocks: cpg_clocks@e6150000 {
 601                         compatible = "renesas,r8a7791-cpg-clocks",
 602                                      "renesas,rcar-gen2-cpg-clocks";
 603                         reg = <0 0xe6150000 0 0x1000>;
 604                         clocks = <&extal_clk>;
 605                         #clock-cells = <1>;
 606                         clock-output-names = "main", "pll0", "pll1", "pll3",
 607                                              "lb", "qspi", "sdh", "sd0", "z";
 608                 };
 609
 610                 /* Variable factor clocks */
 611                 sd1_clk: sd2_clk@e6150078 {
 612                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 613                         reg = <0 0xe6150078 0 4>;
 614                         clocks = <&pll1_div2_clk>;
 615                         #clock-cells = <0>;
 616                         clock-output-names = "sd1";
 617                 };
 618                 sd2_clk: sd3_clk@e615026c {
 619                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 620                         reg = <0 0xe615026c 0 4>;
 621                         clocks = <&pll1_div2_clk>;
 622                         #clock-cells = <0>;
 623                         clock-output-names = "sd2";
 624                 };
 625                 mmc0_clk: mmc0_clk@e6150240 {
 626                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 627                         reg = <0 0xe6150240 0 4>;
 628                         clocks = <&pll1_div2_clk>;
 629                         #clock-cells = <0>;
 630                         clock-output-names = "mmc0";
 631                 };
 632                 ssp_clk: ssp_clk@e6150248 {
 633                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 634                         reg = <0 0xe6150248 0 4>;
 635                         clocks = <&pll1_div2_clk>;
 636                         #clock-cells = <0>;
 637                         clock-output-names = "ssp";
 638                 };
 639                 ssprs_clk: ssprs_clk@e615024c {
 640                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 641                         reg = <0 0xe615024c 0 4>;
 642                         clocks = <&pll1_div2_clk>;
 643                         #clock-cells = <0>;
 644                         clock-output-names = "ssprs";
 645                 };
 646
 647                 /* Fixed factor clocks */
 648                 pll1_div2_clk: pll1_div2_clk {
 649                         compatible = "fixed-factor-clock";
 650                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 651                         #clock-cells = <0>;
 652                         clock-div = <2>;
 653                         clock-mult = <1>;
 654                         clock-output-names = "pll1_div2";
 655                 };
 656                 zg_clk: zg_clk {
 657                         compatible = "fixed-factor-clock";
 658                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 659                         #clock-cells = <0>;
 660                         clock-div = <3>;
 661                         clock-mult = <1>;
 662                         clock-output-names = "zg";
 663                 };
 664                 zx_clk: zx_clk {
 665                         compatible = "fixed-factor-clock";
 666                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 667                         #clock-cells = <0>;
 668                         clock-div = <3>;
 669                         clock-mult = <1>;
 670                         clock-output-names = "zx";
 671                 };
 672                 zs_clk: zs_clk {
 673                         compatible = "fixed-factor-clock";
 674                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 675                         #clock-cells = <0>;
 676                         clock-div = <6>;
 677                         clock-mult = <1>;
 678                         clock-output-names = "zs";
 679                 };
 680                 hp_clk: hp_clk {
 681                         compatible = "fixed-factor-clock";
 682                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 683                         #clock-cells = <0>;
 684                         clock-div = <12>;
 685                         clock-mult = <1>;
 686                         clock-output-names = "hp";
 687                 };
 688                 i_clk: i_clk {
 689                         compatible = "fixed-factor-clock";
 690                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 691                         #clock-cells = <0>;
 692                         clock-div = <2>;
 693                         clock-mult = <1>;
 694                         clock-output-names = "i";
 695                 };
 696                 b_clk: b_clk {
 697                         compatible = "fixed-factor-clock";
 698                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 699                         #clock-cells = <0>;
 700                         clock-div = <12>;
 701                         clock-mult = <1>;
 702                         clock-output-names = "b";
 703                 };
 704                 p_clk: p_clk {
 705                         compatible = "fixed-factor-clock";
 706                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 707                         #clock-cells = <0>;
 708                         clock-div = <24>;
 709                         clock-mult = <1>;
 710                         clock-output-names = "p";
 711                 };
 712                 cl_clk: cl_clk {
 713                         compatible = "fixed-factor-clock";
 714                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 715                         #clock-cells = <0>;
 716                         clock-div = <48>;
 717                         clock-mult = <1>;
 718                         clock-output-names = "cl";
 719                 };
 720                 m2_clk: m2_clk {
 721                         compatible = "fixed-factor-clock";
 722                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 723                         #clock-cells = <0>;
 724                         clock-div = <8>;
 725                         clock-mult = <1>;
 726                         clock-output-names = "m2";
 727                 };
 728                 imp_clk: imp_clk {
 729                         compatible = "fixed-factor-clock";
 730                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 731                         #clock-cells = <0>;
 732                         clock-div = <4>;
 733                         clock-mult = <1>;
 734                         clock-output-names = "imp";
 735                 };
 736                 rclk_clk: rclk_clk {
 737                         compatible = "fixed-factor-clock";
 738                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 739                         #clock-cells = <0>;
 740                         clock-div = <(48 * 1024)>;
 741                         clock-mult = <1>;
 742                         clock-output-names = "rclk";
 743                 };
 744                 oscclk_clk: oscclk_clk {
 745                         compatible = "fixed-factor-clock";
 746                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 747                         #clock-cells = <0>;
 748                         clock-div = <(12 * 1024)>;
 749                         clock-mult = <1>;
 750                         clock-output-names = "oscclk";
 751                 };
 752                 zb3_clk: zb3_clk {
 753                         compatible = "fixed-factor-clock";
 754                         clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
 755                         #clock-cells = <0>;
 756                         clock-div = <4>;
 757                         clock-mult = <1>;
 758                         clock-output-names = "zb3";
 759                 };
 760                 zb3d2_clk: zb3d2_clk {
 761                         compatible = "fixed-factor-clock";
 762                         clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
 763                         #clock-cells = <0>;
 764                         clock-div = <8>;
 765                         clock-mult = <1>;
 766                         clock-output-names = "zb3d2";
 767                 };
 768                 ddr_clk: ddr_clk {
 769                         compatible = "fixed-factor-clock";
 770                         clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
 771                         #clock-cells = <0>;
 772                         clock-div = <8>;
 773                         clock-mult = <1>;
 774                         clock-output-names = "ddr";
 775                 };
 776                 mp_clk: mp_clk {
 777                         compatible = "fixed-factor-clock";
 778                         clocks = <&pll1_div2_clk>;
 779                         #clock-cells = <0>;
 780                         clock-div = <15>;
 781                         clock-mult = <1>;
 782                         clock-output-names = "mp";
 783                 };
 784                 cp_clk: cp_clk {
 785                         compatible = "fixed-factor-clock";
 786                         clocks = <&extal_clk>;
 787                         #clock-cells = <0>;
 788                         clock-div = <2>;
 789                         clock-mult = <1>;
 790                         clock-output-names = "cp";
 791                 };
 792
 793                 /* Gate clocks */
 794                 mstp0_clks: mstp0_clks@e6150130 {
 795                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 796                         reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
 797                         clocks = <&mp_clk>;
 798                         #clock-cells = <1>;
 799                         renesas,clock-indices = <R8A7791_CLK_MSIOF0>;
 800                         clock-output-names = "msiof0";
 801                 };
 802                 mstp1_clks: mstp1_clks@e6150134 {
 803                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 804                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
 805                         clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
 806                                  <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
 807                         #clock-cells = <1>;
 808                         renesas,clock-indices = <
 809                                 R8A7791_CLK_TMU1 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2
 810                                 R8A7791_CLK_CMT0 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1
 811                                 R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_S
 812                         >;
 813                         clock-output-names =
 814                                 "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
 815                                 "vsp1-du0", "vsp1-sy";
 816                 };
 817                 mstp2_clks: mstp2_clks@e6150138 {
 818                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 819                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
 820                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
 821                                  <&mp_clk>, <&mp_clk>, <&mp_clk>,
 822                                  <&zs_clk>, <&zs_clk>;
 823                         #clock-cells = <1>;
 824                         renesas,clock-indices = <
 825                                 R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0
 826                                 R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1
 827                                 R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2
 828                                 R8A7791_CLK_SYS_DMAC1 R8A7791_CLK_SYS_DMAC0
 829                         >;
 830                         clock-output-names =
 831                                 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
 832                                 "scifb1", "msiof1", "scifb2",
 833                                 "sys-dmac1", "sys-dmac0";
 834                 };
 835                 mstp3_clks: mstp3_clks@e615013c {
 836                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 837                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
 838                         clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7791_CLK_SD0>,
 839                                  <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>;
 840                         #clock-cells = <1>;
 841                         renesas,clock-indices = <
 842                                 R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0
 843                                 R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1
 844                                 R8A7791_CLK_SSUSB R8A7791_CLK_CMT1
 845                         >;
 846                         clock-output-names =
 847                                 "tpu0", "sdhi2", "sdhi1", "sdhi0",
 848                                 "mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1";
 849                 };
 850                 mstp5_clks: mstp5_clks@e6150144 {
 851                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 852                         reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
 853                         clocks = <&extal_clk>, <&p_clk>;
 854                         #clock-cells = <1>;
 855                         renesas,clock-indices = <R8A7791_CLK_THERMAL R8A7791_CLK_PWM>;
 856                         clock-output-names = "thermal", "pwm";
 857                 };
 858                 mstp7_clks: mstp7_clks@e615014c {
 859                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 860                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
 861                         clocks = <&mp_clk>,  <&mp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
 862                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
 863                                  <&zx_clk>, <&zx_clk>, <&zx_clk>;
 864                         #clock-cells = <1>;
 865                         renesas,clock-indices = <
 866                                 R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5
 867                                 R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0
 868                                 R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1
 869                                 R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0
 870                                 R8A7791_CLK_LVDS0
 871                         >;
 872                         clock-output-names =
 873                                 "ehci", "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0",
 874                                 "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0";
 875                 };
 876                 mstp8_clks: mstp8_clks@e6150990 {
 877                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 878                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
 879                         clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>, <&zs_clk>,
 880                                  <&zs_clk>;
 881                         #clock-cells = <1>;
 882                         renesas,clock-indices = <
 883                                 R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0
 884                                 R8A7791_CLK_ETHER R8A7791_CLK_SATA1 R8A7791_CLK_SATA0
 885                         >;
 886                         clock-output-names =
 887                                 "vin2", "vin1", "vin0", "ether", "sata1", "sata0";
 888                 };
 889                 mstp9_clks: mstp9_clks@e6150994 {
 890                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 891                         reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
 892                         clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
 893                                  <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
 894                                  <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&hp_clk>,
 895                                  <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
 896                                  <&hp_clk>, <&hp_clk>;
 897                         #clock-cells = <1>;
 898                         renesas,clock-indices = <
 899                                 R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4
 900                                 R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0
 901                                 R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5
 902                                 R8A7791_CLK_IICDVFS R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2
 903                                 R8A7791_CLK_I2C1 R8A7791_CLK_I2C0
 904                         >;
 905                         clock-output-names =
 906                                 "gpio7", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
 907                                 "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2",
 908                                 "i2c1", "i2c0";
 909                 };
 910                 mstp10_clks: mstp10_clks@e6150998 {
 911                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 912                         reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
 913                         clocks = <&p_clk>,
 914                                 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
 915                                 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
 916                                 <&p_clk>,
 917                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
 918                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
 919                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
 920                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
 921                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
 922                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>;
 923
 924                         #clock-cells = <1>;
 925                         clock-indices = <
 926                                 R8A7791_CLK_SSI_ALL
 927                                 R8A7791_CLK_SSI9 R8A7791_CLK_SSI8 R8A7791_CLK_SSI7 R8A7791_CLK_SSI6 R8A7791_CLK_SSI5
 928                                 R8A7791_CLK_SSI4 R8A7791_CLK_SSI3 R8A7791_CLK_SSI2 R8A7791_CLK_SSI1 R8A7791_CLK_SSI0
 929                                 R8A7791_CLK_SCU_ALL
 930                                 R8A7791_CLK_SCU_DVC1 R8A7791_CLK_SCU_DVC0
 931                                 R8A7791_CLK_SCU_SRC9 R8A7791_CLK_SCU_SRC8 R8A7791_CLK_SCU_SRC7 R8A7791_CLK_SCU_SRC6 R8A7791_CLK_SCU_SRC5
 932                                 R8A7791_CLK_SCU_SRC4 R8A7791_CLK_SCU_SRC3 R8A7791_CLK_SCU_SRC2 R8A7791_CLK_SCU_SRC1 R8A7791_CLK_SCU_SRC0
 933                         >;
 934                         clock-output-names =
 935                                 "ssi-all",
 936                                 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
 937                                 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
 938                                 "scu-all",
 939                                 "scu-dvc1", "scu-dvc0",
 940                                 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
 941                                 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
 942                 };
 943                 mstp11_clks: mstp11_clks@e615099c {
 944                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 945                         reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
 946                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
 947                         #clock-cells = <1>;
 948                         renesas,clock-indices = <
 949                                 R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5
 950                         >;
 951                         clock-output-names = "scifa3", "scifa4", "scifa5";
 952                 };
 953         };
 954
 955         qspi: spi@e6b10000 {
 956                 compatible = "renesas,qspi-r8a7791", "renesas,qspi";
 957                 reg = <0 0xe6b10000 0 0x2c>;
 958                 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
 959                 clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>;
 960                 num-cs = <1>;
 961                 #address-cells = <1>;
 962                 #size-cells = <0>;
 963                 status = "disabled";
 964         };
 965
 966         msiof0: spi@e6e20000 {
 967                 compatible = "renesas,msiof-r8a7791";
 968                 reg = <0 0xe6e20000 0 0x0064>;
 969                 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
 970                 clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
 971                 #address-cells = <1>;
 972                 #size-cells = <0>;
 973                 status = "disabled";
 974         };
 975
 976         msiof1: spi@e6e10000 {
 977                 compatible = "renesas,msiof-r8a7791";
 978                 reg = <0 0xe6e10000 0 0x0064>;
 979                 interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
 980                 clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>;
 981                 #address-cells = <1>;
 982                 #size-cells = <0>;
 983                 status = "disabled";
 984         };
 985
 986         msiof2: spi@e6e00000 {
 987                 compatible = "renesas,msiof-r8a7791";
 988                 reg = <0 0xe6e00000 0 0x0064>;
 989                 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
 990                 clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>;
 991                 #address-cells = <1>;
 992                 #size-cells = <0>;
 993                 status = "disabled";
 994         };
 995
 996         pci0: pci@ee090000 {
 997                 compatible = "renesas,pci-r8a7791";
 998                 device_type = "pci";
 999                 clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
1000                 reg = <0 0xee090000 0 0xc00>,
1001                       <0 0xee080000 0 0x1100>;
1002                 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1003                 status = "disabled";
1004
1005                 bus-range = <0 0>;
1006                 #address-cells = <3>;
1007                 #size-cells = <2>;
1008                 #interrupt-cells = <1>;
1009                 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
1010                 interrupt-map-mask = <0xff00 0 0 0x7>;
1011                 interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1012                                  0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1013                                  0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
1014         };
1015
1016         pci1: pci@ee0d0000 {
1017                 compatible = "renesas,pci-r8a7791";
1018                 device_type = "pci";
1019                 clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
1020                 reg = <0 0xee0d0000 0 0xc00>,
1021                       <0 0xee0c0000 0 0x1100>;
1022                 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
1023                 status = "disabled";
1024
1025                 bus-range = <1 1>;
1026                 #address-cells = <3>;
1027                 #size-cells = <2>;
1028                 #interrupt-cells = <1>;
1029                 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
1030                 interrupt-map-mask = <0xff00 0 0 0x7>;
1031                 interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1032                                  0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1033                                  0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
1034         };
1035
1036         pciec: pcie@fe000000 {
1037                 compatible = "renesas,pcie-r8a7791";
1038                 reg = <0 0xfe000000 0 0x80000>;
1039                 #address-cells = <3>;
1040                 #size-cells = <2>;
1041                 bus-range = <0x00 0xff>;
1042                 device_type = "pci";
1043                 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1044                           0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1045                           0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1046                           0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1047                 /* Map all possible DDR as inbound ranges */
1048                 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
1049                               0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
1050                 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>,
1051                              <0 117 IRQ_TYPE_LEVEL_HIGH>,
1052                              <0 118 IRQ_TYPE_LEVEL_HIGH>;
1053                 #interrupt-cells = <1>;
1054                 interrupt-map-mask = <0 0 0 0>;
1055                 interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>;
1056                 clocks = <&mstp3_clks R8A7791_CLK_PCIEC>, <&pcie_bus_clk>;
1057                 clock-names = "pcie", "pcie_bus";
1058                 status = "disabled";
1059         };
1060
1061         rcar_sound: rcar_sound@0xec500000 {
1062                 #sound-dai-cells = <1>;
1063                 compatible =  "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2", "renesas,rcar_sound";
1064                 interrupt-parent = <&gic>;
1065                 reg =   <0 0xec500000 0 0x1000>, /* SCU */
1066                         <0 0xec5a0000 0 0x100>,  /* ADG */
1067                         <0 0xec540000 0 0x1000>, /* SSIU */
1068                         <0 0xec541000 0 0x1280>; /* SSI */
1069                 clocks = <&mstp10_clks R8A7791_CLK_SSI_ALL>,
1070                         <&mstp10_clks R8A7791_CLK_SSI9>, <&mstp10_clks R8A7791_CLK_SSI8>,
1071                         <&mstp10_clks R8A7791_CLK_SSI7>, <&mstp10_clks R8A7791_CLK_SSI6>,
1072                         <&mstp10_clks R8A7791_CLK_SSI5>, <&mstp10_clks R8A7791_CLK_SSI4>,
1073                         <&mstp10_clks R8A7791_CLK_SSI3>, <&mstp10_clks R8A7791_CLK_SSI2>,
1074                         <&mstp10_clks R8A7791_CLK_SSI1>, <&mstp10_clks R8A7791_CLK_SSI0>,
1075                         <&mstp10_clks R8A7791_CLK_SCU_SRC9>, <&mstp10_clks R8A7791_CLK_SCU_SRC8>,
1076                         <&mstp10_clks R8A7791_CLK_SCU_SRC7>, <&mstp10_clks R8A7791_CLK_SCU_SRC6>,
1077                         <&mstp10_clks R8A7791_CLK_SCU_SRC5>, <&mstp10_clks R8A7791_CLK_SCU_SRC4>,
1078                         <&mstp10_clks R8A7791_CLK_SCU_SRC3>, <&mstp10_clks R8A7791_CLK_SCU_SRC2>,
1079                         <&mstp10_clks R8A7791_CLK_SCU_SRC1>, <&mstp10_clks R8A7791_CLK_SCU_SRC0>,
1080                         <&mstp10_clks R8A7791_CLK_SCU_DVC0>, <&mstp10_clks R8A7791_CLK_SCU_DVC1>,
1081                         <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1082                 clock-names = "ssi-all",
1083                                 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1084                                 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1085                                 "src.9", "src.8", "src.7", "src.6", "src.5",
1086                                 "src.4", "src.3", "src.2", "src.1", "src.0",
1087                                 "dvc.0", "dvc.1",
1088                                 "clk_a", "clk_b", "clk_c", "clk_i";
1089
1090                 status = "disabled";
1091
1092                 rcar_sound,dvc {
1093                         dvc0: dvc@0 { };
1094                         dvc1: dvc@1 { };
1095                 };
1096
1097                 rcar_sound,src {
1098                         src0: src@0 { };
1099                         src1: src@1 { };
1100                         src2: src@2 { };
1101                         src3: src@3 { };
1102                         src4: src@4 { };
1103                         src5: src@5 { };
1104                         src6: src@6 { };
1105                         src7: src@7 { };
1106                         src8: src@8 { };
1107                         src9: src@9 { };
1108                 };
1109
1110                 rcar_sound,ssi {
1111                         ssi0: ssi@0 { interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; };
1112                         ssi1: ssi@1 { interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; };
1113                         ssi2: ssi@2 { interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; };
1114                         ssi3: ssi@3 { interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; };
1115                         ssi4: ssi@4 { interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; };
1116                         ssi5: ssi@5 { interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; };
1117                         ssi6: ssi@6 { interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; };
1118                         ssi7: ssi@7 { interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; };
1119                         ssi8: ssi@8 { interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; };
1120                         ssi9: ssi@9 { interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; };
1121                 };
1122         };
1123 };