arch/arm/boot/dts/r8a7790.dtsi

   1 /*
   2  * Device Tree Source for the r8a7790 SoC
   3  *
   4  * Copyright (C) 2013-2014 Renesas Solutions Corp.
   5  * Copyright (C) 2014 Cogent Embedded Inc.
   6  *
   7  * This file is licensed under the terms of the GNU General Public License
   8  * version 2.  This program is licensed "as is" without any warranty of any
   9  * kind, whether express or implied.
  10  */
  11
  12 #include <dt-bindings/clock/r8a7790-clock.h>
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15
  16 / {
  17         compatible = "renesas,r8a7790";
  18         interrupt-parent = <&gic>;
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         aliases {
  23                 i2c0 = &i2c0;
  24                 i2c1 = &i2c1;
  25                 i2c2 = &i2c2;
  26                 i2c3 = &i2c3;
  27                 i2c4 = &iic0;
  28                 i2c5 = &iic1;
  29                 i2c6 = &iic2;
  30                 i2c7 = &iic3;
  31                 spi0 = &qspi;
  32                 spi1 = &msiof0;
  33                 spi2 = &msiof1;
  34                 spi3 = &msiof2;
  35                 spi4 = &msiof3;
  36                 vin0 = &vin0;
  37                 vin1 = &vin1;
  38                 vin2 = &vin2;
  39                 vin3 = &vin3;
  40         };
  41
  42         cpus {
  43                 #address-cells = <1>;
  44                 #size-cells = <0>;
  45
  46                 cpu0: cpu@0 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a15";
  49                         reg = <0>;
  50                         clock-frequency = <1300000000>;
  51                         voltage-tolerance = <1>; /* 1% */
  52                         clocks = <&cpg_clocks R8A7790_CLK_Z>;
  53                         clock-latency = <300000>; /* 300 us */
  54
  55                         /* kHz - uV - OPPs unknown yet */
  56                         operating-points = <1400000 1000000>,
  57                                            <1225000 1000000>,
  58                                            <1050000 1000000>,
  59                                            < 875000 1000000>,
  60                                            < 700000 1000000>,
  61                                            < 350000 1000000>;
  62                 };
  63
  64                 cpu1: cpu@1 {
  65                         device_type = "cpu";
  66                         compatible = "arm,cortex-a15";
  67                         reg = <1>;
  68                         clock-frequency = <1300000000>;
  69                 };
  70
  71                 cpu2: cpu@2 {
  72                         device_type = "cpu";
  73                         compatible = "arm,cortex-a15";
  74                         reg = <2>;
  75                         clock-frequency = <1300000000>;
  76                 };
  77
  78                 cpu3: cpu@3 {
  79                         device_type = "cpu";
  80                         compatible = "arm,cortex-a15";
  81                         reg = <3>;
  82                         clock-frequency = <1300000000>;
  83                 };
  84
  85                 cpu4: cpu@4 {
  86                         device_type = "cpu";
  87                         compatible = "arm,cortex-a7";
  88                         reg = <0x100>;
  89                         clock-frequency = <780000000>;
  90                 };
  91
  92                 cpu5: cpu@5 {
  93                         device_type = "cpu";
  94                         compatible = "arm,cortex-a7";
  95                         reg = <0x101>;
  96                         clock-frequency = <780000000>;
  97                 };
  98
  99                 cpu6: cpu@6 {
 100                         device_type = "cpu";
 101                         compatible = "arm,cortex-a7";
 102                         reg = <0x102>;
 103                         clock-frequency = <780000000>;
 104                 };
 105
 106                 cpu7: cpu@7 {
 107                         device_type = "cpu";
 108                         compatible = "arm,cortex-a7";
 109                         reg = <0x103>;
 110                         clock-frequency = <780000000>;
 111                 };
 112         };
 113
 114         gic: interrupt-controller@f1001000 {
 115                 compatible = "arm,cortex-a15-gic";
 116                 #interrupt-cells = <3>;
 117                 #address-cells = <0>;
 118                 interrupt-controller;
 119                 reg = <0 0xf1001000 0 0x1000>,
 120                         <0 0xf1002000 0 0x1000>,
 121                         <0 0xf1004000 0 0x2000>,
 122                         <0 0xf1006000 0 0x2000>;
 123                 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 124         };
 125
 126         gpio0: gpio@e6050000 {
 127                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 128                 reg = <0 0xe6050000 0 0x50>;
 129                 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
 130                 #gpio-cells = <2>;
 131                 gpio-controller;
 132                 gpio-ranges = <&pfc 0 0 32>;
 133                 #interrupt-cells = <2>;
 134                 interrupt-controller;
 135                 clocks = <&mstp9_clks R8A7790_CLK_GPIO0>;
 136         };
 137
 138         gpio1: gpio@e6051000 {
 139                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 140                 reg = <0 0xe6051000 0 0x50>;
 141                 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
 142                 #gpio-cells = <2>;
 143                 gpio-controller;
 144                 gpio-ranges = <&pfc 0 32 32>;
 145                 #interrupt-cells = <2>;
 146                 interrupt-controller;
 147                 clocks = <&mstp9_clks R8A7790_CLK_GPIO1>;
 148         };
 149
 150         gpio2: gpio@e6052000 {
 151                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 152                 reg = <0 0xe6052000 0 0x50>;
 153                 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
 154                 #gpio-cells = <2>;
 155                 gpio-controller;
 156                 gpio-ranges = <&pfc 0 64 32>;
 157                 #interrupt-cells = <2>;
 158                 interrupt-controller;
 159                 clocks = <&mstp9_clks R8A7790_CLK_GPIO2>;
 160         };
 161
 162         gpio3: gpio@e6053000 {
 163                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 164                 reg = <0 0xe6053000 0 0x50>;
 165                 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
 166                 #gpio-cells = <2>;
 167                 gpio-controller;
 168                 gpio-ranges = <&pfc 0 96 32>;
 169                 #interrupt-cells = <2>;
 170                 interrupt-controller;
 171                 clocks = <&mstp9_clks R8A7790_CLK_GPIO3>;
 172         };
 173
 174         gpio4: gpio@e6054000 {
 175                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 176                 reg = <0 0xe6054000 0 0x50>;
 177                 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
 178                 #gpio-cells = <2>;
 179                 gpio-controller;
 180                 gpio-ranges = <&pfc 0 128 32>;
 181                 #interrupt-cells = <2>;
 182                 interrupt-controller;
 183                 clocks = <&mstp9_clks R8A7790_CLK_GPIO4>;
 184         };
 185
 186         gpio5: gpio@e6055000 {
 187                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 188                 reg = <0 0xe6055000 0 0x50>;
 189                 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
 190                 #gpio-cells = <2>;
 191                 gpio-controller;
 192                 gpio-ranges = <&pfc 0 160 32>;
 193                 #interrupt-cells = <2>;
 194                 interrupt-controller;
 195                 clocks = <&mstp9_clks R8A7790_CLK_GPIO5>;
 196         };
 197
 198         thermal@e61f0000 {
 199                 compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";
 200                 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
 201                 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
 202                 clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
 203         };
 204
 205         timer {
 206                 compatible = "arm,armv7-timer";
 207                 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 208                              <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 209                              <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 210                              <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 211         };
 212
 213         irqc0: interrupt-controller@e61c0000 {
 214                 compatible = "renesas,irqc-r8a7790", "renesas,irqc";
 215                 #interrupt-cells = <2>;
 216                 interrupt-controller;
 217                 reg = <0 0xe61c0000 0 0x200>;
 218                 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
 219                              <0 1 IRQ_TYPE_LEVEL_HIGH>,
 220                              <0 2 IRQ_TYPE_LEVEL_HIGH>,
 221                              <0 3 IRQ_TYPE_LEVEL_HIGH>;
 222         };
 223
 224         dmac0: dma-controller@e6700000 {
 225                 compatible = "renesas,rcar-dmac";
 226                 reg = <0 0xe6700000 0 0x20000>;
 227                 interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
 228                               0 200 IRQ_TYPE_LEVEL_HIGH
 229                               0 201 IRQ_TYPE_LEVEL_HIGH
 230                               0 202 IRQ_TYPE_LEVEL_HIGH
 231                               0 203 IRQ_TYPE_LEVEL_HIGH
 232                               0 204 IRQ_TYPE_LEVEL_HIGH
 233                               0 205 IRQ_TYPE_LEVEL_HIGH
 234                               0 206 IRQ_TYPE_LEVEL_HIGH
 235                               0 207 IRQ_TYPE_LEVEL_HIGH
 236                               0 208 IRQ_TYPE_LEVEL_HIGH
 237                               0 209 IRQ_TYPE_LEVEL_HIGH
 238                               0 210 IRQ_TYPE_LEVEL_HIGH
 239                               0 211 IRQ_TYPE_LEVEL_HIGH
 240                               0 212 IRQ_TYPE_LEVEL_HIGH
 241                               0 213 IRQ_TYPE_LEVEL_HIGH
 242                               0 214 IRQ_TYPE_LEVEL_HIGH>;
 243                 interrupt-names = "error",
 244                                 "ch0", "ch1", "ch2", "ch3",
 245                                 "ch4", "ch5", "ch6", "ch7",
 246                                 "ch8", "ch9", "ch10", "ch11",
 247                                 "ch12", "ch13", "ch14";
 248                 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
 249                 clock-names = "fck";
 250                 #dma-cells = <1>;
 251                 dma-channels = <15>;
 252         };
 253
 254         dmac1: dma-controller@e6720000 {
 255                 compatible = "renesas,rcar-dmac";
 256                 reg = <0 0xe6720000 0 0x20000>;
 257                 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
 258                               0 216 IRQ_TYPE_LEVEL_HIGH
 259                               0 217 IRQ_TYPE_LEVEL_HIGH
 260                               0 218 IRQ_TYPE_LEVEL_HIGH
 261                               0 219 IRQ_TYPE_LEVEL_HIGH
 262                               0 308 IRQ_TYPE_LEVEL_HIGH
 263                               0 309 IRQ_TYPE_LEVEL_HIGH
 264                               0 310 IRQ_TYPE_LEVEL_HIGH
 265                               0 311 IRQ_TYPE_LEVEL_HIGH
 266                               0 312 IRQ_TYPE_LEVEL_HIGH
 267                               0 313 IRQ_TYPE_LEVEL_HIGH
 268                               0 314 IRQ_TYPE_LEVEL_HIGH
 269                               0 315 IRQ_TYPE_LEVEL_HIGH
 270                               0 316 IRQ_TYPE_LEVEL_HIGH
 271                               0 317 IRQ_TYPE_LEVEL_HIGH
 272                               0 318 IRQ_TYPE_LEVEL_HIGH>;
 273                 interrupt-names = "error",
 274                                 "ch0", "ch1", "ch2", "ch3",
 275                                 "ch4", "ch5", "ch6", "ch7",
 276                                 "ch8", "ch9", "ch10", "ch11",
 277                                 "ch12", "ch13", "ch14";
 278                 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
 279                 clock-names = "fck";
 280                 #dma-cells = <1>;
 281                 dma-channels = <15>;
 282         };
 283         i2c0: i2c@e6508000 {
 284                 #address-cells = <1>;
 285                 #size-cells = <0>;
 286                 compatible = "renesas,i2c-r8a7790";
 287                 reg = <0 0xe6508000 0 0x40>;
 288                 interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
 289                 clocks = <&mstp9_clks R8A7790_CLK_I2C0>;
 290                 status = "disabled";
 291         };
 292
 293         i2c1: i2c@e6518000 {
 294                 #address-cells = <1>;
 295                 #size-cells = <0>;
 296                 compatible = "renesas,i2c-r8a7790";
 297                 reg = <0 0xe6518000 0 0x40>;
 298                 interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
 299                 clocks = <&mstp9_clks R8A7790_CLK_I2C1>;
 300                 status = "disabled";
 301         };
 302
 303         i2c2: i2c@e6530000 {
 304                 #address-cells = <1>;
 305                 #size-cells = <0>;
 306                 compatible = "renesas,i2c-r8a7790";
 307                 reg = <0 0xe6530000 0 0x40>;
 308                 interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
 309                 clocks = <&mstp9_clks R8A7790_CLK_I2C2>;
 310                 status = "disabled";
 311         };
 312
 313         i2c3: i2c@e6540000 {
 314                 #address-cells = <1>;
 315                 #size-cells = <0>;
 316                 compatible = "renesas,i2c-r8a7790";
 317                 reg = <0 0xe6540000 0 0x40>;
 318                 interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
 319                 clocks = <&mstp9_clks R8A7790_CLK_I2C3>;
 320                 status = "disabled";
 321         };
 322
 323         iic0: i2c@e6500000 {
 324                 #address-cells = <1>;
 325                 #size-cells = <0>;
 326                 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
 327                 reg = <0 0xe6500000 0 0x425>;
 328                 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
 329                 clocks = <&mstp3_clks R8A7790_CLK_IIC0>;
 330                 status = "disabled";
 331         };
 332
 333         iic1: i2c@e6510000 {
 334                 #address-cells = <1>;
 335                 #size-cells = <0>;
 336                 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
 337                 reg = <0 0xe6510000 0 0x425>;
 338                 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
 339                 clocks = <&mstp3_clks R8A7790_CLK_IIC1>;
 340                 status = "disabled";
 341         };
 342
 343         iic2: i2c@e6520000 {
 344                 #address-cells = <1>;
 345                 #size-cells = <0>;
 346                 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
 347                 reg = <0 0xe6520000 0 0x425>;
 348                 interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>;
 349                 clocks = <&mstp3_clks R8A7790_CLK_IIC2>;
 350                 status = "disabled";
 351         };
 352
 353         iic3: i2c@e60b0000 {
 354                 #address-cells = <1>;
 355                 #size-cells = <0>;
 356                 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
 357                 reg = <0 0xe60b0000 0 0x425>;
 358                 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
 359                 clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>;
 360                 status = "disabled";
 361         };
 362
 363         mmcif0: mmcif@ee200000 {
 364                 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
 365                 reg = <0 0xee200000 0 0x80>;
 366                 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
 367                 clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
 368                 reg-io-width = <4>;
 369                 status = "disabled";
 370         };
 371
 372         mmcif1: mmc@ee220000 {
 373                 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
 374                 reg = <0 0xee220000 0 0x80>;
 375                 interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
 376                 clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
 377                 reg-io-width = <4>;
 378                 status = "disabled";
 379         };
 380
 381         pfc: pfc@e6060000 {
 382                 compatible = "renesas,pfc-r8a7790";
 383                 reg = <0 0xe6060000 0 0x250>;
 384         };
 385
 386         sdhi0: sd@ee100000 {
 387                 compatible = "renesas,sdhi-r8a7790";
 388                 reg = <0 0xee100000 0 0x200>;
 389                 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
 390                 clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
 391                 cap-sd-highspeed;
 392                 status = "disabled";
 393         };
 394
 395         sdhi1: sd@ee120000 {
 396                 compatible = "renesas,sdhi-r8a7790";
 397                 reg = <0 0xee120000 0 0x200>;
 398                 interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
 399                 clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
 400                 cap-sd-highspeed;
 401                 status = "disabled";
 402         };
 403
 404         sdhi2: sd@ee140000 {
 405                 compatible = "renesas,sdhi-r8a7790";
 406                 reg = <0 0xee140000 0 0x100>;
 407                 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
 408                 clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
 409                 cap-sd-highspeed;
 410                 status = "disabled";
 411         };
 412
 413         sdhi3: sd@ee160000 {
 414                 compatible = "renesas,sdhi-r8a7790";
 415                 reg = <0 0xee160000 0 0x100>;
 416                 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
 417                 clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
 418                 cap-sd-highspeed;
 419                 status = "disabled";
 420         };
 421
 422         scifa0: serial@e6c40000 {
 423                 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
 424                 reg = <0 0xe6c40000 0 64>;
 425                 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
 426                 clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>;
 427                 clock-names = "sci_ick";
 428                 status = "disabled";
 429         };
 430
 431         scifa1: serial@e6c50000 {
 432                 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
 433                 reg = <0 0xe6c50000 0 64>;
 434                 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
 435                 clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>;
 436                 clock-names = "sci_ick";
 437                 status = "disabled";
 438         };
 439
 440         scifa2: serial@e6c60000 {
 441                 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
 442                 reg = <0 0xe6c60000 0 64>;
 443                 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
 444                 clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>;
 445                 clock-names = "sci_ick";
 446                 status = "disabled";
 447         };
 448
 449         scifb0: serial@e6c20000 {
 450                 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
 451                 reg = <0 0xe6c20000 0 64>;
 452                 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
 453                 clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>;
 454                 clock-names = "sci_ick";
 455                 status = "disabled";
 456         };
 457
 458         scifb1: serial@e6c30000 {
 459                 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
 460                 reg = <0 0xe6c30000 0 64>;
 461                 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
 462                 clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>;
 463                 clock-names = "sci_ick";
 464                 status = "disabled";
 465         };
 466
 467         scifb2: serial@e6ce0000 {
 468                 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
 469                 reg = <0 0xe6ce0000 0 64>;
 470                 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
 471                 clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>;
 472                 clock-names = "sci_ick";
 473                 status = "disabled";
 474         };
 475
 476         scif0: serial@e6e60000 {
 477                 compatible = "renesas,scif-r8a7790", "renesas,scif";
 478                 reg = <0 0xe6e60000 0 64>;
 479                 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
 480                 clocks = <&mstp7_clks R8A7790_CLK_SCIF0>;
 481                 clock-names = "sci_ick";
 482                 status = "disabled";
 483         };
 484
 485         scif1: serial@e6e68000 {
 486                 compatible = "renesas,scif-r8a7790", "renesas,scif";
 487                 reg = <0 0xe6e68000 0 64>;
 488                 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
 489                 clocks = <&mstp7_clks R8A7790_CLK_SCIF1>;
 490                 clock-names = "sci_ick";
 491                 status = "disabled";
 492         };
 493
 494         hscif0: serial@e62c0000 {
 495                 compatible = "renesas,hscif-r8a7790", "renesas,hscif";
 496                 reg = <0 0xe62c0000 0 96>;
 497                 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
 498                 clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>;
 499                 clock-names = "sci_ick";
 500                 status = "disabled";
 501         };
 502
 503         hscif1: serial@e62c8000 {
 504                 compatible = "renesas,hscif-r8a7790", "renesas,hscif";
 505                 reg = <0 0xe62c8000 0 96>;
 506                 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
 507                 clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>;
 508                 clock-names = "sci_ick";
 509                 status = "disabled";
 510         };
 511
 512         ether: ethernet@ee700000 {
 513                 compatible = "renesas,ether-r8a7790";
 514                 reg = <0 0xee700000 0 0x400>;
 515                 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
 516                 clocks = <&mstp8_clks R8A7790_CLK_ETHER>;
 517                 phy-mode = "rmii";
 518                 #address-cells = <1>;
 519                 #size-cells = <0>;
 520                 status = "disabled";
 521         };
 522
 523         sata0: sata@ee300000 {
 524                 compatible = "renesas,sata-r8a7790";
 525                 reg = <0 0xee300000 0 0x2000>;
 526                 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
 527                 clocks = <&mstp8_clks R8A7790_CLK_SATA0>;
 528                 status = "disabled";
 529         };
 530
 531         sata1: sata@ee500000 {
 532                 compatible = "renesas,sata-r8a7790";
 533                 reg = <0 0xee500000 0 0x2000>;
 534                 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
 535                 clocks = <&mstp8_clks R8A7790_CLK_SATA1>;
 536                 status = "disabled";
 537         };
 538
 539         vin0: video@e6ef0000 {
 540                 compatible = "renesas,vin-r8a7790";
 541                 clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
 542                 reg = <0 0xe6ef0000 0 0x1000>;
 543                 interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
 544                 status = "disabled";
 545         };
 546
 547         vin1: video@e6ef1000 {
 548                 compatible = "renesas,vin-r8a7790";
 549                 clocks = <&mstp8_clks R8A7790_CLK_VIN1>;
 550                 reg = <0 0xe6ef1000 0 0x1000>;
 551                 interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>;
 552                 status = "disabled";
 553         };
 554
 555         vin2: video@e6ef2000 {
 556                 compatible = "renesas,vin-r8a7790";
 557                 clocks = <&mstp8_clks R8A7790_CLK_VIN2>;
 558                 reg = <0 0xe6ef2000 0 0x1000>;
 559                 interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>;
 560                 status = "disabled";
 561         };
 562
 563         vin3: video@e6ef3000 {
 564                 compatible = "renesas,vin-r8a7790";
 565                 clocks = <&mstp8_clks R8A7790_CLK_VIN3>;
 566                 reg = <0 0xe6ef3000 0 0x1000>;
 567                 interrupts = <0 191 IRQ_TYPE_LEVEL_HIGH>;
 568                 status = "disabled";
 569         };
 570
 571         clocks {
 572                 #address-cells = <2>;
 573                 #size-cells = <2>;
 574                 ranges;
 575
 576                 /* External root clock */
 577                 extal_clk: extal_clk {
 578                         compatible = "fixed-clock";
 579                         #clock-cells = <0>;
 580                         /* This value must be overriden by the board. */
 581                         clock-frequency = <0>;
 582                         clock-output-names = "extal";
 583                 };
 584
 585                 /* External PCIe clock - can be overridden by the board */
 586                 pcie_bus_clk: pcie_bus_clk {
 587                         compatible = "fixed-clock";
 588                         #clock-cells = <0>;
 589                         clock-frequency = <100000000>;
 590                         clock-output-names = "pcie_bus";
 591                         status = "disabled";
 592                 };
 593
 594                 /*
 595                  * The external audio clocks are configured as 0 Hz fixed frequency clocks by
 596                  * default. Boards that provide audio clocks should override them.
 597                  */
 598                 audio_clk_a: audio_clk_a {
 599                         compatible = "fixed-clock";
 600                         #clock-cells = <0>;
 601                         clock-frequency = <0>;
 602                         clock-output-names = "audio_clk_a";
 603                 };
 604                 audio_clk_b: audio_clk_b {
 605                         compatible = "fixed-clock";
 606                         #clock-cells = <0>;
 607                         clock-frequency = <0>;
 608                         clock-output-names = "audio_clk_b";
 609                 };
 610                 audio_clk_c: audio_clk_c {
 611                         compatible = "fixed-clock";
 612                         #clock-cells = <0>;
 613                         clock-frequency = <0>;
 614                         clock-output-names = "audio_clk_c";
 615                 };
 616
 617                 /* Special CPG clocks */
 618                 cpg_clocks: cpg_clocks@e6150000 {
 619                         compatible = "renesas,r8a7790-cpg-clocks",
 620                                      "renesas,rcar-gen2-cpg-clocks";
 621                         reg = <0 0xe6150000 0 0x1000>;
 622                         clocks = <&extal_clk>;
 623                         #clock-cells = <1>;
 624                         clock-output-names = "main", "pll0", "pll1", "pll3",
 625                                              "lb", "qspi", "sdh", "sd0", "sd1",
 626                                              "z";
 627                 };
 628
 629                 /* Variable factor clocks */
 630                 sd2_clk: sd2_clk@e6150078 {
 631                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 632                         reg = <0 0xe6150078 0 4>;
 633                         clocks = <&pll1_div2_clk>;
 634                         #clock-cells = <0>;
 635                         clock-output-names = "sd2";
 636                 };
 637                 sd3_clk: sd3_clk@e615007c {
 638                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 639                         reg = <0 0xe615007c 0 4>;
 640                         clocks = <&pll1_div2_clk>;
 641                         #clock-cells = <0>;
 642                         clock-output-names = "sd3";
 643                 };
 644                 mmc0_clk: mmc0_clk@e6150240 {
 645                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 646                         reg = <0 0xe6150240 0 4>;
 647                         clocks = <&pll1_div2_clk>;
 648                         #clock-cells = <0>;
 649                         clock-output-names = "mmc0";
 650                 };
 651                 mmc1_clk: mmc1_clk@e6150244 {
 652                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 653                         reg = <0 0xe6150244 0 4>;
 654                         clocks = <&pll1_div2_clk>;
 655                         #clock-cells = <0>;
 656                         clock-output-names = "mmc1";
 657                 };
 658                 ssp_clk: ssp_clk@e6150248 {
 659                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 660                         reg = <0 0xe6150248 0 4>;
 661                         clocks = <&pll1_div2_clk>;
 662                         #clock-cells = <0>;
 663                         clock-output-names = "ssp";
 664                 };
 665                 ssprs_clk: ssprs_clk@e615024c {
 666                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 667                         reg = <0 0xe615024c 0 4>;
 668                         clocks = <&pll1_div2_clk>;
 669                         #clock-cells = <0>;
 670                         clock-output-names = "ssprs";
 671                 };
 672
 673                 /* Fixed factor clocks */
 674                 pll1_div2_clk: pll1_div2_clk {
 675                         compatible = "fixed-factor-clock";
 676                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 677                         #clock-cells = <0>;
 678                         clock-div = <2>;
 679                         clock-mult = <1>;
 680                         clock-output-names = "pll1_div2";
 681                 };
 682                 z2_clk: z2_clk {
 683                         compatible = "fixed-factor-clock";
 684                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 685                         #clock-cells = <0>;
 686                         clock-div = <2>;
 687                         clock-mult = <1>;
 688                         clock-output-names = "z2";
 689                 };
 690                 zg_clk: zg_clk {
 691                         compatible = "fixed-factor-clock";
 692                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 693                         #clock-cells = <0>;
 694                         clock-div = <3>;
 695                         clock-mult = <1>;
 696                         clock-output-names = "zg";
 697                 };
 698                 zx_clk: zx_clk {
 699                         compatible = "fixed-factor-clock";
 700                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 701                         #clock-cells = <0>;
 702                         clock-div = <3>;
 703                         clock-mult = <1>;
 704                         clock-output-names = "zx";
 705                 };
 706                 zs_clk: zs_clk {
 707                         compatible = "fixed-factor-clock";
 708                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 709                         #clock-cells = <0>;
 710                         clock-div = <6>;
 711                         clock-mult = <1>;
 712                         clock-output-names = "zs";
 713                 };
 714                 hp_clk: hp_clk {
 715                         compatible = "fixed-factor-clock";
 716                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 717                         #clock-cells = <0>;
 718                         clock-div = <12>;
 719                         clock-mult = <1>;
 720                         clock-output-names = "hp";
 721                 };
 722                 i_clk: i_clk {
 723                         compatible = "fixed-factor-clock";
 724                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 725                         #clock-cells = <0>;
 726                         clock-div = <2>;
 727                         clock-mult = <1>;
 728                         clock-output-names = "i";
 729                 };
 730                 b_clk: b_clk {
 731                         compatible = "fixed-factor-clock";
 732                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 733                         #clock-cells = <0>;
 734                         clock-div = <12>;
 735                         clock-mult = <1>;
 736                         clock-output-names = "b";
 737                 };
 738                 p_clk: p_clk {
 739                         compatible = "fixed-factor-clock";
 740                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 741                         #clock-cells = <0>;
 742                         clock-div = <24>;
 743                         clock-mult = <1>;
 744                         clock-output-names = "p";
 745                 };
 746                 cl_clk: cl_clk {
 747                         compatible = "fixed-factor-clock";
 748                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 749                         #clock-cells = <0>;
 750                         clock-div = <48>;
 751                         clock-mult = <1>;
 752                         clock-output-names = "cl";
 753                 };
 754                 m2_clk: m2_clk {
 755                         compatible = "fixed-factor-clock";
 756                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 757                         #clock-cells = <0>;
 758                         clock-div = <8>;
 759                         clock-mult = <1>;
 760                         clock-output-names = "m2";
 761                 };
 762                 imp_clk: imp_clk {
 763                         compatible = "fixed-factor-clock";
 764                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 765                         #clock-cells = <0>;
 766                         clock-div = <4>;
 767                         clock-mult = <1>;
 768                         clock-output-names = "imp";
 769                 };
 770                 rclk_clk: rclk_clk {
 771                         compatible = "fixed-factor-clock";
 772                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 773                         #clock-cells = <0>;
 774                         clock-div = <(48 * 1024)>;
 775                         clock-mult = <1>;
 776                         clock-output-names = "rclk";
 777                 };
 778                 oscclk_clk: oscclk_clk {
 779                         compatible = "fixed-factor-clock";
 780                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 781                         #clock-cells = <0>;
 782                         clock-div = <(12 * 1024)>;
 783                         clock-mult = <1>;
 784                         clock-output-names = "oscclk";
 785                 };
 786                 zb3_clk: zb3_clk {
 787                         compatible = "fixed-factor-clock";
 788                         clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
 789                         #clock-cells = <0>;
 790                         clock-div = <4>;
 791                         clock-mult = <1>;
 792                         clock-output-names = "zb3";
 793                 };
 794                 zb3d2_clk: zb3d2_clk {
 795                         compatible = "fixed-factor-clock";
 796                         clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
 797                         #clock-cells = <0>;
 798                         clock-div = <8>;
 799                         clock-mult = <1>;
 800                         clock-output-names = "zb3d2";
 801                 };
 802                 ddr_clk: ddr_clk {
 803                         compatible = "fixed-factor-clock";
 804                         clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
 805                         #clock-cells = <0>;
 806                         clock-div = <8>;
 807                         clock-mult = <1>;
 808                         clock-output-names = "ddr";
 809                 };
 810                 mp_clk: mp_clk {
 811                         compatible = "fixed-factor-clock";
 812                         clocks = <&pll1_div2_clk>;
 813                         #clock-cells = <0>;
 814                         clock-div = <15>;
 815                         clock-mult = <1>;
 816                         clock-output-names = "mp";
 817                 };
 818                 cp_clk: cp_clk {
 819                         compatible = "fixed-factor-clock";
 820                         clocks = <&extal_clk>;
 821                         #clock-cells = <0>;
 822                         clock-div = <2>;
 823                         clock-mult = <1>;
 824                         clock-output-names = "cp";
 825                 };
 826
 827                 /* Gate clocks */
 828                 mstp0_clks: mstp0_clks@e6150130 {
 829                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 830                         reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
 831                         clocks = <&mp_clk>;
 832                         #clock-cells = <1>;
 833                         renesas,clock-indices = <R8A7790_CLK_MSIOF0>;
 834                         clock-output-names = "msiof0";
 835                 };
 836                 mstp1_clks: mstp1_clks@e6150134 {
 837                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 838                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
 839                         clocks = <&m2_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
 840                                  <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>,
 841                                  <&zs_clk>;
 842                         #clock-cells = <1>;
 843                         renesas,clock-indices = <
 844                                 R8A7790_CLK_JPU R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2
 845                                 R8A7790_CLK_CMT0 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1
 846                                 R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S
 847                         >;
 848                         clock-output-names =
 849                                 "jpu", "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
 850                                 "vsp1-du0", "vsp1-rt", "vsp1-sy";
 851                 };
 852                 mstp2_clks: mstp2_clks@e6150138 {
 853                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 854                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
 855                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
 856                                  <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&zs_clk>,
 857                                  <&zs_clk>;
 858                         #clock-cells = <1>;
 859                         renesas,clock-indices = <
 860                                 R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
 861                                 R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
 862                                 R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
 863                                 R8A7790_CLK_SYS_DMAC1 R8A7790_CLK_SYS_DMAC0
 864                         >;
 865                         clock-output-names =
 866                                 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
 867                                 "scifb1", "msiof1", "msiof3", "scifb2",
 868                                 "sys-dmac1", "sys-dmac0";
 869                 };
 870                 mstp3_clks: mstp3_clks@e615013c {
 871                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 872                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
 873                         clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>,
 874                                  <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>,
 875                                  <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>;
 876                         #clock-cells = <1>;
 877                         renesas,clock-indices = <
 878                                 R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
 879                                 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0
 880                                 R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1
 881                         >;
 882                         clock-output-names =
 883                                 "iic2", "tpu0", "mmcif1", "sdhi3",
 884                                 "sdhi2", "sdhi1", "sdhi0", "mmcif0",
 885                                 "iic0", "pciec", "iic1", "ssusb", "cmt1";
 886                 };
 887                 mstp5_clks: mstp5_clks@e6150144 {
 888                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 889                         reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
 890                         clocks = <&extal_clk>, <&p_clk>;
 891                         #clock-cells = <1>;
 892                         renesas,clock-indices = <R8A7790_CLK_THERMAL R8A7790_CLK_PWM>;
 893                         clock-output-names = "thermal", "pwm";
 894                 };
 895                 mstp7_clks: mstp7_clks@e615014c {
 896                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 897                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
 898                         clocks = <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
 899                                  <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>,
 900                                  <&zx_clk>;
 901                         #clock-cells = <1>;
 902                         renesas,clock-indices = <
 903                                 R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1
 904                                 R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0
 905                                 R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0
 906                                 R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0
 907                         >;
 908                         clock-output-names =
 909                                 "ehci", "hsusb", "hscif1", "hscif0", "scif1",
 910                                 "scif0", "du2", "du1", "du0", "lvds1", "lvds0";
 911                 };
 912                 mstp8_clks: mstp8_clks@e6150990 {
 913                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 914                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
 915                         clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>,
 916                                  <&zs_clk>, <&zs_clk>;
 917                         #clock-cells = <1>;
 918                         renesas,clock-indices = <
 919                                 R8A7790_CLK_VIN3 R8A7790_CLK_VIN2 R8A7790_CLK_VIN1
 920                                 R8A7790_CLK_VIN0 R8A7790_CLK_ETHER R8A7790_CLK_SATA1
 921                                 R8A7790_CLK_SATA0
 922                         >;
 923                         clock-output-names =
 924                                 "vin3", "vin2", "vin1", "vin0", "ether", "sata1", "sata0";
 925                 };
 926                 mstp9_clks: mstp9_clks@e6150994 {
 927                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 928                         reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
 929                         clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>,
 930                                  <&cp_clk>, <&cp_clk>, <&cp_clk>,
 931                                  <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>,
 932                                  <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
 933                         #clock-cells = <1>;
 934                         renesas,clock-indices = <
 935                                 R8A7790_CLK_GPIO5 R8A7790_CLK_GPIO4 R8A7790_CLK_GPIO3
 936                                 R8A7790_CLK_GPIO2 R8A7790_CLK_GPIO1 R8A7790_CLK_GPIO0
 937                                 R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS
 938                                 R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 R8A7790_CLK_I2C0
 939                         >;
 940                         clock-output-names =
 941                                 "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
 942                                 "rcan1", "rcan0", "qspi_mod", "iic3",
 943                                 "i2c3", "i2c2", "i2c1", "i2c0";
 944                 };
 945                 mstp10_clks: mstp10_clks@e6150998 {
 946                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 947                         reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
 948                         clocks = <&p_clk>,
 949                                 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
 950                                 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
 951                                 <&p_clk>,
 952                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
 953                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
 954                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
 955                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
 956                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
 957                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>;
 958
 959                         #clock-cells = <1>;
 960                         clock-indices = <
 961                                 R8A7790_CLK_SSI_ALL
 962                                 R8A7790_CLK_SSI9 R8A7790_CLK_SSI8 R8A7790_CLK_SSI7 R8A7790_CLK_SSI6 R8A7790_CLK_SSI5
 963                                 R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2 R8A7790_CLK_SSI1 R8A7790_CLK_SSI0
 964                                 R8A7790_CLK_SCU_ALL
 965                                 R8A7790_CLK_SCU_DVC1 R8A7790_CLK_SCU_DVC0
 966                                 R8A7790_CLK_SCU_SRC9 R8A7790_CLK_SCU_SRC8 R8A7790_CLK_SCU_SRC7 R8A7790_CLK_SCU_SRC6 R8A7790_CLK_SCU_SRC5
 967                                 R8A7790_CLK_SCU_SRC4 R8A7790_CLK_SCU_SRC3 R8A7790_CLK_SCU_SRC2 R8A7790_CLK_SCU_SRC1 R8A7790_CLK_SCU_SRC0
 968                         >;
 969                         clock-output-names =
 970                                 "ssi-all",
 971                                 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
 972                                 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
 973                                 "scu-all",
 974                                 "scu-dvc1", "scu-dvc0",
 975                                 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
 976                                 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
 977                 };
 978         };
 979
 980         qspi: spi@e6b10000 {
 981                 compatible = "renesas,qspi-r8a7790", "renesas,qspi";
 982                 reg = <0 0xe6b10000 0 0x2c>;
 983                 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
 984                 clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>;
 985                 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
 986                 dma-names = "tx", "rx";
 987                 num-cs = <1>;
 988                 #address-cells = <1>;
 989                 #size-cells = <0>;
 990                 status = "disabled";
 991         };
 992
 993         msiof0: spi@e6e20000 {
 994                 compatible = "renesas,msiof-r8a7790";
 995                 reg = <0 0xe6e20000 0 0x0064>, <0 0xe7e20000 0 0x0064>;
 996                 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
 997                 clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>;
 998                 dmas = <&dmac0 0x51>, <&dmac0 0x52>;
 999                 dma-names = "tx", "rx";
1000                 #address-cells = <1>;
1001                 #size-cells = <0>;
1002                 status = "disabled";
1003         };
1004
1005         msiof1: spi@e6e10000 {
1006                 compatible = "renesas,msiof-r8a7790";
1007                 reg = <0 0xe6e10000 0 0x0064>, <0 0xe7e10000 0 0x0064>;
1008                 interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
1009                 clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>;
1010                 dmas = <&dmac0 0x55>, <&dmac0 0x56>;
1011                 dma-names = "tx", "rx";
1012                 #address-cells = <1>;
1013                 #size-cells = <0>;
1014                 status = "disabled";
1015         };
1016
1017         msiof2: spi@e6e00000 {
1018                 compatible = "renesas,msiof-r8a7790";
1019                 reg = <0 0xe6e00000 0 0x0064>, <0 0xe7e00000 0 0x0064>;
1020                 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
1021                 clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>;
1022                 dmas = <&dmac0 0x41>, <&dmac0 0x42>;
1023                 dma-names = "tx", "rx";
1024                 #address-cells = <1>;
1025                 #size-cells = <0>;
1026                 status = "disabled";
1027         };
1028
1029         msiof3: spi@e6c90000 {
1030                 compatible = "renesas,msiof-r8a7790";
1031                 reg = <0 0xe6c90000 0 0x0064>, <0 0xe7c90000 0 0x0064>;
1032                 interrupts = <0 159 IRQ_TYPE_LEVEL_HIGH>;
1033                 clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>;
1034                 dmas = <&dmac0 0x45>, <&dmac0 0x46>;
1035                 dma-names = "tx", "rx";
1036                 #address-cells = <1>;
1037                 #size-cells = <0>;
1038                 status = "disabled";
1039         };
1040
1041         pci0: pci@ee090000 {
1042                 compatible = "renesas,pci-r8a7790";
1043                 device_type = "pci";
1044                 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1045                 reg = <0 0xee090000 0 0xc00>,
1046                       <0 0xee080000 0 0x1100>;
1047                 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1048                 status = "disabled";
1049
1050                 bus-range = <0 0>;
1051                 #address-cells = <3>;
1052                 #size-cells = <2>;
1053                 #interrupt-cells = <1>;
1054                 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
1055                 interrupt-map-mask = <0xff00 0 0 0x7>;
1056                 interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1057                                  0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1058                                  0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
1059         };
1060
1061         pci1: pci@ee0b0000 {
1062                 compatible = "renesas,pci-r8a7790";
1063                 device_type = "pci";
1064                 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1065                 reg = <0 0xee0b0000 0 0xc00>,
1066                       <0 0xee0a0000 0 0x1100>;
1067                 interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
1068                 status = "disabled";
1069
1070                 bus-range = <1 1>;
1071                 #address-cells = <3>;
1072                 #size-cells = <2>;
1073                 #interrupt-cells = <1>;
1074                 ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>;
1075                 interrupt-map-mask = <0xff00 0 0 0x7>;
1076                 interrupt-map = <0x0000 0 0 1 &gic 0 112 IRQ_TYPE_LEVEL_HIGH
1077                                  0x0800 0 0 1 &gic 0 112 IRQ_TYPE_LEVEL_HIGH
1078                                  0x1000 0 0 2 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>;
1079         };
1080
1081         pci2: pci@ee0d0000 {
1082                 compatible = "renesas,pci-r8a7790";
1083                 device_type = "pci";
1084                 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1085                 reg = <0 0xee0d0000 0 0xc00>,
1086                       <0 0xee0c0000 0 0x1100>;
1087                 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
1088                 status = "disabled";
1089
1090                 bus-range = <2 2>;
1091                 #address-cells = <3>;
1092                 #size-cells = <2>;
1093                 #interrupt-cells = <1>;
1094                 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
1095                 interrupt-map-mask = <0xff00 0 0 0x7>;
1096                 interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1097                                  0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1098                                  0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
1099         };
1100
1101         pciec: pcie@fe000000 {
1102                 compatible = "renesas,pcie-r8a7790";
1103                 reg = <0 0xfe000000 0 0x80000>;
1104                 #address-cells = <3>;
1105                 #size-cells = <2>;
1106                 bus-range = <0x00 0xff>;
1107                 device_type = "pci";
1108                 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1109                           0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1110                           0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1111                           0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1112                 /* Map all possible DDR as inbound ranges */
1113                 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
1114                               0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;
1115                 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>,
1116                              <0 117 IRQ_TYPE_LEVEL_HIGH>,
1117                              <0 118 IRQ_TYPE_LEVEL_HIGH>;
1118                 #interrupt-cells = <1>;
1119                 interrupt-map-mask = <0 0 0 0>;
1120                 interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>;
1121                 clocks = <&mstp3_clks R8A7790_CLK_PCIEC>, <&pcie_bus_clk>;
1122                 clock-names = "pcie", "pcie_bus";
1123                 status = "disabled";
1124         };
1125
1126         rcar_sound: rcar_sound@0xec500000 {
1127                 #sound-dai-cells = <1>;
1128                 compatible =  "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2", "renesas,rcar_sound";
1129                 reg =   <0 0xec500000 0 0x1000>, /* SCU */
1130                         <0 0xec5a0000 0 0x100>,  /* ADG */
1131                         <0 0xec540000 0 0x1000>, /* SSIU */
1132                         <0 0xec541000 0 0x1280>; /* SSI */
1133                 clocks = <&mstp10_clks R8A7790_CLK_SSI_ALL>,
1134                         <&mstp10_clks R8A7790_CLK_SSI9>, <&mstp10_clks R8A7790_CLK_SSI8>,
1135                         <&mstp10_clks R8A7790_CLK_SSI7>, <&mstp10_clks R8A7790_CLK_SSI6>,
1136                         <&mstp10_clks R8A7790_CLK_SSI5>, <&mstp10_clks R8A7790_CLK_SSI4>,
1137                         <&mstp10_clks R8A7790_CLK_SSI3>, <&mstp10_clks R8A7790_CLK_SSI2>,
1138                         <&mstp10_clks R8A7790_CLK_SSI1>, <&mstp10_clks R8A7790_CLK_SSI0>,
1139                         <&mstp10_clks R8A7790_CLK_SCU_SRC9>, <&mstp10_clks R8A7790_CLK_SCU_SRC8>,
1140                         <&mstp10_clks R8A7790_CLK_SCU_SRC7>, <&mstp10_clks R8A7790_CLK_SCU_SRC6>,
1141                         <&mstp10_clks R8A7790_CLK_SCU_SRC5>, <&mstp10_clks R8A7790_CLK_SCU_SRC4>,
1142                         <&mstp10_clks R8A7790_CLK_SCU_SRC3>, <&mstp10_clks R8A7790_CLK_SCU_SRC2>,
1143                         <&mstp10_clks R8A7790_CLK_SCU_SRC1>, <&mstp10_clks R8A7790_CLK_SCU_SRC0>,
1144                         <&mstp10_clks R8A7790_CLK_SCU_DVC0>, <&mstp10_clks R8A7790_CLK_SCU_DVC1>,
1145                         <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1146                 clock-names = "ssi-all",
1147                                 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1148                                 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1149                                 "src.9", "src.8", "src.7", "src.6", "src.5",
1150                                 "src.4", "src.3", "src.2", "src.1", "src.0",
1151                                 "dvc.0", "dvc.1",
1152                                 "clk_a", "clk_b", "clk_c", "clk_i";
1153
1154                 status = "disabled";
1155
1156                 rcar_sound,dvc {
1157                         dvc0: dvc@0 { };
1158                         dvc1: dvc@1 { };
1159                 };
1160
1161                 rcar_sound,src {
1162                         src0: src@0 { };
1163                         src1: src@1 { };
1164                         src2: src@2 { };
1165                         src3: src@3 { };
1166                         src4: src@4 { };
1167                         src5: src@5 { };
1168                         src6: src@6 { };
1169                         src7: src@7 { };
1170                         src8: src@8 { };
1171                         src9: src@9 { };
1172                 };
1173
1174                 rcar_sound,ssi {
1175                         ssi0: ssi@0 { interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; };
1176                         ssi1: ssi@1 { interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; };
1177                         ssi2: ssi@2 { interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; };
1178                         ssi3: ssi@3 { interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; };
1179                         ssi4: ssi@4 { interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; };
1180                         ssi5: ssi@5 { interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; };
1181                         ssi6: ssi@6 { interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; };
1182                         ssi7: ssi@7 { interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; };
1183                         ssi8: ssi@8 { interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; };
1184                         ssi9: ssi@9 { interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; };
1185                 };
1186         };
1187 };