arch/arm/boot/dts/r8a77470.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for the r8a77470 SoC
   4  *
   5  * Copyright (C) 2018 Renesas Electronics Corp.
   6  */
   7
   8 #include <dt-bindings/interrupt-controller/irq.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/clock/r8a77470-cpg-mssr.h>
  11 #include <dt-bindings/power/r8a77470-sysc.h>
  12 / {
  13         compatible = "renesas,r8a77470";
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16
  17         cpus {
  18                 #address-cells = <1>;
  19                 #size-cells = <0>;
  20                 enable-method = "renesas,apmu";
  21
  22                 cpu0: cpu@0 {
  23                         device_type = "cpu";
  24                         compatible = "arm,cortex-a7";
  25                         reg = <0>;
  26                         clock-frequency = <1000000000>;
  27                         clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;
  28                         power-domains = <&sysc R8A77470_PD_CA7_CPU0>;
  29                         next-level-cache = <&L2_CA7>;
  30                 };
  31
  32                 cpu1: cpu@1 {
  33                         device_type = "cpu";
  34                         compatible = "arm,cortex-a7";
  35                         reg = <1>;
  36                         clock-frequency = <1000000000>;
  37                         clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;
  38                         power-domains = <&sysc R8A77470_PD_CA7_CPU1>;
  39                         next-level-cache = <&L2_CA7>;
  40                 };
  41
  42                 L2_CA7: cache-controller-0 {
  43                         compatible = "cache";
  44                         cache-unified;
  45                         cache-level = <2>;
  46                         power-domains = <&sysc R8A77470_PD_CA7_SCU>;
  47                 };
  48         };
  49
  50         /* External root clock */
  51         extal_clk: extal {
  52                 compatible = "fixed-clock";
  53                 #clock-cells = <0>;
  54                 /* This value must be overridden by the board. */
  55                 clock-frequency = <0>;
  56         };
  57
  58         /* External SCIF clock */
  59         scif_clk: scif {
  60                 compatible = "fixed-clock";
  61                 #clock-cells = <0>;
  62                 /* This value must be overridden by the board. */
  63                 clock-frequency = <0>;
  64         };
  65
  66         soc {
  67                 compatible = "simple-bus";
  68                 interrupt-parent = <&gic>;
  69
  70                 #address-cells = <2>;
  71                 #size-cells = <2>;
  72                 ranges;
  73
  74                 gpio0: gpio@e6050000 {
  75                         compatible = "renesas,gpio-r8a77470",
  76                                      "renesas,rcar-gen2-gpio";
  77                         reg = <0 0xe6050000 0 0x50>;
  78                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
  79                         #gpio-cells = <2>;
  80                         gpio-controller;
  81                         gpio-ranges = <&pfc 0 0 23>;
  82                         #interrupt-cells = <2>;
  83                         interrupt-controller;
  84                         clocks = <&cpg CPG_MOD 912>;
  85                         power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
  86                         resets = <&cpg 912>;
  87                 };
  88
  89                 gpio1: gpio@e6051000 {
  90                         compatible = "renesas,gpio-r8a77470",
  91                                      "renesas,rcar-gen2-gpio";
  92                         reg = <0 0xe6051000 0 0x50>;
  93                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
  94                         #gpio-cells = <2>;
  95                         gpio-controller;
  96                         gpio-ranges = <&pfc 0 32 23>;
  97                         #interrupt-cells = <2>;
  98                         interrupt-controller;
  99                         clocks = <&cpg CPG_MOD 911>;
 100                         power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
 101                         resets = <&cpg 911>;
 102                 };
 103
 104                 gpio2: gpio@e6052000 {
 105                         compatible = "renesas,gpio-r8a77470",
 106                                      "renesas,rcar-gen2-gpio";
 107                         reg = <0 0xe6052000 0 0x50>;
 108                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 109                         #gpio-cells = <2>;
 110                         gpio-controller;
 111                         gpio-ranges = <&pfc 0 64 32>;
 112                         #interrupt-cells = <2>;
 113                         interrupt-controller;
 114                         clocks = <&cpg CPG_MOD 910>;
 115                         power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
 116                         resets = <&cpg 910>;
 117                 };
 118
 119                 gpio3: gpio@e6053000 {
 120                         compatible = "renesas,gpio-r8a77470",
 121                                      "renesas,rcar-gen2-gpio";
 122                         reg = <0 0xe6053000 0 0x50>;
 123                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 124                         #gpio-cells = <2>;
 125                         gpio-controller;
 126                         gpio-ranges = <&pfc 0 96 30>;
 127                         gpio-reserved-ranges = <17 10>;
 128                         #interrupt-cells = <2>;
 129                         interrupt-controller;
 130                         clocks = <&cpg CPG_MOD 909>;
 131                         power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
 132                         resets = <&cpg 909>;
 133                 };
 134
 135                 gpio4: gpio@e6054000 {
 136                         compatible = "renesas,gpio-r8a77470",
 137                                      "renesas,rcar-gen2-gpio";
 138                         reg = <0 0xe6054000 0 0x50>;
 139                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 140                         #gpio-cells = <2>;
 141                         gpio-controller;
 142                         gpio-ranges = <&pfc 0 128 26>;
 143                         #interrupt-cells = <2>;
 144                         interrupt-controller;
 145                         clocks = <&cpg CPG_MOD 908>;
 146                         power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
 147                         resets = <&cpg 908>;
 148                 };
 149
 150                 gpio5: gpio@e6055000 {
 151                         compatible = "renesas,gpio-r8a77470",
 152                                      "renesas,rcar-gen2-gpio";
 153                         reg = <0 0xe6055000 0 0x50>;
 154                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 155                         #gpio-cells = <2>;
 156                         gpio-controller;
 157                         gpio-ranges = <&pfc 0 160 32>;
 158                         #interrupt-cells = <2>;
 159                         interrupt-controller;
 160                         clocks = <&cpg CPG_MOD 907>;
 161                         power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
 162                         resets = <&cpg 907>;
 163                 };
 164
 165                 pfc: pin-controller@e6060000 {
 166                         compatible = "renesas,pfc-r8a77470";
 167                         reg = <0 0xe6060000 0 0x118>;
 168                 };
 169
 170                 cpg: clock-controller@e6150000 {
 171                         compatible = "renesas,r8a77470-cpg-mssr";
 172                         reg = <0 0xe6150000 0 0x1000>;
 173                         clocks = <&extal_clk>, <&usb_extal_clk>;
 174                         clock-names = "extal", "usb_extal";
 175                         #clock-cells = <2>;
 176                         #power-domain-cells = <0>;
 177                         #reset-cells = <1>;
 178                 };
 179
 180                 apmu@e6151000 {
 181                         compatible = "renesas,r8a77470-apmu", "renesas,apmu";
 182                         reg = <0 0xe6151000 0 0x188>;
 183                         cpus = <&cpu0 &cpu1>;
 184                 };
 185
 186                 rst: reset-controller@e6160000 {
 187                         compatible = "renesas,r8a77470-rst";
 188                         reg = <0 0xe6160000 0 0x100>;
 189                 };
 190
 191                 sysc: system-controller@e6180000 {
 192                         compatible = "renesas,r8a77470-sysc";
 193                         reg = <0 0xe6180000 0 0x200>;
 194                         #power-domain-cells = <1>;
 195                 };
 196
 197                 irqc: interrupt-controller@e61c0000 {
 198                         compatible = "renesas,irqc-r8a77470", "renesas,irqc";
 199                         #interrupt-cells = <2>;
 200                         interrupt-controller;
 201                         reg = <0 0xe61c0000 0 0x200>;
 202                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 203                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 204                                      <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 205                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 206                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 207                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 208                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 209                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 210                                      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 211                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 212                         clocks = <&cpg CPG_MOD 407>;
 213                         power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
 214                         resets = <&cpg 407>;
 215                 };
 216
 217                 icram0: sram@e63a0000 {
 218                         compatible = "mmio-sram";
 219                         reg = <0 0xe63a0000 0 0x12000>;
 220                 };
 221
 222                 icram1: sram@e63c0000 {
 223                         compatible = "mmio-sram";
 224                         reg = <0 0xe63c0000 0 0x1000>;
 225                         #address-cells = <1>;
 226                         #size-cells = <1>;
 227                         ranges = <0 0 0xe63c0000 0x1000>;
 228
 229                         smp-sram@0 {
 230                                 compatible = "renesas,smp-sram";
 231                                 reg = <0 0x100>;
 232                         };
 233                 };
 234
 235                 icram2: sram@e6300000 {
 236                         compatible = "mmio-sram";
 237                         reg = <0 0xe6300000 0 0x20000>;
 238                 };
 239
 240                 i2c4: i2c@e6520000 {
 241                         #address-cells = <1>;
 242                         #size-cells = <0>;
 243                         compatible = "renesas,i2c-r8a77470",
 244                                      "renesas,rcar-gen2-i2c";
 245                         reg = <0 0xe6520000 0 0x40>;
 246                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 247                         clocks = <&cpg CPG_MOD 927>;
 248                         power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
 249                         resets = <&cpg 927>;
 250                         i2c-scl-internal-delay-ns = <6>;
 251                         status = "disabled";
 252                 };
 253
 254                 dmac0: dma-controller@e6700000 {
 255                         compatible = "renesas,dmac-r8a77470",
 256                                      "renesas,rcar-dmac";
 257                         reg = <0 0xe6700000 0 0x20000>;
 258                         interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
 259                                       GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
 260                                       GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
 261                                       GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
 262                                       GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
 263                                       GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
 264                                       GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
 265                                       GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
 266                                       GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
 267                                       GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
 268                                       GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
 269                                       GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
 270                                       GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
 271                                       GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
 272                                       GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
 273                                       GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
 274                         interrupt-names = "error",
 275                                           "ch0", "ch1", "ch2", "ch3",
 276                                           "ch4", "ch5", "ch6", "ch7",
 277                                           "ch8", "ch9", "ch10", "ch11",
 278                                           "ch12", "ch13", "ch14";
 279                         clocks = <&cpg CPG_MOD 219>;
 280                         clock-names = "fck";
 281                         power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
 282                         resets = <&cpg 219>;
 283                         #dma-cells = <1>;
 284                         dma-channels = <15>;
 285                 };
 286
 287                 dmac1: dma-controller@e6720000 {
 288                         compatible = "renesas,dmac-r8a77470",
 289                                      "renesas,rcar-dmac";
 290                         reg = <0 0xe6720000 0 0x20000>;
 291                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
 292                                       GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
 293                                       GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
 294                                       GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
 295                                       GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
 296                                       GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
 297                                       GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
 298                                       GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
 299                                       GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
 300                                       GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
 301                                       GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
 302                                       GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
 303                                       GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
 304                                       GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
 305                                       GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
 306                                       GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
 307                         interrupt-names = "error",
 308                                           "ch0", "ch1", "ch2", "ch3",
 309                                           "ch4", "ch5", "ch6", "ch7",
 310                                           "ch8", "ch9", "ch10", "ch11",
 311                                           "ch12", "ch13", "ch14";
 312                         clocks = <&cpg CPG_MOD 218>;
 313                         clock-names = "fck";
 314                         power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
 315                         resets = <&cpg 218>;
 316                         #dma-cells = <1>;
 317                         dma-channels = <15>;
 318                 };
 319
 320                 avb: ethernet@e6800000 {
 321                         compatible = "renesas,etheravb-r8a77470",
 322                                      "renesas,etheravb-rcar-gen2";
 323                         reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
 324                         interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
 325                         clocks = <&cpg CPG_MOD 812>;
 326                         power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
 327                         resets = <&cpg 812>;
 328                         #address-cells = <1>;
 329                         #size-cells = <0>;
 330                         status = "disabled";
 331                 };
 332
 333                 scif0: serial@e6e60000 {
 334                         compatible = "renesas,scif-r8a77470",
 335                                      "renesas,rcar-gen2-scif", "renesas,scif";
 336                         reg = <0 0xe6e60000 0 0x40>;
 337                         interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 338                         clocks = <&cpg CPG_MOD 721>,
 339                                  <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>;
 340                         clock-names = "fck", "brg_int", "scif_clk";
 341                         dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
 342                                <&dmac1 0x29>, <&dmac1 0x2a>;
 343                         dma-names = "tx", "rx", "tx", "rx";
 344                         power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
 345                         resets = <&cpg 721>;
 346                         status = "disabled";
 347                 };
 348
 349                 scif1: serial@e6e68000 {
 350                         compatible = "renesas,scif-r8a77470",
 351                                      "renesas,rcar-gen2-scif", "renesas,scif";
 352                         reg = <0 0xe6e68000 0 0x40>;
 353                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 354                         clocks = <&cpg CPG_MOD 720>,
 355                                  <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>;
 356                         clock-names = "fck", "brg_int", "scif_clk";
 357                         dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
 358                                <&dmac1 0x2d>, <&dmac1 0x2e>;
 359                         dma-names = "tx", "rx", "tx", "rx";
 360                         power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
 361                         resets = <&cpg 720>;
 362                         status = "disabled";
 363                 };
 364
 365                 scif2: serial@e6e58000 {
 366                         compatible = "renesas,scif-r8a77470",
 367                                      "renesas,rcar-gen2-scif", "renesas,scif";
 368                         reg = <0 0xe6e58000 0 0x40>;
 369                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 370                         clocks = <&cpg CPG_MOD 719>,
 371                                  <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>;
 372                         clock-names = "fck", "brg_int", "scif_clk";
 373                         dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
 374                                <&dmac1 0x2b>, <&dmac1 0x2c>;
 375                         dma-names = "tx", "rx", "tx", "rx";
 376                         power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
 377                         resets = <&cpg 719>;
 378                         status = "disabled";
 379                 };
 380
 381                 scif3: serial@e6ea8000 {
 382                         compatible = "renesas,scif-r8a77470",
 383                                      "renesas,rcar-gen2-scif", "renesas,scif";
 384                         reg = <0 0xe6ea8000 0 0x40>;
 385                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 386                         clocks = <&cpg CPG_MOD 718>,
 387                                  <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>;
 388                         clock-names = "fck", "brg_int", "scif_clk";
 389                         dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
 390                                <&dmac1 0x2f>, <&dmac1 0x30>;
 391                         dma-names = "tx", "rx", "tx", "rx";
 392                         power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
 393                         resets = <&cpg 718>;
 394                         status = "disabled";
 395                 };
 396
 397                 scif4: serial@e6ee0000 {
 398                         compatible = "renesas,scif-r8a77470",
 399                                      "renesas,rcar-gen2-scif", "renesas,scif";
 400                         reg = <0 0xe6ee0000 0 0x40>;
 401                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 402                         clocks = <&cpg CPG_MOD 715>,
 403                                  <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>;
 404                         clock-names = "fck", "brg_int", "scif_clk";
 405                         dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
 406                                <&dmac1 0xfb>, <&dmac1 0xfc>;
 407                         dma-names = "tx", "rx", "tx", "rx";
 408                         power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
 409                         resets = <&cpg 715>;
 410                         status = "disabled";
 411                 };
 412
 413                 scif5: serial@e6ee8000 {
 414                         compatible = "renesas,scif-r8a77470",
 415                                      "renesas,rcar-gen2-scif", "renesas,scif";
 416                         reg = <0 0xe6ee8000 0 0x40>;
 417                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 418                         clocks = <&cpg CPG_MOD 714>,
 419                                  <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>;
 420                         clock-names = "fck", "brg_int", "scif_clk";
 421                         dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
 422                                <&dmac1 0xfd>, <&dmac1 0xfe>;
 423                         dma-names = "tx", "rx", "tx", "rx";
 424                         power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
 425                         resets = <&cpg 714>;
 426                         status = "disabled";
 427                 };
 428
 429                 sdhi2: sd@ee160000 {
 430                         compatible = "renesas,sdhi-r8a77470",
 431                                      "renesas,rcar-gen2-sdhi";
 432                         reg = <0 0xee160000 0 0x328>;
 433                         interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
 434                         clocks = <&cpg CPG_MOD 312>;
 435                         dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
 436                                <&dmac1 0xd3>, <&dmac1 0xd4>;
 437                         dma-names = "tx", "rx", "tx", "rx";
 438                         max-frequency = <97500000>;
 439                         power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
 440                         resets = <&cpg 312>;
 441                         status = "disabled";
 442                 };
 443
 444                 gic: interrupt-controller@f1001000 {
 445                         compatible = "arm,gic-400";
 446                         #interrupt-cells = <3>;
 447                         #address-cells = <0>;
 448                         interrupt-controller;
 449                         reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
 450                               <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
 451                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 452                         clocks = <&cpg CPG_MOD 408>;
 453                         clock-names = "clk";
 454                         power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
 455                         resets = <&cpg 408>;
 456                 };
 457
 458                 prr: chipid@ff000044 {
 459                         compatible = "renesas,prr";
 460                         reg = <0 0xff000044 0 4>;
 461                 };
 462         };
 463
 464         timer {
 465                 compatible = "arm,armv7-timer";
 466                 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 467                                       <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 468                                       <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 469                                       <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 470         };
 471
 472         /* External USB clock - can be overridden by the board */
 473         usb_extal_clk: usb_extal {
 474                 compatible = "fixed-clock";
 475                 #clock-cells = <0>;
 476                 clock-frequency = <48000000>;
 477         };
 478 };