arch/arm/boot/dts/r8a7745.dtsi

   1 /*
   2  * Device Tree Source for the r8a7745 SoC
   3  *
   4  * Copyright (C) 2016 Cogent Embedded Inc.
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2. This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 #include <dt-bindings/interrupt-controller/irq.h>
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13 #include <dt-bindings/clock/r8a7745-cpg-mssr.h>
  14 #include <dt-bindings/power/r8a7745-sysc.h>
  15
  16 / {
  17         compatible = "renesas,r8a7745";
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20
  21         cpus {
  22                 #address-cells = <1>;
  23                 #size-cells = <0>;
  24
  25                 cpu0: cpu@0 {
  26                         device_type = "cpu";
  27                         compatible = "arm,cortex-a7";
  28                         reg = <0>;
  29                         clock-frequency = <1000000000>;
  30                         clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>;
  31                         power-domains = <&sysc R8A7745_PD_CA7_CPU0>;
  32                         next-level-cache = <&L2_CA7>;
  33                 };
  34
  35                 L2_CA7: cache-controller-0 {
  36                         compatible = "cache";
  37                         cache-unified;
  38                         cache-level = <2>;
  39                         power-domains = <&sysc R8A7745_PD_CA7_SCU>;
  40                 };
  41         };
  42
  43         soc {
  44                 compatible = "simple-bus";
  45                 interrupt-parent = <&gic>;
  46
  47                 #address-cells = <2>;
  48                 #size-cells = <2>;
  49                 ranges;
  50
  51                 gic: interrupt-controller@f1001000 {
  52                         compatible = "arm,gic-400";
  53                         #interrupt-cells = <3>;
  54                         #address-cells = <0>;
  55                         interrupt-controller;
  56                         reg = <0 0xf1001000 0 0x1000>,
  57                               <0 0xf1002000 0 0x2000>,
  58                               <0 0xf1004000 0 0x2000>,
  59                               <0 0xf1006000 0 0x2000>;
  60                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
  61                                                  IRQ_TYPE_LEVEL_HIGH)>;
  62                         clocks = <&cpg CPG_MOD 408>;
  63                         clock-names = "clk";
  64                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
  65                         resets = <&cpg 408>;
  66                 };
  67
  68                 irqc: interrupt-controller@e61c0000 {
  69                         compatible = "renesas,irqc-r8a7745", "renesas,irqc";
  70                         #interrupt-cells = <2>;
  71                         interrupt-controller;
  72                         reg = <0 0xe61c0000 0 0x200>;
  73                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  74                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
  75                                      <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
  76                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
  77                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
  78                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
  79                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
  80                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
  81                                      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
  82                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
  83                         clocks = <&cpg CPG_MOD 407>;
  84                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
  85                         resets = <&cpg 407>;
  86                 };
  87
  88                 timer {
  89                         compatible = "arm,armv7-timer";
  90                         interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
  91                                                   IRQ_TYPE_LEVEL_LOW)>,
  92                                      <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
  93                                                   IRQ_TYPE_LEVEL_LOW)>,
  94                                      <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
  95                                                   IRQ_TYPE_LEVEL_LOW)>,
  96                                      <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
  97                                                   IRQ_TYPE_LEVEL_LOW)>;
  98                 };
  99
 100                 cpg: clock-controller@e6150000 {
 101                         compatible = "renesas,r8a7745-cpg-mssr";
 102                         reg = <0 0xe6150000 0 0x1000>;
 103                         clocks = <&extal_clk>, <&usb_extal_clk>;
 104                         clock-names = "extal", "usb_extal";
 105                         #clock-cells = <2>;
 106                         #power-domain-cells = <0>;
 107                         #reset-cells = <1>;
 108                 };
 109
 110                 prr: chipid@ff000044 {
 111                         compatible = "renesas,prr";
 112                         reg = <0 0xff000044 0 4>;
 113                 };
 114
 115                 rst: reset-controller@e6160000 {
 116                         compatible = "renesas,r8a7745-rst";
 117                         reg = <0 0xe6160000 0 0x100>;
 118                 };
 119
 120                 sysc: system-controller@e6180000 {
 121                         compatible = "renesas,r8a7745-sysc";
 122                         reg = <0 0xe6180000 0 0x200>;
 123                         #power-domain-cells = <1>;
 124                 };
 125
 126                 dmac0: dma-controller@e6700000 {
 127                         compatible = "renesas,dmac-r8a7745",
 128                                      "renesas,rcar-dmac";
 129                         reg = <0 0xe6700000 0 0x20000>;
 130                         interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
 131                                       GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
 132                                       GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
 133                                       GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
 134                                       GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
 135                                       GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
 136                                       GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
 137                                       GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
 138                                       GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
 139                                       GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
 140                                       GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
 141                                       GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
 142                                       GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
 143                                       GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
 144                                       GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
 145                                       GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
 146                         interrupt-names = "error",
 147                                         "ch0", "ch1", "ch2", "ch3",
 148                                         "ch4", "ch5", "ch6", "ch7",
 149                                         "ch8", "ch9", "ch10", "ch11",
 150                                         "ch12", "ch13", "ch14";
 151                         clocks = <&cpg CPG_MOD 219>;
 152                         clock-names = "fck";
 153                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
 154                         resets = <&cpg 219>;
 155                         #dma-cells = <1>;
 156                         dma-channels = <15>;
 157                 };
 158
 159                 dmac1: dma-controller@e6720000 {
 160                         compatible = "renesas,dmac-r8a7745",
 161                                      "renesas,rcar-dmac";
 162                         reg = <0 0xe6720000 0 0x20000>;
 163                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
 164                                       GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
 165                                       GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
 166                                       GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
 167                                       GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
 168                                       GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
 169                                       GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
 170                                       GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
 171                                       GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
 172                                       GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
 173                                       GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
 174                                       GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
 175                                       GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
 176                                       GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
 177                                       GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
 178                                       GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
 179                         interrupt-names = "error",
 180                                         "ch0", "ch1", "ch2", "ch3",
 181                                         "ch4", "ch5", "ch6", "ch7",
 182                                         "ch8", "ch9", "ch10", "ch11",
 183                                         "ch12", "ch13", "ch14";
 184                         clocks = <&cpg CPG_MOD 218>;
 185                         clock-names = "fck";
 186                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
 187                         resets = <&cpg 218>;
 188                         #dma-cells = <1>;
 189                         dma-channels = <15>;
 190                 };
 191
 192                 scifa0: serial@e6c40000 {
 193                         compatible = "renesas,scifa-r8a7745",
 194                                      "renesas,rcar-gen2-scifa", "renesas,scifa";
 195                         reg = <0 0xe6c40000 0 0x40>;
 196                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 197                         clocks = <&cpg CPG_MOD 204>;
 198                         clock-names = "fck";
 199                         dmas = <&dmac0 0x21>, <&dmac0 0x22>,
 200                                <&dmac1 0x21>, <&dmac1 0x22>;
 201                         dma-names = "tx", "rx", "tx", "rx";
 202                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
 203                         resets = <&cpg 204>;
 204                         status = "disabled";
 205                 };
 206
 207                 scifa1: serial@e6c50000 {
 208                         compatible = "renesas,scifa-r8a7745",
 209                                      "renesas,rcar-gen2-scifa", "renesas,scifa";
 210                         reg = <0 0xe6c50000 0 0x40>;
 211                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 212                         clocks = <&cpg CPG_MOD 203>;
 213                         clock-names = "fck";
 214                         dmas = <&dmac0 0x25>, <&dmac0 0x26>,
 215                                <&dmac1 0x25>, <&dmac1 0x26>;
 216                         dma-names = "tx", "rx", "tx", "rx";
 217                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
 218                         resets = <&cpg 203>;
 219                         status = "disabled";
 220                 };
 221
 222                 scifa2: serial@e6c60000 {
 223                         compatible = "renesas,scifa-r8a7745",
 224                                      "renesas,rcar-gen2-scifa", "renesas,scifa";
 225                         reg = <0 0xe6c60000 0 0x40>;
 226                         interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
 227                         clocks = <&cpg CPG_MOD 202>;
 228                         clock-names = "fck";
 229                         dmas = <&dmac0 0x27>, <&dmac0 0x28>,
 230                                <&dmac1 0x27>, <&dmac1 0x28>;
 231                         dma-names = "tx", "rx", "tx", "rx";
 232                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
 233                         resets = <&cpg 202>;
 234                         status = "disabled";
 235                 };
 236
 237                 scifa3: serial@e6c70000 {
 238                         compatible = "renesas,scifa-r8a7745",
 239                                      "renesas,rcar-gen2-scifa", "renesas,scifa";
 240                         reg = <0 0xe6c70000 0 0x40>;
 241                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 242                         clocks = <&cpg CPG_MOD 1106>;
 243                         clock-names = "fck";
 244                         dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
 245                                <&dmac1 0x1b>, <&dmac1 0x1c>;
 246                         dma-names = "tx", "rx", "tx", "rx";
 247                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
 248                         resets = <&cpg 1106>;
 249                         status = "disabled";
 250                 };
 251
 252                 scifa4: serial@e6c78000 {
 253                         compatible = "renesas,scifa-r8a7745",
 254                                      "renesas,rcar-gen2-scifa", "renesas,scifa";
 255                         reg = <0 0xe6c78000 0 0x40>;
 256                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 257                         clocks = <&cpg CPG_MOD 1107>;
 258                         clock-names = "fck";
 259                         dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
 260                                <&dmac1 0x1f>, <&dmac1 0x20>;
 261                         dma-names = "tx", "rx", "tx", "rx";
 262                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
 263                         resets = <&cpg 1107>;
 264                         status = "disabled";
 265                 };
 266
 267                 scifa5: serial@e6c80000 {
 268                         compatible = "renesas,scifa-r8a7745",
 269                                      "renesas,rcar-gen2-scifa", "renesas,scifa";
 270                         reg = <0 0xe6c80000 0 0x40>;
 271                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 272                         clocks = <&cpg CPG_MOD 1108>;
 273                         clock-names = "fck";
 274                         dmas = <&dmac0 0x23>, <&dmac0 0x24>,
 275                                <&dmac1 0x23>, <&dmac1 0x24>;
 276                         dma-names = "tx", "rx", "tx", "rx";
 277                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
 278                         resets = <&cpg 1108>;
 279                         status = "disabled";
 280                 };
 281
 282                 scifb0: serial@e6c20000 {
 283                         compatible = "renesas,scifb-r8a7745",
 284                                      "renesas,rcar-gen2-scifb", "renesas,scifb";
 285                         reg = <0 0xe6c20000 0 0x100>;
 286                         interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
 287                         clocks = <&cpg CPG_MOD 206>;
 288                         clock-names = "fck";
 289                         dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
 290                                <&dmac1 0x3d>, <&dmac1 0x3e>;
 291                         dma-names = "tx", "rx", "tx", "rx";
 292                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
 293                         resets = <&cpg 206>;
 294                         status = "disabled";
 295                 };
 296
 297                 scifb1: serial@e6c30000 {
 298                         compatible = "renesas,scifb-r8a7745",
 299                                      "renesas,rcar-gen2-scifb", "renesas,scifb";
 300                         reg = <0 0xe6c30000 0 0x100>;
 301                         interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 302                         clocks = <&cpg CPG_MOD 207>;
 303                         clock-names = "fck";
 304                         dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
 305                                <&dmac1 0x19>, <&dmac1 0x1a>;
 306                         dma-names = "tx", "rx", "tx", "rx";
 307                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
 308                         resets = <&cpg 207>;
 309                         status = "disabled";
 310                 };
 311
 312                 scifb2: serial@e6ce0000 {
 313                         compatible = "renesas,scifb-r8a7745",
 314                                      "renesas,rcar-gen2-scifb", "renesas,scifb";
 315                         reg = <0 0xe6ce0000 0 0x100>;
 316                         interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
 317                         clocks = <&cpg CPG_MOD 216>;
 318                         clock-names = "fck";
 319                         dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
 320                                <&dmac1 0x1d>, <&dmac1 0x1e>;
 321                         dma-names = "tx", "rx", "tx", "rx";
 322                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
 323                         resets = <&cpg 216>;
 324                         status = "disabled";
 325                 };
 326
 327                 scif0: serial@e6e60000 {
 328                         compatible = "renesas,scif-r8a7745",
 329                                      "renesas,rcar-gen2-scif", "renesas,scif";
 330                         reg = <0 0xe6e60000 0 0x40>;
 331                         interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 332                         clocks = <&cpg CPG_MOD 721>,
 333                                  <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
 334                         clock-names = "fck", "brg_int", "scif_clk";
 335                         dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
 336                                <&dmac1 0x29>, <&dmac1 0x2a>;
 337                         dma-names = "tx", "rx", "tx", "rx";
 338                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
 339                         resets = <&cpg 721>;
 340                         status = "disabled";
 341                 };
 342
 343                 scif1: serial@e6e68000 {
 344                         compatible = "renesas,scif-r8a7745",
 345                                      "renesas,rcar-gen2-scif", "renesas,scif";
 346                         reg = <0 0xe6e68000 0 0x40>;
 347                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 348                         clocks = <&cpg CPG_MOD 720>,
 349                                  <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
 350                         clock-names = "fck", "brg_int", "scif_clk";
 351                         dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
 352                                <&dmac1 0x2d>, <&dmac1 0x2e>;
 353                         dma-names = "tx", "rx", "tx", "rx";
 354                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
 355                         resets = <&cpg 720>;
 356                         status = "disabled";
 357                 };
 358
 359                 scif2: serial@e6e58000 {
 360                         compatible = "renesas,scif-r8a7745",
 361                                      "renesas,rcar-gen2-scif", "renesas,scif";
 362                         reg = <0 0xe6e58000 0 0x40>;
 363                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 364                         clocks = <&cpg CPG_MOD 719>,
 365                                  <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
 366                         clock-names = "fck", "brg_int", "scif_clk";
 367                         dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
 368                                <&dmac1 0x2b>, <&dmac1 0x2c>;
 369                         dma-names = "tx", "rx", "tx", "rx";
 370                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
 371                         resets = <&cpg 719>;
 372                         status = "disabled";
 373                 };
 374
 375                 scif3: serial@e6ea8000 {
 376                         compatible = "renesas,scif-r8a7745",
 377                                      "renesas,rcar-gen2-scif", "renesas,scif";
 378                         reg = <0 0xe6ea8000 0 0x40>;
 379                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 380                         clocks = <&cpg CPG_MOD 718>,
 381                                  <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
 382                         clock-names = "fck", "brg_int", "scif_clk";
 383                         dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
 384                                <&dmac1 0x2f>, <&dmac1 0x30>;
 385                         dma-names = "tx", "rx", "tx", "rx";
 386                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
 387                         resets = <&cpg 718>;
 388                         status = "disabled";
 389                 };
 390
 391                 scif4: serial@e6ee0000 {
 392                         compatible = "renesas,scif-r8a7745",
 393                                      "renesas,rcar-gen2-scif", "renesas,scif";
 394                         reg = <0 0xe6ee0000 0 0x40>;
 395                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 396                         clocks = <&cpg CPG_MOD 715>,
 397                                  <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
 398                         clock-names = "fck", "brg_int", "scif_clk";
 399                         dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
 400                                <&dmac1 0xfb>, <&dmac1 0xfc>;
 401                         dma-names = "tx", "rx", "tx", "rx";
 402                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
 403                         resets = <&cpg 715>;
 404                         status = "disabled";
 405                 };
 406
 407                 scif5: serial@e6ee8000 {
 408                         compatible = "renesas,scif-r8a7745",
 409                                      "renesas,rcar-gen2-scif", "renesas,scif";
 410                         reg = <0 0xe6ee8000 0 0x40>;
 411                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 412                         clocks = <&cpg CPG_MOD 714>,
 413                                  <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
 414                         clock-names = "fck", "brg_int", "scif_clk";
 415                         dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
 416                                <&dmac1 0xfd>, <&dmac1 0xfe>;
 417                         dma-names = "tx", "rx", "tx", "rx";
 418                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
 419                         resets = <&cpg 714>;
 420                         status = "disabled";
 421                 };
 422
 423                 hscif0: serial@e62c0000 {
 424                         compatible = "renesas,hscif-r8a7745",
 425                                      "renesas,rcar-gen2-hscif", "renesas,hscif";
 426                         reg = <0 0xe62c0000 0 0x60>;
 427                         interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 428                         clocks = <&cpg CPG_MOD 717>,
 429                                  <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
 430                         clock-names = "fck", "brg_int", "scif_clk";
 431                         dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
 432                                <&dmac1 0x39>, <&dmac1 0x3a>;
 433                         dma-names = "tx", "rx", "tx", "rx";
 434                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
 435                         resets = <&cpg 717>;
 436                         status = "disabled";
 437                 };
 438
 439                 hscif1: serial@e62c8000 {
 440                         compatible = "renesas,hscif-r8a7745",
 441                                      "renesas,rcar-gen2-hscif", "renesas,hscif";
 442                         reg = <0 0xe62c8000 0 0x60>;
 443                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 444                         clocks = <&cpg CPG_MOD 716>,
 445                                  <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
 446                         clock-names = "fck", "brg_int", "scif_clk";
 447                         dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
 448                                <&dmac1 0x4d>, <&dmac1 0x4e>;
 449                         dma-names = "tx", "rx", "tx", "rx";
 450                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
 451                         resets = <&cpg 716>;
 452                         status = "disabled";
 453                 };
 454
 455                 hscif2: serial@e62d0000 {
 456                         compatible = "renesas,hscif-r8a7745",
 457                                      "renesas,rcar-gen2-hscif", "renesas,hscif";
 458                         reg = <0 0xe62d0000 0 0x60>;
 459                         interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 460                         clocks = <&cpg CPG_MOD 713>,
 461                                  <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
 462                         clock-names = "fck", "brg_int", "scif_clk";
 463                         dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
 464                                <&dmac1 0x3b>, <&dmac1 0x3c>;
 465                         dma-names = "tx", "rx", "tx", "rx";
 466                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
 467                         resets = <&cpg 713>;
 468                         status = "disabled";
 469                 };
 470
 471                 ether: ethernet@ee700000 {
 472                         compatible = "renesas,ether-r8a7745";
 473                         reg = <0 0xee700000 0 0x400>;
 474                         interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
 475                         clocks = <&cpg CPG_MOD 813>;
 476                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
 477                         resets = <&cpg 813>;
 478                         phy-mode = "rmii";
 479                         #address-cells = <1>;
 480                         #size-cells = <0>;
 481                         status = "disabled";
 482                 };
 483         };
 484
 485         /* External root clock */
 486         extal_clk: extal {
 487                 compatible = "fixed-clock";
 488                 #clock-cells = <0>;
 489                 /* This value must be overridden by the board. */
 490                 clock-frequency = <0>;
 491         };
 492
 493         /* External USB clock - can be overridden by the board */
 494         usb_extal_clk: usb_extal {
 495                 compatible = "fixed-clock";
 496                 #clock-cells = <0>;
 497                 clock-frequency = <48000000>;
 498         };
 499
 500         /* External SCIF clock */
 501         scif_clk: scif {
 502                 compatible = "fixed-clock";
 503                 #clock-cells = <0>;
 504                 /* This value must be overridden by the board. */
 505                 clock-frequency = <0>;
 506         };
 507 };