arch/arm/boot/dts/r8a7740.dtsi

   1 /*
   2  * Device Tree Source for the r8a7740 SoC
   3  *
   4  * Copyright (C) 2012 Renesas Solutions Corp.
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 #include <dt-bindings/clock/r8a7740-clock.h>
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13 #include <dt-bindings/interrupt-controller/irq.h>
  14
  15 / {
  16         compatible = "renesas,r8a7740";
  17         interrupt-parent = <&gic>;
  18         #address-cells = <1>;
  19         #size-cells = <1>;
  20
  21         cpus {
  22                 #address-cells = <1>;
  23                 #size-cells = <0>;
  24                 cpu@0 {
  25                         compatible = "arm,cortex-a9";
  26                         device_type = "cpu";
  27                         reg = <0x0>;
  28                         clock-frequency = <800000000>;
  29                         power-domains = <&pd_a3sm>;
  30                         next-level-cache = <&L2>;
  31                 };
  32         };
  33
  34         gic: interrupt-controller@c2800000 {
  35                 compatible = "arm,pl390";
  36                 #interrupt-cells = <3>;
  37                 interrupt-controller;
  38                 reg = <0xc2800000 0x1000>,
  39                       <0xc2000000 0x1000>;
  40         };
  41
  42         L2: cache-controller@f0100000 {
  43                 compatible = "arm,pl310-cache";
  44                 reg = <0xf0100000 0x1000>;
  45                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
  46                 power-domains = <&pd_a3sm>;
  47                 arm,data-latency = <3 3 3>;
  48                 arm,tag-latency = <2 2 2>;
  49                 arm,shared-override;
  50                 cache-unified;
  51                 cache-level = <2>;
  52         };
  53
  54         dbsc3: memory-controller@fe400000 {
  55                 compatible = "renesas,dbsc3-r8a7740";
  56                 reg = <0xfe400000 0x400>;
  57                 power-domains = <&pd_a4s>;
  58         };
  59
  60         pmu {
  61                 compatible = "arm,cortex-a9-pmu";
  62                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
  63         };
  64
  65         ptm {
  66                 compatible = "arm,coresight-etm3x";
  67                 power-domains = <&pd_d4>;
  68         };
  69
  70         cmt1: timer@e6138000 {
  71                 compatible = "renesas,cmt-48-r8a7740", "renesas,cmt-48";
  72                 reg = <0xe6138000 0x170>;
  73                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
  74                 clocks = <&mstp3_clks R8A7740_CLK_CMT1>;
  75                 clock-names = "fck";
  76                 power-domains = <&pd_c5>;
  77                 status = "disabled";
  78         };
  79
  80         /* irqpin0: IRQ0 - IRQ7 */
  81         irqpin0: interrupt-controller@e6900000 {
  82                 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
  83                 #interrupt-cells = <2>;
  84                 interrupt-controller;
  85                 reg = <0xe6900000 4>,
  86                         <0xe6900010 4>,
  87                         <0xe6900020 1>,
  88                         <0xe6900040 1>,
  89                         <0xe6900060 1>;
  90                 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
  91                               GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
  92                               GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
  93                               GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
  94                               GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
  95                               GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
  96                               GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
  97                               GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
  98                 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
  99                 power-domains = <&pd_a4s>;
 100         };
 101
 102         /* irqpin1: IRQ8 - IRQ15 */
 103         irqpin1: interrupt-controller@e6900004 {
 104                 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
 105                 #interrupt-cells = <2>;
 106                 interrupt-controller;
 107                 reg = <0xe6900004 4>,
 108                         <0xe6900014 4>,
 109                         <0xe6900024 1>,
 110                         <0xe6900044 1>,
 111                         <0xe6900064 1>;
 112                 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
 113                               GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
 114                               GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
 115                               GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
 116                               GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
 117                               GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
 118                               GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
 119                               GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 120                 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
 121                 power-domains = <&pd_a4s>;
 122         };
 123
 124         /* irqpin2: IRQ16 - IRQ23 */
 125         irqpin2: interrupt-controller@e6900008 {
 126                 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
 127                 #interrupt-cells = <2>;
 128                 interrupt-controller;
 129                 reg = <0xe6900008 4>,
 130                         <0xe6900018 4>,
 131                         <0xe6900028 1>,
 132                         <0xe6900048 1>,
 133                         <0xe6900068 1>;
 134                 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
 135                               GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
 136                               GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
 137                               GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
 138                               GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
 139                               GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
 140                               GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
 141                               GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 142                 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
 143                 power-domains = <&pd_a4s>;
 144         };
 145
 146         /* irqpin3: IRQ24 - IRQ31 */
 147         irqpin3: interrupt-controller@e690000c {
 148                 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
 149                 #interrupt-cells = <2>;
 150                 interrupt-controller;
 151                 reg = <0xe690000c 4>,
 152                         <0xe690001c 4>,
 153                         <0xe690002c 1>,
 154                         <0xe690004c 1>,
 155                         <0xe690006c 1>;
 156                 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
 157                               GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
 158                               GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
 159                               GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
 160                               GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
 161                               GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
 162                               GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
 163                               GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 164                 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
 165                 power-domains = <&pd_a4s>;
 166         };
 167
 168         ether: ethernet@e9a00000 {
 169                 compatible = "renesas,gether-r8a7740";
 170                 reg = <0xe9a00000 0x800>,
 171                       <0xe9a01800 0x800>;
 172                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 173                 clocks = <&mstp3_clks R8A7740_CLK_GETHER>;
 174                 power-domains = <&pd_a4s>;
 175                 phy-mode = "mii";
 176                 #address-cells = <1>;
 177                 #size-cells = <0>;
 178                 status = "disabled";
 179         };
 180
 181         i2c0: i2c@fff20000 {
 182                 #address-cells = <1>;
 183                 #size-cells = <0>;
 184                 compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic";
 185                 reg = <0xfff20000 0x425>;
 186                 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
 187                               GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
 188                               GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
 189                               GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
 190                 clocks = <&mstp1_clks R8A7740_CLK_IIC0>;
 191                 power-domains = <&pd_a4r>;
 192                 status = "disabled";
 193         };
 194
 195         i2c1: i2c@e6c20000 {
 196                 #address-cells = <1>;
 197                 #size-cells = <0>;
 198                 compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic";
 199                 reg = <0xe6c20000 0x425>;
 200                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
 201                               GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH
 202                               GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH
 203                               GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 204                 clocks = <&mstp3_clks R8A7740_CLK_IIC1>;
 205                 power-domains = <&pd_a3sp>;
 206                 status = "disabled";
 207         };
 208
 209         scifa0: serial@e6c40000 {
 210                 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
 211                 reg = <0xe6c40000 0x100>;
 212                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 213                 clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>;
 214                 clock-names = "fck";
 215                 power-domains = <&pd_a3sp>;
 216                 status = "disabled";
 217         };
 218
 219         scifa1: serial@e6c50000 {
 220                 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
 221                 reg = <0xe6c50000 0x100>;
 222                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 223                 clocks = <&mstp2_clks R8A7740_CLK_SCIFA1>;
 224                 clock-names = "fck";
 225                 power-domains = <&pd_a3sp>;
 226                 status = "disabled";
 227         };
 228
 229         scifa2: serial@e6c60000 {
 230                 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
 231                 reg = <0xe6c60000 0x100>;
 232                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 233                 clocks = <&mstp2_clks R8A7740_CLK_SCIFA2>;
 234                 clock-names = "fck";
 235                 power-domains = <&pd_a3sp>;
 236                 status = "disabled";
 237         };
 238
 239         scifa3: serial@e6c70000 {
 240                 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
 241                 reg = <0xe6c70000 0x100>;
 242                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 243                 clocks = <&mstp2_clks R8A7740_CLK_SCIFA3>;
 244                 clock-names = "fck";
 245                 power-domains = <&pd_a3sp>;
 246                 status = "disabled";
 247         };
 248
 249         scifa4: serial@e6c80000 {
 250                 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
 251                 reg = <0xe6c80000 0x100>;
 252                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 253                 clocks = <&mstp2_clks R8A7740_CLK_SCIFA4>;
 254                 clock-names = "fck";
 255                 power-domains = <&pd_a3sp>;
 256                 status = "disabled";
 257         };
 258
 259         scifa5: serial@e6cb0000 {
 260                 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
 261                 reg = <0xe6cb0000 0x100>;
 262                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 263                 clocks = <&mstp2_clks R8A7740_CLK_SCIFA5>;
 264                 clock-names = "fck";
 265                 power-domains = <&pd_a3sp>;
 266                 status = "disabled";
 267         };
 268
 269         scifa6: serial@e6cc0000 {
 270                 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
 271                 reg = <0xe6cc0000 0x100>;
 272                 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 273                 clocks = <&mstp2_clks R8A7740_CLK_SCIFA6>;
 274                 clock-names = "fck";
 275                 power-domains = <&pd_a3sp>;
 276                 status = "disabled";
 277         };
 278
 279         scifa7: serial@e6cd0000 {
 280                 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
 281                 reg = <0xe6cd0000 0x100>;
 282                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 283                 clocks = <&mstp2_clks R8A7740_CLK_SCIFA7>;
 284                 clock-names = "fck";
 285                 power-domains = <&pd_a3sp>;
 286                 status = "disabled";
 287         };
 288
 289         scifb: serial@e6c30000 {
 290                 compatible = "renesas,scifb-r8a7740", "renesas,scifb";
 291                 reg = <0xe6c30000 0x100>;
 292                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 293                 clocks = <&mstp2_clks R8A7740_CLK_SCIFB>;
 294                 clock-names = "fck";
 295                 power-domains = <&pd_a3sp>;
 296                 status = "disabled";
 297         };
 298
 299         pfc: pin-controller@e6050000 {
 300                 compatible = "renesas,pfc-r8a7740";
 301                 reg = <0xe6050000 0x8000>,
 302                       <0xe605800c 0x20>;
 303                 gpio-controller;
 304                 #gpio-cells = <2>;
 305                 gpio-ranges = <&pfc 0 0 212>;
 306                 interrupts-extended =
 307                         <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
 308                         <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
 309                         <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
 310                         <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
 311                         <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
 312                         <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
 313                         <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
 314                         <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
 315                 power-domains = <&pd_c5>;
 316         };
 317
 318         tpu: pwm@e6600000 {
 319                 compatible = "renesas,tpu-r8a7740", "renesas,tpu";
 320                 reg = <0xe6600000 0x148>;
 321                 clocks = <&mstp3_clks R8A7740_CLK_TPU0>;
 322                 power-domains = <&pd_a3sp>;
 323                 status = "disabled";
 324                 #pwm-cells = <3>;
 325         };
 326
 327         mmcif0: mmc@e6bd0000 {
 328                 compatible = "renesas,mmcif-r8a7740", "renesas,sh-mmcif";
 329                 reg = <0xe6bd0000 0x100>;
 330                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH
 331                               GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 332                 clocks = <&mstp3_clks R8A7740_CLK_MMC>;
 333                 power-domains = <&pd_a3sp>;
 334                 status = "disabled";
 335         };
 336
 337         sdhi0: sd@e6850000 {
 338                 compatible = "renesas,sdhi-r8a7740";
 339                 reg = <0xe6850000 0x100>;
 340                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH
 341                               GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH
 342                               GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 343                 clocks = <&mstp3_clks R8A7740_CLK_SDHI0>;
 344                 power-domains = <&pd_a3sp>;
 345                 cap-sd-highspeed;
 346                 cap-sdio-irq;
 347                 status = "disabled";
 348         };
 349
 350         sdhi1: sd@e6860000 {
 351                 compatible = "renesas,sdhi-r8a7740";
 352                 reg = <0xe6860000 0x100>;
 353                 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH
 354                               GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH
 355                               GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
 356                 clocks = <&mstp3_clks R8A7740_CLK_SDHI1>;
 357                 power-domains = <&pd_a3sp>;
 358                 cap-sd-highspeed;
 359                 cap-sdio-irq;
 360                 status = "disabled";
 361         };
 362
 363         sdhi2: sd@e6870000 {
 364                 compatible = "renesas,sdhi-r8a7740";
 365                 reg = <0xe6870000 0x100>;
 366                 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH
 367                               GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH
 368                               GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 369                 clocks = <&mstp4_clks R8A7740_CLK_SDHI2>;
 370                 power-domains = <&pd_a3sp>;
 371                 cap-sd-highspeed;
 372                 cap-sdio-irq;
 373                 status = "disabled";
 374         };
 375
 376         sh_fsi2: sound@fe1f0000 {
 377                 #sound-dai-cells = <1>;
 378                 compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2";
 379                 reg = <0xfe1f0000 0x400>;
 380                 interrupts = <GIC_SPI 9 0x4>;
 381                 clocks = <&mstp3_clks R8A7740_CLK_FSI>;
 382                 power-domains = <&pd_a4mp>;
 383                 status = "disabled";
 384         };
 385
 386         tmu0: timer@fff80000 {
 387                 compatible = "renesas,tmu-r8a7740", "renesas,tmu";
 388                 reg = <0xfff80000 0x2c>;
 389                 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
 390                              <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
 391                              <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
 392                 clocks = <&mstp1_clks R8A7740_CLK_TMU0>;
 393                 clock-names = "fck";
 394                 power-domains = <&pd_a4r>;
 395
 396                 #renesas,channels = <3>;
 397
 398                 status = "disabled";
 399         };
 400
 401         tmu1: timer@fff90000 {
 402                 compatible = "renesas,tmu-r8a7740", "renesas,tmu";
 403                 reg = <0xfff90000 0x2c>;
 404                 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 405                              <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
 406                              <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
 407                 clocks = <&mstp1_clks R8A7740_CLK_TMU1>;
 408                 clock-names = "fck";
 409                 power-domains = <&pd_a4r>;
 410
 411                 #renesas,channels = <3>;
 412
 413                 status = "disabled";
 414         };
 415
 416         clocks {
 417                 #address-cells = <1>;
 418                 #size-cells = <1>;
 419                 ranges;
 420
 421                 /* External root clock */
 422                 extalr_clk: extalr {
 423                         compatible = "fixed-clock";
 424                         #clock-cells = <0>;
 425                         clock-frequency = <32768>;
 426                 };
 427                 extal1_clk: extal1 {
 428                         compatible = "fixed-clock";
 429                         #clock-cells = <0>;
 430                         clock-frequency = <0>;
 431                 };
 432                 extal2_clk: extal2 {
 433                         compatible = "fixed-clock";
 434                         #clock-cells = <0>;
 435                         clock-frequency = <0>;
 436                 };
 437                 dv_clk: dv {
 438                         compatible = "fixed-clock";
 439                         #clock-cells = <0>;
 440                         clock-frequency = <27000000>;
 441                 };
 442                 fmsick_clk: fmsick {
 443                         compatible = "fixed-clock";
 444                         #clock-cells = <0>;
 445                         clock-frequency = <0>;
 446                 };
 447                 fmsock_clk: fmsock {
 448                         compatible = "fixed-clock";
 449                         #clock-cells = <0>;
 450                         clock-frequency = <0>;
 451                 };
 452                 fsiack_clk: fsiack {
 453                         compatible = "fixed-clock";
 454                         #clock-cells = <0>;
 455                         clock-frequency = <0>;
 456                 };
 457                 fsibck_clk: fsibck {
 458                         compatible = "fixed-clock";
 459                         #clock-cells = <0>;
 460                         clock-frequency = <0>;
 461                 };
 462
 463                 /* Special CPG clocks */
 464                 cpg_clocks: cpg_clocks@e6150000 {
 465                         compatible = "renesas,r8a7740-cpg-clocks";
 466                         reg = <0xe6150000 0x10000>;
 467                         clocks = <&extal1_clk>, <&extalr_clk>;
 468                         #clock-cells = <1>;
 469                         clock-output-names = "system", "pllc0", "pllc1",
 470                                              "pllc2", "r",
 471                                              "usb24s",
 472                                              "i", "zg", "b", "m1", "hp",
 473                                              "hpp", "usbp", "s", "zb", "m3",
 474                                              "cp";
 475                 };
 476
 477                 /* Variable factor clocks (DIV6) */
 478                 vclk1_clk: vclk1@e6150008 {
 479                         compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
 480                         reg = <0xe6150008 4>;
 481                         clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>,
 482                                  <&cpg_clocks R8A7740_CLK_USB24S>,
 483                                  <&extal1_div2_clk>, <&extalr_clk>, <0>,
 484                                  <0>;
 485                         #clock-cells = <0>;
 486                 };
 487                 vclk2_clk: vclk2@e615000c {
 488                         compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
 489                         reg = <0xe615000c 4>;
 490                         clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>,
 491                                  <&cpg_clocks R8A7740_CLK_USB24S>,
 492                                  <&extal1_div2_clk>, <&extalr_clk>, <0>,
 493                                  <0>;
 494                         #clock-cells = <0>;
 495                 };
 496                 fmsi_clk: fmsi@e6150010 {
 497                         compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
 498                         reg = <0xe6150010 4>;
 499                         clocks = <&pllc1_div2_clk>, <&fmsick_clk>, <0>, <0>;
 500                         #clock-cells = <0>;
 501                 };
 502                 fmso_clk: fmso@e6150014 {
 503                         compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
 504                         reg = <0xe6150014 4>;
 505                         clocks = <&pllc1_div2_clk>, <&fmsock_clk>, <0>, <0>;
 506                         #clock-cells = <0>;
 507                 };
 508                 fsia_clk: fsia@e6150018 {
 509                         compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
 510                         reg = <0xe6150018 4>;
 511                         clocks = <&pllc1_div2_clk>, <&fsiack_clk>, <0>, <0>;
 512                         #clock-cells = <0>;
 513                 };
 514                 sub_clk: sub@e6150080 {
 515                         compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
 516                         reg = <0xe6150080 4>;
 517                         clocks = <&pllc1_div2_clk>,
 518                                  <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>;
 519                         #clock-cells = <0>;
 520                 };
 521                 spu_clk: spu@e6150084 {
 522                         compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
 523                         reg = <0xe6150084 4>;
 524                         clocks = <&pllc1_div2_clk>,
 525                                  <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>;
 526                         #clock-cells = <0>;
 527                 };
 528                 vou_clk: vou@e6150088 {
 529                         compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
 530                         reg = <0xe6150088 4>;
 531                         clocks = <&pllc1_div2_clk>, <&extal1_clk>, <&dv_clk>,
 532                                  <0>;
 533                         #clock-cells = <0>;
 534                 };
 535                 stpro_clk: stpro@e615009c {
 536                         compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
 537                         reg = <0xe615009c 4>;
 538                         clocks = <&cpg_clocks R8A7740_CLK_PLLC0>;
 539                         #clock-cells = <0>;
 540                 };
 541
 542                 /* Fixed factor clocks */
 543                 pllc1_div2_clk: pllc1_div2 {
 544                         compatible = "fixed-factor-clock";
 545                         clocks = <&cpg_clocks R8A7740_CLK_PLLC1>;
 546                         #clock-cells = <0>;
 547                         clock-div = <2>;
 548                         clock-mult = <1>;
 549                 };
 550                 extal1_div2_clk: extal1_div2 {
 551                         compatible = "fixed-factor-clock";
 552                         clocks = <&extal1_clk>;
 553                         #clock-cells = <0>;
 554                         clock-div = <2>;
 555                         clock-mult = <1>;
 556                 };
 557
 558                 /* Gate clocks */
 559                 subck_clks: subck_clks@e6150080 {
 560                         compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
 561                         reg = <0xe6150080 4>;
 562                         clocks = <&sub_clk>, <&sub_clk>;
 563                         #clock-cells = <1>;
 564                         clock-indices = <
 565                                 R8A7740_CLK_SUBCK R8A7740_CLK_SUBCK2
 566                         >;
 567                         clock-output-names =
 568                                 "subck", "subck2";
 569                 };
 570                 mstp1_clks: mstp1_clks@e6150134 {
 571                         compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
 572                         reg = <0xe6150134 4>, <0xe6150038 4>;
 573                         clocks = <&cpg_clocks R8A7740_CLK_S>,
 574                                  <&cpg_clocks R8A7740_CLK_S>, <&sub_clk>,
 575                                  <&cpg_clocks R8A7740_CLK_B>,
 576                                  <&cpg_clocks R8A7740_CLK_HPP>, <&sub_clk>,
 577                                  <&cpg_clocks R8A7740_CLK_B>;
 578                         #clock-cells = <1>;
 579                         clock-indices = <
 580                                 R8A7740_CLK_CEU21 R8A7740_CLK_CEU20 R8A7740_CLK_TMU0
 581                                 R8A7740_CLK_LCDC1 R8A7740_CLK_IIC0 R8A7740_CLK_TMU1
 582                                 R8A7740_CLK_LCDC0
 583                         >;
 584                         clock-output-names =
 585                                 "ceu21", "ceu20", "tmu0", "lcdc1", "iic0",
 586                                 "tmu1", "lcdc0";
 587                 };
 588                 mstp2_clks: mstp2_clks@e6150138 {
 589                         compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
 590                         reg = <0xe6150138 4>, <0xe6150040 4>;
 591                         clocks = <&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>,
 592                                  <&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>,
 593                                  <&cpg_clocks R8A7740_CLK_HP>,
 594                                  <&cpg_clocks R8A7740_CLK_HP>,
 595                                  <&cpg_clocks R8A7740_CLK_HP>,
 596                                  <&sub_clk>, <&sub_clk>, <&sub_clk>,
 597                                  <&sub_clk>, <&sub_clk>, <&sub_clk>,
 598                                  <&sub_clk>;
 599                         #clock-cells = <1>;
 600                         clock-indices = <
 601                                 R8A7740_CLK_SCIFA6 R8A7740_CLK_INTCA
 602                                 R8A7740_CLK_SCIFA7
 603                                 R8A7740_CLK_DMAC1 R8A7740_CLK_DMAC2
 604                                 R8A7740_CLK_DMAC3 R8A7740_CLK_USBDMAC
 605                                 R8A7740_CLK_SCIFA5 R8A7740_CLK_SCIFB
 606                                 R8A7740_CLK_SCIFA0 R8A7740_CLK_SCIFA1
 607                                 R8A7740_CLK_SCIFA2 R8A7740_CLK_SCIFA3
 608                                 R8A7740_CLK_SCIFA4
 609                         >;
 610                         clock-output-names =
 611                                 "scifa6", "intca",
 612                                 "scifa7", "dmac1", "dmac2", "dmac3",
 613                                 "usbdmac", "scifa5", "scifb", "scifa0", "scifa1",
 614                                 "scifa2", "scifa3", "scifa4";
 615                 };
 616                 mstp3_clks: mstp3_clks@e615013c {
 617                         compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
 618                         reg = <0xe615013c 4>, <0xe6150048 4>;
 619                         clocks = <&cpg_clocks R8A7740_CLK_R>,
 620                                  <&cpg_clocks R8A7740_CLK_HP>,
 621                                  <&sub_clk>,
 622                                  <&cpg_clocks R8A7740_CLK_HP>,
 623                                  <&cpg_clocks R8A7740_CLK_HP>,
 624                                  <&cpg_clocks R8A7740_CLK_HP>,
 625                                  <&cpg_clocks R8A7740_CLK_HP>,
 626                                  <&cpg_clocks R8A7740_CLK_HP>,
 627                                  <&cpg_clocks R8A7740_CLK_HP>;
 628                         #clock-cells = <1>;
 629                         clock-indices = <
 630                                 R8A7740_CLK_CMT1 R8A7740_CLK_FSI R8A7740_CLK_IIC1
 631                                 R8A7740_CLK_USBF R8A7740_CLK_SDHI0 R8A7740_CLK_SDHI1
 632                                 R8A7740_CLK_MMC R8A7740_CLK_GETHER R8A7740_CLK_TPU0
 633                         >;
 634                         clock-output-names =
 635                                 "cmt1", "fsi", "iic1", "usbf", "sdhi0", "sdhi1",
 636                                 "mmc", "gether", "tpu0";
 637                 };
 638                 mstp4_clks: mstp4_clks@e6150140 {
 639                         compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
 640                         reg = <0xe6150140 4>, <0xe615004c 4>;
 641                         clocks = <&cpg_clocks R8A7740_CLK_HP>,
 642                                  <&cpg_clocks R8A7740_CLK_HP>,
 643                                  <&cpg_clocks R8A7740_CLK_HP>,
 644                                  <&cpg_clocks R8A7740_CLK_HP>;
 645                         #clock-cells = <1>;
 646                         clock-indices = <
 647                                 R8A7740_CLK_USBH R8A7740_CLK_SDHI2
 648                                 R8A7740_CLK_USBFUNC R8A7740_CLK_USBPHY
 649                         >;
 650                         clock-output-names =
 651                                 "usbhost", "sdhi2", "usbfunc", "usphy";
 652                 };
 653         };
 654
 655         sysc: system-controller@e6180000 {
 656                 compatible = "renesas,sysc-r8a7740", "renesas,sysc-rmobile";
 657                 reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>;
 658
 659                 pm-domains {
 660                         pd_c5: c5 {
 661                                 #address-cells = <1>;
 662                                 #size-cells = <0>;
 663                                 #power-domain-cells = <0>;
 664
 665                                 pd_a4lc: a4lc@1 {
 666                                         reg = <1>;
 667                                         #power-domain-cells = <0>;
 668                                 };
 669
 670                                 pd_a4mp: a4mp@2 {
 671                                         reg = <2>;
 672                                         #power-domain-cells = <0>;
 673                                 };
 674
 675                                 pd_d4: d4@3 {
 676                                         reg = <3>;
 677                                         #power-domain-cells = <0>;
 678                                 };
 679
 680                                 pd_a4r: a4r@5 {
 681                                         reg = <5>;
 682                                         #address-cells = <1>;
 683                                         #size-cells = <0>;
 684                                         #power-domain-cells = <0>;
 685
 686                                         pd_a3rv: a3rv@6 {
 687                                                 reg = <6>;
 688                                                 #power-domain-cells = <0>;
 689                                         };
 690                                 };
 691
 692                                 pd_a4s: a4s@10 {
 693                                         reg = <10>;
 694                                         #address-cells = <1>;
 695                                         #size-cells = <0>;
 696                                         #power-domain-cells = <0>;
 697
 698                                         pd_a3sp: a3sp@11 {
 699                                                 reg = <11>;
 700                                                 #power-domain-cells = <0>;
 701                                         };
 702
 703                                         pd_a3sm: a3sm@12 {
 704                                                 reg = <12>;
 705                                                 #power-domain-cells = <0>;
 706                                         };
 707
 708                                         pd_a3sg: a3sg@13 {
 709                                                 reg = <13>;
 710                                                 #power-domain-cells = <0>;
 711                                         };
 712                                 };
 713
 714                                 pd_a4su: a4su@20 {
 715                                         reg = <20>;
 716                                         #power-domain-cells = <0>;
 717                                 };
 718                         };
 719                 };
 720         };
 721 };