arch/arm/boot/dts/qcom-msm8960.dtsi

   1 /dts-v1/;
   2
   3 /include/ "skeleton.dtsi"
   4
   5 #include <dt-bindings/interrupt-controller/arm-gic.h>
   6 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
   7 #include <dt-bindings/mfd/qcom-rpm.h>
   8 #include <dt-bindings/soc/qcom,gsbi.h>
   9
  10 / {
  11         model = "Qualcomm MSM8960";
  12         compatible = "qcom,msm8960";
  13         interrupt-parent = <&intc>;
  14
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18                 interrupts = <1 14 0x304>;
  19
  20                 cpu@0 {
  21                         compatible = "qcom,krait";
  22                         enable-method = "qcom,kpss-acc-v1";
  23                         device_type = "cpu";
  24                         reg = <0>;
  25                         next-level-cache = <&L2>;
  26                         qcom,acc = <&acc0>;
  27                         qcom,saw = <&saw0>;
  28                 };
  29
  30                 cpu@1 {
  31                         compatible = "qcom,krait";
  32                         enable-method = "qcom,kpss-acc-v1";
  33                         device_type = "cpu";
  34                         reg = <1>;
  35                         next-level-cache = <&L2>;
  36                         qcom,acc = <&acc1>;
  37                         qcom,saw = <&saw1>;
  38                 };
  39
  40                 L2: l2-cache {
  41                         compatible = "cache";
  42                         cache-level = <2>;
  43                 };
  44         };
  45
  46         cpu-pmu {
  47                 compatible = "qcom,krait-pmu";
  48                 interrupts = <1 10 0x304>;
  49                 qcom,no-pc-write;
  50         };
  51
  52         clocks {
  53                 cxo_board {
  54                         compatible = "fixed-clock";
  55                         #clock-cells = <0>;
  56                         clock-frequency = <19200000>;
  57                         clock-output-names = "cxo_board";
  58                 };
  59
  60                 pxo_board {
  61                         compatible = "fixed-clock";
  62                         #clock-cells = <0>;
  63                         clock-frequency = <27000000>;
  64                         clock-output-names = "pxo_board";
  65                 };
  66
  67                 sleep_clk {
  68                         compatible = "fixed-clock";
  69                         #clock-cells = <0>;
  70                         clock-frequency = <32768>;
  71                         clock-output-names = "sleep_clk";
  72                 };
  73         };
  74
  75         soc: soc {
  76                 #address-cells = <1>;
  77                 #size-cells = <1>;
  78                 ranges;
  79                 compatible = "simple-bus";
  80
  81                 intc: interrupt-controller@2000000 {
  82                         compatible = "qcom,msm-qgic2";
  83                         interrupt-controller;
  84                         #interrupt-cells = <3>;
  85                         reg = <0x02000000 0x1000>,
  86                               <0x02002000 0x1000>;
  87                 };
  88
  89                 timer@200a000 {
  90                         compatible = "qcom,kpss-timer",
  91                                      "qcom,kpss-wdt-msm8960", "qcom,msm-timer";
  92                         interrupts = <1 1 0x301>,
  93                                      <1 2 0x301>,
  94                                      <1 3 0x301>;
  95                         reg = <0x0200a000 0x100>;
  96                         clock-frequency = <27000000>,
  97                                           <32768>;
  98                         cpu-offset = <0x80000>;
  99                 };
 100
 101                 msmgpio: pinctrl@800000 {
 102                         compatible = "qcom,msm8960-pinctrl";
 103                         gpio-controller;
 104                         #gpio-cells = <2>;
 105                         interrupts = <0 16 0x4>;
 106                         interrupt-controller;
 107                         #interrupt-cells = <2>;
 108                         reg = <0x800000 0x4000>;
 109                 };
 110
 111                 gcc: clock-controller@900000 {
 112                         compatible = "qcom,gcc-msm8960";
 113                         #clock-cells = <1>;
 114                         #reset-cells = <1>;
 115                         reg = <0x900000 0x4000>;
 116                 };
 117
 118                 lcc: clock-controller@28000000 {
 119                         compatible = "qcom,lcc-msm8960";
 120                         reg = <0x28000000 0x1000>;
 121                         #clock-cells = <1>;
 122                         #reset-cells = <1>;
 123                 };
 124
 125                 clock-controller@4000000 {
 126                         compatible = "qcom,mmcc-msm8960";
 127                         reg = <0x4000000 0x1000>;
 128                         #clock-cells = <1>;
 129                         #reset-cells = <1>;
 130                 };
 131
 132                 l2cc: clock-controller@2011000 {
 133                         compatible      = "syscon";
 134                         reg             = <0x2011000 0x1000>;
 135                 };
 136
 137                 rpm@108000 {
 138                         compatible      = "qcom,rpm-msm8960";
 139                         reg             = <0x108000 0x1000>;
 140                         qcom,ipc        = <&l2cc 0x8 2>;
 141
 142                         interrupts      = <0 19 0>, <0 21 0>, <0 22 0>;
 143                         interrupt-names = "ack", "err", "wakeup";
 144
 145                         regulators {
 146                                 compatible = "qcom,rpm-pm8921-regulators";
 147                         };
 148                 };
 149
 150                 acc0: clock-controller@2088000 {
 151                         compatible = "qcom,kpss-acc-v1";
 152                         reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
 153                 };
 154
 155                 acc1: clock-controller@2098000 {
 156                         compatible = "qcom,kpss-acc-v1";
 157                         reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
 158                 };
 159
 160                 saw0: regulator@2089000 {
 161                         compatible = "qcom,saw2";
 162                         reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
 163                         regulator;
 164                 };
 165
 166                 saw1: regulator@2099000 {
 167                         compatible = "qcom,saw2";
 168                         reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
 169                         regulator;
 170                 };
 171
 172                 gsbi5: gsbi@16400000 {
 173                         compatible = "qcom,gsbi-v1.0.0";
 174                         cell-index = <5>;
 175                         reg = <0x16400000 0x100>;
 176                         clocks = <&gcc GSBI5_H_CLK>;
 177                         clock-names = "iface";
 178                         #address-cells = <1>;
 179                         #size-cells = <1>;
 180                         ranges;
 181
 182                         syscon-tcsr = <&tcsr>;
 183
 184                         gsbi5_serial: serial@16440000 {
 185                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 186                                 reg = <0x16440000 0x1000>,
 187                                       <0x16400000 0x1000>;
 188                                 interrupts = <0 154 0x0>;
 189                                 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
 190                                 clock-names = "core", "iface";
 191                                 status = "disabled";
 192                         };
 193                 };
 194
 195                 qcom,ssbi@500000 {
 196                         compatible = "qcom,ssbi";
 197                         reg = <0x500000 0x1000>;
 198                         qcom,controller-type = "pmic-arbiter";
 199
 200                         pmicintc: pmic@0 {
 201                                 compatible = "qcom,pm8921";
 202                                 interrupt-parent = <&msmgpio>;
 203                                 interrupts = <104 8>;
 204                                 #interrupt-cells = <2>;
 205                                 interrupt-controller;
 206                                 #address-cells = <1>;
 207                                 #size-cells = <0>;
 208
 209                                 pwrkey@1c {
 210                                         compatible = "qcom,pm8921-pwrkey";
 211                                         reg = <0x1c>;
 212                                         interrupt-parent = <&pmicintc>;
 213                                         interrupts = <50 1>, <51 1>;
 214                                         debounce = <15625>;
 215                                         pull-up;
 216                                 };
 217
 218                                 keypad@148 {
 219                                         compatible = "qcom,pm8921-keypad";
 220                                         reg = <0x148>;
 221                                         interrupt-parent = <&pmicintc>;
 222                                         interrupts = <74 1>, <75 1>;
 223                                         debounce = <15>;
 224                                         scan-delay = <32>;
 225                                         row-hold = <91500>;
 226                                 };
 227
 228                                 rtc@11d {
 229                                         compatible = "qcom,pm8921-rtc";
 230                                         interrupt-parent = <&pmicintc>;
 231                                         interrupts = <39 1>;
 232                                         reg = <0x11d>;
 233                                         allow-set-time;
 234                                 };
 235                         };
 236                 };
 237
 238                 rng@1a500000 {
 239                         compatible = "qcom,prng";
 240                         reg = <0x1a500000 0x200>;
 241                         clocks = <&gcc PRNG_CLK>;
 242                         clock-names = "core";
 243                 };
 244
 245                 /* Temporary fixed regulator */
 246                 vsdcc_fixed: vsdcc-regulator {
 247                         compatible = "regulator-fixed";
 248                         regulator-name = "SDCC Power";
 249                         regulator-min-microvolt = <2700000>;
 250                         regulator-max-microvolt = <2700000>;
 251                         regulator-always-on;
 252                 };
 253
 254                 amba {
 255                         compatible = "simple-bus";
 256                         #address-cells = <1>;
 257                         #size-cells = <1>;
 258                         ranges;
 259                         sdcc1: sdcc@12400000 {
 260                                 status          = "disabled";
 261                                 compatible      = "arm,pl18x", "arm,primecell";
 262                                 arm,primecell-periphid = <0x00051180>;
 263                                 reg             = <0x12400000 0x8000>;
 264                                 interrupts      = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 265                                 interrupt-names = "cmd_irq";
 266                                 clocks          = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
 267                                 clock-names     = "mclk", "apb_pclk";
 268                                 bus-width       = <8>;
 269                                 max-frequency   = <96000000>;
 270                                 non-removable;
 271                                 cap-sd-highspeed;
 272                                 cap-mmc-highspeed;
 273                                 vmmc-supply = <&vsdcc_fixed>;
 274                         };
 275
 276                         sdcc3: sdcc@12180000 {
 277                                 compatible      = "arm,pl18x", "arm,primecell";
 278                                 arm,primecell-periphid = <0x00051180>;
 279                                 status          = "disabled";
 280                                 reg             = <0x12180000 0x8000>;
 281                                 interrupts      = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 282                                 interrupt-names = "cmd_irq";
 283                                 clocks          = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
 284                                 clock-names     = "mclk", "apb_pclk";
 285                                 bus-width       = <4>;
 286                                 cap-sd-highspeed;
 287                                 cap-mmc-highspeed;
 288                                 max-frequency   = <192000000>;
 289                                 no-1-8-v;
 290                                 vmmc-supply = <&vsdcc_fixed>;
 291                         };
 292                 };
 293
 294                 tcsr: syscon@1a400000 {
 295                         compatible = "qcom,tcsr-msm8960", "syscon";
 296                         reg = <0x1a400000 0x100>;
 297                 };
 298
 299                 gsbi@16000000 {
 300                         compatible = "qcom,gsbi-v1.0.0";
 301                         cell-index = <1>;
 302                         reg = <0x16000000 0x100>;
 303                         clocks = <&gcc GSBI1_H_CLK>;
 304                         clock-names = "iface";
 305                         #address-cells = <1>;
 306                         #size-cells = <1>;
 307                         ranges;
 308
 309                         spi@16080000 {
 310                                 compatible = "qcom,spi-qup-v1.1.1";
 311                                 #address-cells = <1>;
 312                                 #size-cells = <0>;
 313                                 reg = <0x16080000 0x1000>;
 314                                 interrupts = <0 147 0>;
 315                                 spi-max-frequency = <24000000>;
 316                                 cs-gpios = <&msmgpio 8 0>;
 317
 318                                 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
 319                                 clock-names = "core", "iface";
 320                                 status = "disabled";
 321                         };
 322                 };
 323         };
 324 };