1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
5 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
6 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
7 #include <dt-bindings/clock/qcom,rpmcc.h>
8 #include <dt-bindings/soc/qcom,gsbi.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 model = "Qualcomm APQ8064";
15 compatible = "qcom,apq8064";
16 interrupt-parent = <&intc>;
23 smem_region: smem@80000000 {
24 reg = <0x80000000 0x200000>;
28 wcnss_mem: wcnss@8f000000 {
29 reg = <0x8f000000 0x700000>;
39 compatible = "qcom,krait";
40 enable-method = "qcom,kpss-acc-v1";
43 next-level-cache = <&L2>;
46 cpu-idle-states = <&CPU_SPC>;
50 compatible = "qcom,krait";
51 enable-method = "qcom,kpss-acc-v1";
54 next-level-cache = <&L2>;
57 cpu-idle-states = <&CPU_SPC>;
61 compatible = "qcom,krait";
62 enable-method = "qcom,kpss-acc-v1";
65 next-level-cache = <&L2>;
68 cpu-idle-states = <&CPU_SPC>;
72 compatible = "qcom,krait";
73 enable-method = "qcom,kpss-acc-v1";
76 next-level-cache = <&L2>;
79 cpu-idle-states = <&CPU_SPC>;
89 compatible = "qcom,idle-state-spc",
91 entry-latency-us = <400>;
92 exit-latency-us = <900>;
93 min-residency-us = <3000>;
99 device_type = "memory";
105 polling-delay-passive = <250>;
106 polling-delay = <1000>;
108 thermal-sensors = <&gcc 7>;
109 coefficients = <1199 0>;
113 temperature = <75000>;
118 temperature = <110000>;
126 polling-delay-passive = <250>;
127 polling-delay = <1000>;
129 thermal-sensors = <&gcc 8>;
130 coefficients = <1132 0>;
134 temperature = <75000>;
139 temperature = <110000>;
147 polling-delay-passive = <250>;
148 polling-delay = <1000>;
150 thermal-sensors = <&gcc 9>;
151 coefficients = <1199 0>;
155 temperature = <75000>;
160 temperature = <110000>;
168 polling-delay-passive = <250>;
169 polling-delay = <1000>;
171 thermal-sensors = <&gcc 10>;
172 coefficients = <1132 0>;
176 temperature = <75000>;
181 temperature = <110000>;
190 compatible = "qcom,krait-pmu";
191 interrupts = <1 10 0x304>;
195 cxo_board: cxo_board {
196 compatible = "fixed-clock";
198 clock-frequency = <19200000>;
202 compatible = "fixed-clock";
204 clock-frequency = <27000000>;
207 sleep_clk: sleep_clk {
208 compatible = "fixed-clock";
210 clock-frequency = <32768>;
214 sfpb_mutex: hwmutex {
215 compatible = "qcom,sfpb-mutex";
216 syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
221 compatible = "qcom,smem";
222 memory-region = <&smem_region>;
224 hwlocks = <&sfpb_mutex 3>;
228 compatible = "qcom,smd";
231 interrupts = <0 37 IRQ_TYPE_EDGE_RISING>;
233 qcom,ipc = <&l2cc 8 3>;
240 interrupts = <0 90 IRQ_TYPE_EDGE_RISING>;
242 qcom,ipc = <&l2cc 8 15>;
249 interrupts = <0 138 IRQ_TYPE_EDGE_RISING>;
251 qcom,ipc = <&sps_sic_non_secure 0x4080 0>;
258 interrupts = <0 198 IRQ_TYPE_EDGE_RISING>;
260 qcom,ipc = <&l2cc 8 25>;
268 compatible = "qcom,smsm";
270 #address-cells = <1>;
273 qcom,ipc-1 = <&l2cc 8 4>;
274 qcom,ipc-2 = <&l2cc 8 14>;
275 qcom,ipc-3 = <&l2cc 8 23>;
276 qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>;
280 #qcom,smem-state-cells = <1>;
283 modem_smsm: modem@1 {
285 interrupts = <0 38 IRQ_TYPE_EDGE_RISING>;
287 interrupt-controller;
288 #interrupt-cells = <2>;
293 interrupts = <0 89 IRQ_TYPE_EDGE_RISING>;
295 interrupt-controller;
296 #interrupt-cells = <2>;
299 wcnss_smsm: wcnss@3 {
301 interrupts = <0 204 IRQ_TYPE_EDGE_RISING>;
303 interrupt-controller;
304 #interrupt-cells = <2>;
309 interrupts = <0 137 IRQ_TYPE_EDGE_RISING>;
311 interrupt-controller;
312 #interrupt-cells = <2>;
318 compatible = "qcom,scm-apq8064";
320 clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>;
321 clock-names = "core";
327 * These channels from the ADC are simply hardware monitors.
328 * That is why the ADC is referred to as "HKADC" - HouseKeeping
332 compatible = "iio-hwmon";
333 io-channels = <&xoadc 0x00 0x01>, /* Battery */
334 <&xoadc 0x00 0x02>, /* DC in (charger) */
335 <&xoadc 0x00 0x04>, /* VPH the main system voltage */
336 <&xoadc 0x00 0x0b>, /* Die temperature */
337 <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */
338 <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */
339 <&xoadc 0x00 0x0e>; /* Charger temperature */
343 #address-cells = <1>;
346 compatible = "simple-bus";
348 tlmm_pinmux: pinctrl@800000 {
349 compatible = "qcom,apq8064-pinctrl";
350 reg = <0x800000 0x4000>;
354 interrupt-controller;
355 #interrupt-cells = <2>;
356 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
358 pinctrl-names = "default";
359 pinctrl-0 = <&ps_hold>;
362 sfpb_wrapper_mutex: syscon@1200000 {
363 compatible = "syscon";
364 reg = <0x01200000 0x8000>;
367 intc: interrupt-controller@2000000 {
368 compatible = "qcom,msm-qgic2";
369 interrupt-controller;
370 #interrupt-cells = <3>;
371 reg = <0x02000000 0x1000>,
376 compatible = "qcom,kpss-timer",
377 "qcom,kpss-wdt-apq8064", "qcom,msm-timer";
378 interrupts = <1 1 0x301>,
381 reg = <0x0200a000 0x100>;
382 clock-frequency = <27000000>,
384 cpu-offset = <0x80000>;
387 acc0: clock-controller@2088000 {
388 compatible = "qcom,kpss-acc-v1";
389 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
392 acc1: clock-controller@2098000 {
393 compatible = "qcom,kpss-acc-v1";
394 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
397 acc2: clock-controller@20a8000 {
398 compatible = "qcom,kpss-acc-v1";
399 reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
402 acc3: clock-controller@20b8000 {
403 compatible = "qcom,kpss-acc-v1";
404 reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
407 saw0: power-controller@2089000 {
408 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
409 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
413 saw1: power-controller@2099000 {
414 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
415 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
419 saw2: power-controller@20a9000 {
420 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
421 reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
425 saw3: power-controller@20b9000 {
426 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
427 reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
431 sps_sic_non_secure: sps-sic-non-secure@12100000 {
432 compatible = "syscon";
433 reg = <0x12100000 0x10000>;
436 gsbi1: gsbi@12440000 {
438 compatible = "qcom,gsbi-v1.0.0";
440 reg = <0x12440000 0x100>;
441 clocks = <&gcc GSBI1_H_CLK>;
442 clock-names = "iface";
443 #address-cells = <1>;
447 syscon-tcsr = <&tcsr>;
449 gsbi1_serial: serial@12450000 {
450 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
451 reg = <0x12450000 0x100>,
453 interrupts = <0 193 IRQ_TYPE_LEVEL_HIGH>;
454 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
455 clock-names = "core", "iface";
459 gsbi1_i2c: i2c@12460000 {
460 compatible = "qcom,i2c-qup-v1.1.1";
461 pinctrl-0 = <&i2c1_pins>;
462 pinctrl-1 = <&i2c1_pins_sleep>;
463 pinctrl-names = "default", "sleep";
464 reg = <0x12460000 0x1000>;
465 interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>;
466 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
467 clock-names = "core", "iface";
468 #address-cells = <1>;
475 gsbi2: gsbi@12480000 {
477 compatible = "qcom,gsbi-v1.0.0";
479 reg = <0x12480000 0x100>;
480 clocks = <&gcc GSBI2_H_CLK>;
481 clock-names = "iface";
482 #address-cells = <1>;
486 syscon-tcsr = <&tcsr>;
488 gsbi2_i2c: i2c@124a0000 {
489 compatible = "qcom,i2c-qup-v1.1.1";
490 reg = <0x124a0000 0x1000>;
491 pinctrl-0 = <&i2c2_pins>;
492 pinctrl-1 = <&i2c2_pins_sleep>;
493 pinctrl-names = "default", "sleep";
494 interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>;
495 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
496 clock-names = "core", "iface";
497 #address-cells = <1>;
503 gsbi3: gsbi@16200000 {
505 compatible = "qcom,gsbi-v1.0.0";
507 reg = <0x16200000 0x100>;
508 clocks = <&gcc GSBI3_H_CLK>;
509 clock-names = "iface";
510 #address-cells = <1>;
513 gsbi3_i2c: i2c@16280000 {
514 compatible = "qcom,i2c-qup-v1.1.1";
515 pinctrl-0 = <&i2c3_pins>;
516 pinctrl-1 = <&i2c3_pins_sleep>;
517 pinctrl-names = "default", "sleep";
518 reg = <0x16280000 0x1000>;
519 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
520 clocks = <&gcc GSBI3_QUP_CLK>,
522 clock-names = "core", "iface";
523 #address-cells = <1>;
529 gsbi4: gsbi@16300000 {
531 compatible = "qcom,gsbi-v1.0.0";
533 reg = <0x16300000 0x03>;
534 clocks = <&gcc GSBI4_H_CLK>;
535 clock-names = "iface";
536 #address-cells = <1>;
540 gsbi4_i2c: i2c@16380000 {
541 compatible = "qcom,i2c-qup-v1.1.1";
542 pinctrl-0 = <&i2c4_pins>;
543 pinctrl-1 = <&i2c4_pins_sleep>;
544 pinctrl-names = "default", "sleep";
545 reg = <0x16380000 0x1000>;
546 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
547 clocks = <&gcc GSBI4_QUP_CLK>,
549 clock-names = "core", "iface";
554 gsbi5: gsbi@1a200000 {
556 compatible = "qcom,gsbi-v1.0.0";
558 reg = <0x1a200000 0x03>;
559 clocks = <&gcc GSBI5_H_CLK>;
560 clock-names = "iface";
561 #address-cells = <1>;
565 gsbi5_serial: serial@1a240000 {
566 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
567 reg = <0x1a240000 0x100>,
569 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
570 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
571 clock-names = "core", "iface";
575 gsbi5_spi: spi@1a280000 {
576 compatible = "qcom,spi-qup-v1.1.1";
577 reg = <0x1a280000 0x1000>;
578 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
579 pinctrl-0 = <&spi5_default>;
580 pinctrl-1 = <&spi5_sleep>;
581 pinctrl-names = "default", "sleep";
582 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
583 clock-names = "core", "iface";
585 #address-cells = <1>;
590 gsbi6: gsbi@16500000 {
592 compatible = "qcom,gsbi-v1.0.0";
594 reg = <0x16500000 0x03>;
595 clocks = <&gcc GSBI6_H_CLK>;
596 clock-names = "iface";
597 #address-cells = <1>;
601 gsbi6_serial: serial@16540000 {
602 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
603 reg = <0x16540000 0x100>,
605 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
606 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
607 clock-names = "core", "iface";
611 gsbi6_i2c: i2c@16580000 {
612 compatible = "qcom,i2c-qup-v1.1.1";
613 pinctrl-0 = <&i2c6_pins>;
614 pinctrl-1 = <&i2c6_pins_sleep>;
615 pinctrl-names = "default", "sleep";
616 reg = <0x16580000 0x1000>;
617 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
618 clocks = <&gcc GSBI6_QUP_CLK>,
620 clock-names = "core", "iface";
625 gsbi7: gsbi@16600000 {
627 compatible = "qcom,gsbi-v1.0.0";
629 reg = <0x16600000 0x100>;
630 clocks = <&gcc GSBI7_H_CLK>;
631 clock-names = "iface";
632 #address-cells = <1>;
635 syscon-tcsr = <&tcsr>;
637 gsbi7_serial: serial@16640000 {
638 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
639 reg = <0x16640000 0x1000>,
641 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
642 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
643 clock-names = "core", "iface";
647 gsbi7_i2c: i2c@16680000 {
648 compatible = "qcom,i2c-qup-v1.1.1";
649 pinctrl-0 = <&i2c7_pins>;
650 pinctrl-1 = <&i2c7_pins_sleep>;
651 pinctrl-names = "default", "sleep";
652 reg = <0x16680000 0x1000>;
653 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
654 clocks = <&gcc GSBI7_QUP_CLK>,
656 clock-names = "core", "iface";
662 compatible = "qcom,prng";
663 reg = <0x1a500000 0x200>;
664 clocks = <&gcc PRNG_CLK>;
665 clock-names = "core";
669 compatible = "qcom,ssbi";
670 reg = <0x00c00000 0x1000>;
671 qcom,controller-type = "pmic-arbiter";
674 compatible = "qcom,pm8821";
675 interrupt-parent = <&tlmm_pinmux>;
676 interrupts = <76 IRQ_TYPE_LEVEL_LOW>;
677 #interrupt-cells = <2>;
678 interrupt-controller;
679 #address-cells = <1>;
682 pm8821_mpps: mpps@50 {
683 compatible = "qcom,pm8821-mpp", "qcom,ssbi-mpp";
685 interrupts = <24 IRQ_TYPE_NONE>,
696 compatible = "qcom,ssbi";
697 reg = <0x00500000 0x1000>;
698 qcom,controller-type = "pmic-arbiter";
701 compatible = "qcom,pm8921";
702 interrupt-parent = <&tlmm_pinmux>;
704 #interrupt-cells = <2>;
705 interrupt-controller;
706 #address-cells = <1>;
709 pm8921_gpio: gpio@150 {
711 compatible = "qcom,pm8921-gpio",
714 interrupts = <192 IRQ_TYPE_NONE>,
763 pm8921_mpps: mpps@50 {
764 compatible = "qcom,pm8921-mpp",
785 compatible = "qcom,pm8921-rtc";
786 interrupt-parent = <&pmicintc>;
793 compatible = "qcom,pm8921-pwrkey";
795 interrupt-parent = <&pmicintc>;
796 interrupts = <50 1>, <51 1>;
802 compatible = "qcom,pm8921-adc";
804 interrupts-extended = <&pmicintc 78 IRQ_TYPE_EDGE_RISING>;
805 #address-cells = <2>;
807 #io-channel-cells = <2>;
809 vcoin: adc-channel@00 {
812 vbat: adc-channel@01 {
815 dcin: adc-channel@02 {
818 vph_pwr: adc-channel@04 {
821 batt_therm: adc-channel@08 {
824 batt_id: adc-channel@09 {
827 usb_vbus: adc-channel@0a {
830 die_temp: adc-channel@0b {
833 ref_625mv: adc-channel@0c {
836 ref_1250mv: adc-channel@0d {
839 chg_temp: adc-channel@0e {
842 ref_muxoff: adc-channel@0f {
849 qfprom: qfprom@700000 {
850 compatible = "qcom,qfprom";
851 reg = <0x00700000 0x1000>;
852 #address-cells = <1>;
858 tsens_backup: backup_calib {
863 gcc: clock-controller@900000 {
864 compatible = "qcom,gcc-apq8064";
865 reg = <0x00900000 0x4000>;
866 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
867 nvmem-cell-names = "calib", "calib_backup";
870 #thermal-sensor-cells = <1>;
873 lcc: clock-controller@28000000 {
874 compatible = "qcom,lcc-apq8064";
875 reg = <0x28000000 0x1000>;
880 mmcc: clock-controller@4000000 {
881 compatible = "qcom,mmcc-apq8064";
882 reg = <0x4000000 0x1000>;
887 l2cc: clock-controller@2011000 {
888 compatible = "syscon";
889 reg = <0x2011000 0x1000>;
893 compatible = "qcom,rpm-apq8064";
894 reg = <0x108000 0x1000>;
895 qcom,ipc = <&l2cc 0x8 2>;
897 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
898 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
899 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
900 interrupt-names = "ack", "err", "wakeup";
902 rpmcc: clock-controller {
903 compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc";
908 compatible = "qcom,rpm-pm8921-regulators";
944 pm8921_lvs1: lvs1 {};
945 pm8921_lvs2: lvs2 {};
946 pm8921_lvs3: lvs3 {};
947 pm8921_lvs4: lvs4 {};
948 pm8921_lvs5: lvs5 {};
949 pm8921_lvs6: lvs6 {};
950 pm8921_lvs7: lvs7 {};
952 pm8921_usb_switch: usb-switch {};
954 pm8921_hdmi_switch: hdmi-switch {
963 compatible = "qcom,ci-hdrc";
964 reg = <0x12500000 0x200>,
966 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
967 clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>;
968 clock-names = "core", "iface";
969 assigned-clocks = <&gcc USB_HS1_XCVR_CLK>;
970 assigned-clock-rates = <60000000>;
971 resets = <&gcc USB_HS1_RESET>;
972 reset-names = "core";
974 ahb-burst-config = <0>;
975 phys = <&usb_hs1_phy>;
976 phy-names = "usb-phy";
982 compatible = "qcom,usb-hs-phy-apq8064",
984 clocks = <&sleep_clk>, <&cxo_board>;
985 clock-names = "sleep", "ref";
994 compatible = "qcom,ci-hdrc";
995 reg = <0x12520000 0x200>,
997 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
998 clocks = <&gcc USB_HS3_XCVR_CLK>, <&gcc USB_HS3_H_CLK>;
999 clock-names = "core", "iface";
1000 assigned-clocks = <&gcc USB_HS3_XCVR_CLK>;
1001 assigned-clock-rates = <60000000>;
1002 resets = <&gcc USB_HS3_RESET>;
1003 reset-names = "core";
1005 ahb-burst-config = <0>;
1006 phys = <&usb_hs3_phy>;
1007 phy-names = "usb-phy";
1008 status = "disabled";
1013 compatible = "qcom,usb-hs-phy-apq8064",
1016 clocks = <&sleep_clk>, <&cxo_board>;
1017 clock-names = "sleep", "ref";
1019 reset-names = "por";
1024 usb4: usb@12530000 {
1025 compatible = "qcom,ci-hdrc";
1026 reg = <0x12530000 0x200>,
1028 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
1029 clocks = <&gcc USB_HS4_XCVR_CLK>, <&gcc USB_HS4_H_CLK>;
1030 clock-names = "core", "iface";
1031 assigned-clocks = <&gcc USB_HS4_XCVR_CLK>;
1032 assigned-clock-rates = <60000000>;
1033 resets = <&gcc USB_HS4_RESET>;
1034 reset-names = "core";
1036 ahb-burst-config = <0>;
1037 phys = <&usb_hs4_phy>;
1038 phy-names = "usb-phy";
1039 status = "disabled";
1044 compatible = "qcom,usb-hs-phy-apq8064",
1047 clocks = <&sleep_clk>, <&cxo_board>;
1048 clock-names = "sleep", "ref";
1050 reset-names = "por";
1055 sata_phy0: phy@1b400000 {
1056 compatible = "qcom,apq8064-sata-phy";
1057 status = "disabled";
1058 reg = <0x1b400000 0x200>;
1059 reg-names = "phy_mem";
1060 clocks = <&gcc SATA_PHY_CFG_CLK>;
1061 clock-names = "cfg";
1065 sata0: sata@29000000 {
1066 compatible = "qcom,apq8064-ahci", "generic-ahci";
1067 status = "disabled";
1068 reg = <0x29000000 0x180>;
1069 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
1071 clocks = <&gcc SFAB_SATA_S_H_CLK>,
1074 <&gcc SATA_RXOOB_CLK>,
1075 <&gcc SATA_PMALIVE_CLK>;
1076 clock-names = "slave_iface",
1082 assigned-clocks = <&gcc SATA_RXOOB_CLK>,
1083 <&gcc SATA_PMALIVE_CLK>;
1084 assigned-clock-rates = <100000000>, <100000000>;
1086 phys = <&sata_phy0>;
1087 phy-names = "sata-phy";
1088 ports-implemented = <0x1>;
1091 /* Temporary fixed regulator */
1092 sdcc1bam:dma@12402000{
1093 compatible = "qcom,bam-v1.3.0";
1094 reg = <0x12402000 0x8000>;
1095 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
1096 clocks = <&gcc SDC1_H_CLK>;
1097 clock-names = "bam_clk";
1102 sdcc3bam:dma@12182000{
1103 compatible = "qcom,bam-v1.3.0";
1104 reg = <0x12182000 0x8000>;
1105 interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
1106 clocks = <&gcc SDC3_H_CLK>;
1107 clock-names = "bam_clk";
1112 sdcc4bam:dma@121c2000{
1113 compatible = "qcom,bam-v1.3.0";
1114 reg = <0x121c2000 0x8000>;
1115 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
1116 clocks = <&gcc SDC4_H_CLK>;
1117 clock-names = "bam_clk";
1123 compatible = "simple-bus";
1124 #address-cells = <1>;
1127 sdcc1: sdcc@12400000 {
1128 status = "disabled";
1129 compatible = "arm,pl18x", "arm,primecell";
1130 pinctrl-names = "default";
1131 pinctrl-0 = <&sdcc1_pins>;
1132 arm,primecell-periphid = <0x00051180>;
1133 reg = <0x12400000 0x2000>;
1134 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1135 interrupt-names = "cmd_irq";
1136 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1137 clock-names = "mclk", "apb_pclk";
1139 max-frequency = <96000000>;
1143 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1144 dma-names = "tx", "rx";
1147 sdcc3: sdcc@12180000 {
1148 compatible = "arm,pl18x", "arm,primecell";
1149 arm,primecell-periphid = <0x00051180>;
1150 status = "disabled";
1151 reg = <0x12180000 0x2000>;
1152 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1153 interrupt-names = "cmd_irq";
1154 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1155 clock-names = "mclk", "apb_pclk";
1159 max-frequency = <192000000>;
1161 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1162 dma-names = "tx", "rx";
1165 sdcc4: sdcc@121c0000 {
1166 compatible = "arm,pl18x", "arm,primecell";
1167 arm,primecell-periphid = <0x00051180>;
1168 status = "disabled";
1169 reg = <0x121c0000 0x2000>;
1170 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1171 interrupt-names = "cmd_irq";
1172 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
1173 clock-names = "mclk", "apb_pclk";
1177 max-frequency = <48000000>;
1178 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
1179 dma-names = "tx", "rx";
1180 pinctrl-names = "default";
1181 pinctrl-0 = <&sdc4_gpios>;
1185 tcsr: syscon@1a400000 {
1186 compatible = "qcom,tcsr-apq8064", "syscon";
1187 reg = <0x1a400000 0x100>;
1190 gpu: adreno-3xx@4300000 {
1191 compatible = "qcom,adreno-3xx";
1192 reg = <0x04300000 0x20000>;
1193 reg-names = "kgsl_3d0_reg_memory";
1194 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1195 interrupt-names = "kgsl_3d0_irq";
1203 <&mmcc GFX3D_AHB_CLK>,
1204 <&mmcc GFX3D_AXI_CLK>,
1205 <&mmcc MMSS_IMEM_AHB_CLK>;
1206 qcom,chipid = <0x03020002>;
1273 qcom,gpu-pwrlevels {
1274 compatible = "qcom,gpu-pwrlevels";
1275 qcom,gpu-pwrlevel@0 {
1276 qcom,gpu-freq = <450000000>;
1278 qcom,gpu-pwrlevel@1 {
1279 qcom,gpu-freq = <27000000>;
1284 mmss_sfpb: syscon@5700000 {
1285 compatible = "syscon";
1286 reg = <0x5700000 0x70>;
1289 dsi0: mdss_dsi@4700000 {
1290 compatible = "qcom,mdss-dsi-ctrl";
1291 label = "MDSS DSI CTRL->0";
1292 #address-cells = <1>;
1294 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1295 reg = <0x04700000 0x200>;
1296 reg-names = "dsi_ctrl";
1298 clocks = <&mmcc DSI_M_AHB_CLK>,
1299 <&mmcc DSI_S_AHB_CLK>,
1300 <&mmcc AMP_AHB_CLK>,
1302 <&mmcc DSI1_BYTE_CLK>,
1303 <&mmcc DSI_PIXEL_CLK>,
1304 <&mmcc DSI1_ESC_CLK>;
1305 clock-names = "iface_clk", "bus_clk", "core_mmss_clk",
1306 "src_clk", "byte_clk", "pixel_clk",
1309 assigned-clocks = <&mmcc DSI1_BYTE_SRC>,
1310 <&mmcc DSI1_ESC_SRC>,
1312 <&mmcc DSI_PIXEL_SRC>;
1313 assigned-clock-parents = <&dsi0_phy 0>,
1317 syscon-sfpb = <&mmss_sfpb>;
1320 #address-cells = <1>;
1331 dsi0_out: endpoint {
1338 dsi0_phy: dsi-phy@4700200 {
1339 compatible = "qcom,dsi-phy-28nm-8960";
1343 reg = <0x04700200 0x100>,
1346 reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator";
1347 clock-names = "iface_clk";
1348 clocks = <&mmcc DSI_M_AHB_CLK>;
1352 mdp_port0: iommu@7500000 {
1353 compatible = "qcom,apq8064-iommu";
1359 <&mmcc SMMU_AHB_CLK>,
1360 <&mmcc MDP_AXI_CLK>;
1361 reg = <0x07500000 0x100000>;
1363 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
1364 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
1368 mdp_port1: iommu@7600000 {
1369 compatible = "qcom,apq8064-iommu";
1375 <&mmcc SMMU_AHB_CLK>,
1376 <&mmcc MDP_AXI_CLK>;
1377 reg = <0x07600000 0x100000>;
1379 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
1380 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1384 gfx3d: iommu@7c00000 {
1385 compatible = "qcom,apq8064-iommu";
1391 <&mmcc SMMU_AHB_CLK>,
1392 <&mmcc GFX3D_AXI_CLK>;
1393 reg = <0x07c00000 0x100000>;
1395 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1396 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1400 gfx3d1: iommu@7d00000 {
1401 compatible = "qcom,apq8064-iommu";
1407 <&mmcc SMMU_AHB_CLK>,
1408 <&mmcc GFX3D_AXI_CLK>;
1409 reg = <0x07d00000 0x100000>;
1411 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
1412 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
1416 pcie: pci@1b500000 {
1417 compatible = "qcom,pcie-apq8064", "snps,dw-pcie";
1418 reg = <0x1b500000 0x1000
1421 0x0ff00000 0x100000>;
1422 reg-names = "dbi", "elbi", "parf", "config";
1423 device_type = "pci";
1424 linux,pci-domain = <0>;
1425 bus-range = <0x00 0xff>;
1427 #address-cells = <3>;
1429 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */
1430 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* memory */
1431 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1432 interrupt-names = "msi";
1433 #interrupt-cells = <1>;
1434 interrupt-map-mask = <0 0 0 0x7>;
1435 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1436 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1437 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1438 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1439 clocks = <&gcc PCIE_A_CLK>,
1441 <&gcc PCIE_PHY_REF_CLK>;
1442 clock-names = "core", "iface", "phy";
1443 resets = <&gcc PCIE_ACLK_RESET>,
1444 <&gcc PCIE_HCLK_RESET>,
1445 <&gcc PCIE_POR_RESET>,
1446 <&gcc PCIE_PCI_RESET>,
1447 <&gcc PCIE_PHY_RESET>;
1448 reset-names = "axi", "ahb", "por", "pci", "phy";
1449 status = "disabled";
1452 hdmi: hdmi-tx@4a00000 {
1453 compatible = "qcom,hdmi-tx-8960";
1454 pinctrl-names = "default";
1455 pinctrl-0 = <&hdmi_pinctrl>;
1456 reg = <0x04a00000 0x2f0>;
1457 reg-names = "core_physical";
1458 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1459 clocks = <&mmcc HDMI_APP_CLK>,
1460 <&mmcc HDMI_M_AHB_CLK>,
1461 <&mmcc HDMI_S_AHB_CLK>;
1462 clock-names = "core_clk",
1467 phy-names = "hdmi-phy";
1470 #address-cells = <1>;
1481 hdmi_out: endpoint {
1487 hdmi_phy: hdmi-phy@4a00400 {
1488 compatible = "qcom,hdmi-phy-8960";
1489 reg = <0x4a00400 0x60>,
1491 reg-names = "hdmi_phy",
1494 clocks = <&mmcc HDMI_S_AHB_CLK>;
1495 clock-names = "slave_iface_clk";
1500 compatible = "qcom,mdp4";
1501 reg = <0x05100000 0xf0000>;
1502 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1503 clocks = <&mmcc MDP_CLK>,
1504 <&mmcc MDP_AHB_CLK>,
1505 <&mmcc MDP_AXI_CLK>,
1506 <&mmcc MDP_LUT_CLK>,
1507 <&mmcc HDMI_TV_CLK>,
1509 clock-names = "core_clk",
1516 iommus = <&mdp_port0 0
1522 #address-cells = <1>;
1527 mdp_lvds_out: endpoint {
1533 mdp_dsi1_out: endpoint {
1539 mdp_dsi2_out: endpoint {
1545 mdp_dtv_out: endpoint {
1551 riva: riva-pil@3204000 {
1552 compatible = "qcom,riva-pil";
1554 reg = <0x03200800 0x1000>, <0x03202000 0x2000>, <0x03204000 0x100>;
1555 reg-names = "ccu", "dxe", "pmu";
1557 interrupts-extended = <&intc GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
1558 <&wcnss_smsm 6 IRQ_TYPE_EDGE_RISING>;
1559 interrupt-names = "wdog", "fatal";
1561 memory-region = <&wcnss_mem>;
1563 vddcx-supply = <&pm8921_s3>;
1564 vddmx-supply = <&pm8921_l24>;
1565 vddpx-supply = <&pm8921_s4>;
1567 status = "disabled";
1570 compatible = "qcom,wcn3660";
1572 clocks = <&cxo_board>;
1575 vddxo-supply = <&pm8921_l4>;
1576 vddrfa-supply = <&pm8921_s2>;
1577 vddpa-supply = <&pm8921_l10>;
1578 vdddig-supply = <&pm8921_lvs2>;
1582 interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>;
1584 qcom,ipc = <&l2cc 8 25>;
1585 qcom,smd-edge = <6>;
1590 compatible = "qcom,wcnss";
1591 qcom,smd-channels = "WCNSS_CTRL";
1593 qcom,mmio = <&riva>;
1596 compatible = "qcom,wcnss-bt";
1600 compatible = "qcom,wcnss-wlan";
1602 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
1603 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
1604 interrupt-names = "tx", "rx";
1606 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1607 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
1614 compatible = "coresight-etb10", "arm,primecell";
1615 reg = <0x1a01000 0x1000>;
1617 clocks = <&rpmcc RPM_QDSS_CLK>;
1618 clock-names = "apb_pclk";
1623 remote-endpoint = <&replicator_out0>;
1630 compatible = "arm,coresight-tpiu", "arm,primecell";
1631 reg = <0x1a03000 0x1000>;
1633 clocks = <&rpmcc RPM_QDSS_CLK>;
1634 clock-names = "apb_pclk";
1639 remote-endpoint = <&replicator_out1>;
1646 compatible = "arm,coresight-replicator";
1648 clocks = <&rpmcc RPM_QDSS_CLK>;
1649 clock-names = "apb_pclk";
1652 #address-cells = <1>;
1657 replicator_out0: endpoint {
1658 remote-endpoint = <&etb_in>;
1663 replicator_out1: endpoint {
1664 remote-endpoint = <&tpiu_in>;
1671 replicator_in: endpoint {
1672 remote-endpoint = <&funnel_out>;
1679 compatible = "arm,coresight-funnel", "arm,primecell";
1680 reg = <0x1a04000 0x1000>;
1682 clocks = <&rpmcc RPM_QDSS_CLK>;
1683 clock-names = "apb_pclk";
1686 #address-cells = <1>;
1690 * Not described input ports:
1691 * 2 - connected to STM component
1698 funnel_in0: endpoint {
1699 remote-endpoint = <&etm0_out>;
1704 funnel_in1: endpoint {
1705 remote-endpoint = <&etm1_out>;
1710 funnel_in4: endpoint {
1711 remote-endpoint = <&etm2_out>;
1716 funnel_in5: endpoint {
1717 remote-endpoint = <&etm3_out>;
1724 funnel_out: endpoint {
1725 remote-endpoint = <&replicator_in>;
1732 compatible = "arm,coresight-etm3x", "arm,primecell";
1733 reg = <0x1a1c000 0x1000>;
1735 clocks = <&rpmcc RPM_QDSS_CLK>;
1736 clock-names = "apb_pclk";
1742 etm0_out: endpoint {
1743 remote-endpoint = <&funnel_in0>;
1750 compatible = "arm,coresight-etm3x", "arm,primecell";
1751 reg = <0x1a1d000 0x1000>;
1753 clocks = <&rpmcc RPM_QDSS_CLK>;
1754 clock-names = "apb_pclk";
1760 etm1_out: endpoint {
1761 remote-endpoint = <&funnel_in1>;
1768 compatible = "arm,coresight-etm3x", "arm,primecell";
1769 reg = <0x1a1e000 0x1000>;
1771 clocks = <&rpmcc RPM_QDSS_CLK>;
1772 clock-names = "apb_pclk";
1778 etm2_out: endpoint {
1779 remote-endpoint = <&funnel_in4>;
1786 compatible = "arm,coresight-etm3x", "arm,primecell";
1787 reg = <0x1a1f000 0x1000>;
1789 clocks = <&rpmcc RPM_QDSS_CLK>;
1790 clock-names = "apb_pclk";
1796 etm3_out: endpoint {
1797 remote-endpoint = <&funnel_in5>;
1804 #include "qcom-apq8064-pins.dtsi"