arch/arm/boot/dts/omap5.dtsi

   1 /*
   2  * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  * Based on "omap4.dtsi"
   8  */
   9
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 #include <dt-bindings/pinctrl/omap.h>
  13
  14 #include "skeleton.dtsi"
  15
  16 / {
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         compatible = "ti,omap5";
  21         interrupt-parent = <&gic>;
  22
  23         aliases {
  24                 i2c0 = &i2c1;
  25                 i2c1 = &i2c2;
  26                 i2c2 = &i2c3;
  27                 i2c3 = &i2c4;
  28                 i2c4 = &i2c5;
  29                 serial0 = &uart1;
  30                 serial1 = &uart2;
  31                 serial2 = &uart3;
  32                 serial3 = &uart4;
  33                 serial4 = &uart5;
  34                 serial5 = &uart6;
  35         };
  36
  37         cpus {
  38                 #address-cells = <1>;
  39                 #size-cells = <0>;
  40
  41                 cpu0: cpu@0 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a15";
  44                         reg = <0x0>;
  45
  46                         operating-points = <
  47                                 /* kHz    uV */
  48                                 1000000 1060000
  49                                 1500000 1250000
  50                         >;
  51
  52                         clocks = <&dpll_mpu_ck>;
  53                         clock-names = "cpu";
  54
  55                         clock-latency = <300000>; /* From omap-cpufreq driver */
  56
  57                         /* cooling options */
  58                         cooling-min-level = <0>;
  59                         cooling-max-level = <2>;
  60                         #cooling-cells = <2>; /* min followed by max */
  61                 };
  62                 cpu@1 {
  63                         device_type = "cpu";
  64                         compatible = "arm,cortex-a15";
  65                         reg = <0x1>;
  66                 };
  67         };
  68
  69         thermal-zones {
  70                 #include "omap4-cpu-thermal.dtsi"
  71                 #include "omap5-gpu-thermal.dtsi"
  72                 #include "omap5-core-thermal.dtsi"
  73         };
  74
  75         timer {
  76                 compatible = "arm,armv7-timer";
  77                 /* PPI secure/nonsecure IRQ */
  78                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  79                              <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  80                              <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  81                              <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
  82         };
  83
  84         pmu {
  85                 compatible = "arm,cortex-a15-pmu";
  86                 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
  87                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
  88         };
  89
  90         gic: interrupt-controller@48211000 {
  91                 compatible = "arm,cortex-a15-gic";
  92                 interrupt-controller;
  93                 #interrupt-cells = <3>;
  94                 reg = <0x48211000 0x1000>,
  95                       <0x48212000 0x1000>,
  96                       <0x48214000 0x2000>,
  97                       <0x48216000 0x2000>;
  98         };
  99
 100         /*
 101          * The soc node represents the soc top level view. It is used for IPs
 102          * that are not memory mapped in the MPU view or for the MPU itself.
 103          */
 104         soc {
 105                 compatible = "ti,omap-infra";
 106                 mpu {
 107                         compatible = "ti,omap5-mpu";
 108                         ti,hwmods = "mpu";
 109                 };
 110         };
 111
 112         /*
 113          * XXX: Use a flat representation of the OMAP3 interconnect.
 114          * The real OMAP interconnect network is quite complex.
 115          * Since it will not bring real advantage to represent that in DT for
 116          * the moment, just use a fake OCP bus entry to represent the whole bus
 117          * hierarchy.
 118          */
 119         ocp {
 120                 compatible = "ti,omap4-l3-noc", "simple-bus";
 121                 #address-cells = <1>;
 122                 #size-cells = <1>;
 123                 ranges;
 124                 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
 125                 reg = <0x44000000 0x2000>,
 126                       <0x44800000 0x3000>,
 127                       <0x45000000 0x4000>;
 128                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 129                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 130
 131                 prm: prm@4ae06000 {
 132                         compatible = "ti,omap5-prm";
 133                         reg = <0x4ae06000 0x3000>;
 134
 135                         prm_clocks: clocks {
 136                                 #address-cells = <1>;
 137                                 #size-cells = <0>;
 138                         };
 139
 140                         prm_clockdomains: clockdomains {
 141                         };
 142                 };
 143
 144                 cm_core_aon: cm_core_aon@4a004000 {
 145                         compatible = "ti,omap5-cm-core-aon";
 146                         reg = <0x4a004000 0x2000>;
 147
 148                         cm_core_aon_clocks: clocks {
 149                                 #address-cells = <1>;
 150                                 #size-cells = <0>;
 151                         };
 152
 153                         cm_core_aon_clockdomains: clockdomains {
 154                         };
 155                 };
 156
 157                 scrm: scrm@4ae0a000 {
 158                         compatible = "ti,omap5-scrm";
 159                         reg = <0x4ae0a000 0x2000>;
 160
 161                         scrm_clocks: clocks {
 162                                 #address-cells = <1>;
 163                                 #size-cells = <0>;
 164                         };
 165
 166                         scrm_clockdomains: clockdomains {
 167                         };
 168                 };
 169
 170                 cm_core: cm_core@4a008000 {
 171                         compatible = "ti,omap5-cm-core";
 172                         reg = <0x4a008000 0x3000>;
 173
 174                         cm_core_clocks: clocks {
 175                                 #address-cells = <1>;
 176                                 #size-cells = <0>;
 177                         };
 178
 179                         cm_core_clockdomains: clockdomains {
 180                         };
 181                 };
 182
 183                 counter32k: counter@4ae04000 {
 184                         compatible = "ti,omap-counter32k";
 185                         reg = <0x4ae04000 0x40>;
 186                         ti,hwmods = "counter_32k";
 187                 };
 188
 189                 omap5_pmx_core: pinmux@4a002840 {
 190                         compatible = "ti,omap4-padconf", "pinctrl-single";
 191                         reg = <0x4a002840 0x01b6>;
 192                         #address-cells = <1>;
 193                         #size-cells = <0>;
 194                         pinctrl-single,register-width = <16>;
 195                         pinctrl-single,function-mask = <0x7fff>;
 196                 };
 197                 omap5_pmx_wkup: pinmux@4ae0c840 {
 198                         compatible = "ti,omap4-padconf", "pinctrl-single";
 199                         reg = <0x4ae0c840 0x0038>;
 200                         #address-cells = <1>;
 201                         #size-cells = <0>;
 202                         pinctrl-single,register-width = <16>;
 203                         pinctrl-single,function-mask = <0x7fff>;
 204                 };
 205
 206                 omap5_padconf_global: tisyscon@4a002da0 {
 207                         compatible = "syscon";
 208                         reg = <0x4A002da0 0xec>;
 209                 };
 210
 211                 pbias_regulator: pbias_regulator {
 212                         compatible = "ti,pbias-omap";
 213                         reg = <0x60 0x4>;
 214                         syscon = <&omap5_padconf_global>;
 215                         pbias_mmc_reg: pbias_mmc_omap5 {
 216                                 regulator-name = "pbias_mmc_omap5";
 217                                 regulator-min-microvolt = <1800000>;
 218                                 regulator-max-microvolt = <3000000>;
 219                         };
 220                 };
 221
 222                 sdma: dma-controller@4a056000 {
 223                         compatible = "ti,omap4430-sdma";
 224                         reg = <0x4a056000 0x1000>;
 225                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 226                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 227                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 228                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 229                         #dma-cells = <1>;
 230                         #dma-channels = <32>;
 231                         #dma-requests = <127>;
 232                 };
 233
 234                 gpio1: gpio@4ae10000 {
 235                         compatible = "ti,omap4-gpio";
 236                         reg = <0x4ae10000 0x200>;
 237                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 238                         ti,hwmods = "gpio1";
 239                         ti,gpio-always-on;
 240                         gpio-controller;
 241                         #gpio-cells = <2>;
 242                         interrupt-controller;
 243                         #interrupt-cells = <2>;
 244                 };
 245
 246                 gpio2: gpio@48055000 {
 247                         compatible = "ti,omap4-gpio";
 248                         reg = <0x48055000 0x200>;
 249                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 250                         ti,hwmods = "gpio2";
 251                         gpio-controller;
 252                         #gpio-cells = <2>;
 253                         interrupt-controller;
 254                         #interrupt-cells = <2>;
 255                 };
 256
 257                 gpio3: gpio@48057000 {
 258                         compatible = "ti,omap4-gpio";
 259                         reg = <0x48057000 0x200>;
 260                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 261                         ti,hwmods = "gpio3";
 262                         gpio-controller;
 263                         #gpio-cells = <2>;
 264                         interrupt-controller;
 265                         #interrupt-cells = <2>;
 266                 };
 267
 268                 gpio4: gpio@48059000 {
 269                         compatible = "ti,omap4-gpio";
 270                         reg = <0x48059000 0x200>;
 271                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 272                         ti,hwmods = "gpio4";
 273                         gpio-controller;
 274                         #gpio-cells = <2>;
 275                         interrupt-controller;
 276                         #interrupt-cells = <2>;
 277                 };
 278
 279                 gpio5: gpio@4805b000 {
 280                         compatible = "ti,omap4-gpio";
 281                         reg = <0x4805b000 0x200>;
 282                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 283                         ti,hwmods = "gpio5";
 284                         gpio-controller;
 285                         #gpio-cells = <2>;
 286                         interrupt-controller;
 287                         #interrupt-cells = <2>;
 288                 };
 289
 290                 gpio6: gpio@4805d000 {
 291                         compatible = "ti,omap4-gpio";
 292                         reg = <0x4805d000 0x200>;
 293                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 294                         ti,hwmods = "gpio6";
 295                         gpio-controller;
 296                         #gpio-cells = <2>;
 297                         interrupt-controller;
 298                         #interrupt-cells = <2>;
 299                 };
 300
 301                 gpio7: gpio@48051000 {
 302                         compatible = "ti,omap4-gpio";
 303                         reg = <0x48051000 0x200>;
 304                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 305                         ti,hwmods = "gpio7";
 306                         gpio-controller;
 307                         #gpio-cells = <2>;
 308                         interrupt-controller;
 309                         #interrupt-cells = <2>;
 310                 };
 311
 312                 gpio8: gpio@48053000 {
 313                         compatible = "ti,omap4-gpio";
 314                         reg = <0x48053000 0x200>;
 315                         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 316                         ti,hwmods = "gpio8";
 317                         gpio-controller;
 318                         #gpio-cells = <2>;
 319                         interrupt-controller;
 320                         #interrupt-cells = <2>;
 321                 };
 322
 323                 gpmc: gpmc@50000000 {
 324                         compatible = "ti,omap4430-gpmc";
 325                         reg = <0x50000000 0x1000>;
 326                         #address-cells = <2>;
 327                         #size-cells = <1>;
 328                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 329                         gpmc,num-cs = <8>;
 330                         gpmc,num-waitpins = <4>;
 331                         ti,hwmods = "gpmc";
 332                         clocks = <&l3_iclk_div>;
 333                         clock-names = "fck";
 334                 };
 335
 336                 i2c1: i2c@48070000 {
 337                         compatible = "ti,omap4-i2c";
 338                         reg = <0x48070000 0x100>;
 339                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 340                         #address-cells = <1>;
 341                         #size-cells = <0>;
 342                         ti,hwmods = "i2c1";
 343                 };
 344
 345                 i2c2: i2c@48072000 {
 346                         compatible = "ti,omap4-i2c";
 347                         reg = <0x48072000 0x100>;
 348                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 349                         #address-cells = <1>;
 350                         #size-cells = <0>;
 351                         ti,hwmods = "i2c2";
 352                 };
 353
 354                 i2c3: i2c@48060000 {
 355                         compatible = "ti,omap4-i2c";
 356                         reg = <0x48060000 0x100>;
 357                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 358                         #address-cells = <1>;
 359                         #size-cells = <0>;
 360                         ti,hwmods = "i2c3";
 361                 };
 362
 363                 i2c4: i2c@4807a000 {
 364                         compatible = "ti,omap4-i2c";
 365                         reg = <0x4807a000 0x100>;
 366                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 367                         #address-cells = <1>;
 368                         #size-cells = <0>;
 369                         ti,hwmods = "i2c4";
 370                 };
 371
 372                 i2c5: i2c@4807c000 {
 373                         compatible = "ti,omap4-i2c";
 374                         reg = <0x4807c000 0x100>;
 375                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 376                         #address-cells = <1>;
 377                         #size-cells = <0>;
 378                         ti,hwmods = "i2c5";
 379                 };
 380
 381                 hwspinlock: spinlock@4a0f6000 {
 382                         compatible = "ti,omap4-hwspinlock";
 383                         reg = <0x4a0f6000 0x1000>;
 384                         ti,hwmods = "spinlock";
 385                         #hwlock-cells = <1>;
 386                 };
 387
 388                 mcspi1: spi@48098000 {
 389                         compatible = "ti,omap4-mcspi";
 390                         reg = <0x48098000 0x200>;
 391                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 392                         #address-cells = <1>;
 393                         #size-cells = <0>;
 394                         ti,hwmods = "mcspi1";
 395                         ti,spi-num-cs = <4>;
 396                         dmas = <&sdma 35>,
 397                                <&sdma 36>,
 398                                <&sdma 37>,
 399                                <&sdma 38>,
 400                                <&sdma 39>,
 401                                <&sdma 40>,
 402                                <&sdma 41>,
 403                                <&sdma 42>;
 404                         dma-names = "tx0", "rx0", "tx1", "rx1",
 405                                     "tx2", "rx2", "tx3", "rx3";
 406                 };
 407
 408                 mcspi2: spi@4809a000 {
 409                         compatible = "ti,omap4-mcspi";
 410                         reg = <0x4809a000 0x200>;
 411                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 412                         #address-cells = <1>;
 413                         #size-cells = <0>;
 414                         ti,hwmods = "mcspi2";
 415                         ti,spi-num-cs = <2>;
 416                         dmas = <&sdma 43>,
 417                                <&sdma 44>,
 418                                <&sdma 45>,
 419                                <&sdma 46>;
 420                         dma-names = "tx0", "rx0", "tx1", "rx1";
 421                 };
 422
 423                 mcspi3: spi@480b8000 {
 424                         compatible = "ti,omap4-mcspi";
 425                         reg = <0x480b8000 0x200>;
 426                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 427                         #address-cells = <1>;
 428                         #size-cells = <0>;
 429                         ti,hwmods = "mcspi3";
 430                         ti,spi-num-cs = <2>;
 431                         dmas = <&sdma 15>, <&sdma 16>;
 432                         dma-names = "tx0", "rx0";
 433                 };
 434
 435                 mcspi4: spi@480ba000 {
 436                         compatible = "ti,omap4-mcspi";
 437                         reg = <0x480ba000 0x200>;
 438                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 439                         #address-cells = <1>;
 440                         #size-cells = <0>;
 441                         ti,hwmods = "mcspi4";
 442                         ti,spi-num-cs = <1>;
 443                         dmas = <&sdma 70>, <&sdma 71>;
 444                         dma-names = "tx0", "rx0";
 445                 };
 446
 447                 uart1: serial@4806a000 {
 448                         compatible = "ti,omap4-uart";
 449                         reg = <0x4806a000 0x100>;
 450                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 451                         ti,hwmods = "uart1";
 452                         clock-frequency = <48000000>;
 453                 };
 454
 455                 uart2: serial@4806c000 {
 456                         compatible = "ti,omap4-uart";
 457                         reg = <0x4806c000 0x100>;
 458                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 459                         ti,hwmods = "uart2";
 460                         clock-frequency = <48000000>;
 461                 };
 462
 463                 uart3: serial@48020000 {
 464                         compatible = "ti,omap4-uart";
 465                         reg = <0x48020000 0x100>;
 466                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 467                         ti,hwmods = "uart3";
 468                         clock-frequency = <48000000>;
 469                 };
 470
 471                 uart4: serial@4806e000 {
 472                         compatible = "ti,omap4-uart";
 473                         reg = <0x4806e000 0x100>;
 474                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 475                         ti,hwmods = "uart4";
 476                         clock-frequency = <48000000>;
 477                 };
 478
 479                 uart5: serial@48066000 {
 480                         compatible = "ti,omap4-uart";
 481                         reg = <0x48066000 0x100>;
 482                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 483                         ti,hwmods = "uart5";
 484                         clock-frequency = <48000000>;
 485                 };
 486
 487                 uart6: serial@48068000 {
 488                         compatible = "ti,omap4-uart";
 489                         reg = <0x48068000 0x100>;
 490                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 491                         ti,hwmods = "uart6";
 492                         clock-frequency = <48000000>;
 493                 };
 494
 495                 mmc1: mmc@4809c000 {
 496                         compatible = "ti,omap4-hsmmc";
 497                         reg = <0x4809c000 0x400>;
 498                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 499                         ti,hwmods = "mmc1";
 500                         ti,dual-volt;
 501                         ti,needs-special-reset;
 502                         dmas = <&sdma 61>, <&sdma 62>;
 503                         dma-names = "tx", "rx";
 504                         pbias-supply = <&pbias_mmc_reg>;
 505                 };
 506
 507                 mmc2: mmc@480b4000 {
 508                         compatible = "ti,omap4-hsmmc";
 509                         reg = <0x480b4000 0x400>;
 510                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 511                         ti,hwmods = "mmc2";
 512                         ti,needs-special-reset;
 513                         dmas = <&sdma 47>, <&sdma 48>;
 514                         dma-names = "tx", "rx";
 515                 };
 516
 517                 mmc3: mmc@480ad000 {
 518                         compatible = "ti,omap4-hsmmc";
 519                         reg = <0x480ad000 0x400>;
 520                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 521                         ti,hwmods = "mmc3";
 522                         ti,needs-special-reset;
 523                         dmas = <&sdma 77>, <&sdma 78>;
 524                         dma-names = "tx", "rx";
 525                 };
 526
 527                 mmc4: mmc@480d1000 {
 528                         compatible = "ti,omap4-hsmmc";
 529                         reg = <0x480d1000 0x400>;
 530                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 531                         ti,hwmods = "mmc4";
 532                         ti,needs-special-reset;
 533                         dmas = <&sdma 57>, <&sdma 58>;
 534                         dma-names = "tx", "rx";
 535                 };
 536
 537                 mmc5: mmc@480d5000 {
 538                         compatible = "ti,omap4-hsmmc";
 539                         reg = <0x480d5000 0x400>;
 540                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 541                         ti,hwmods = "mmc5";
 542                         ti,needs-special-reset;
 543                         dmas = <&sdma 59>, <&sdma 60>;
 544                         dma-names = "tx", "rx";
 545                 };
 546
 547                 mmu_dsp: mmu@4a066000 {
 548                         compatible = "ti,omap4-iommu";
 549                         reg = <0x4a066000 0x100>;
 550                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 551                         ti,hwmods = "mmu_dsp";
 552                 };
 553
 554                 mmu_ipu: mmu@55082000 {
 555                         compatible = "ti,omap4-iommu";
 556                         reg = <0x55082000 0x100>;
 557                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 558                         ti,hwmods = "mmu_ipu";
 559                         ti,iommu-bus-err-back;
 560                 };
 561
 562                 keypad: keypad@4ae1c000 {
 563                         compatible = "ti,omap4-keypad";
 564                         reg = <0x4ae1c000 0x400>;
 565                         ti,hwmods = "kbd";
 566                 };
 567
 568                 mcpdm: mcpdm@40132000 {
 569                         compatible = "ti,omap4-mcpdm";
 570                         reg = <0x40132000 0x7f>, /* MPU private access */
 571                               <0x49032000 0x7f>; /* L3 Interconnect */
 572                         reg-names = "mpu", "dma";
 573                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 574                         ti,hwmods = "mcpdm";
 575                         dmas = <&sdma 65>,
 576                                <&sdma 66>;
 577                         dma-names = "up_link", "dn_link";
 578                         status = "disabled";
 579                 };
 580
 581                 dmic: dmic@4012e000 {
 582                         compatible = "ti,omap4-dmic";
 583                         reg = <0x4012e000 0x7f>, /* MPU private access */
 584                               <0x4902e000 0x7f>; /* L3 Interconnect */
 585                         reg-names = "mpu", "dma";
 586                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 587                         ti,hwmods = "dmic";
 588                         dmas = <&sdma 67>;
 589                         dma-names = "up_link";
 590                         status = "disabled";
 591                 };
 592
 593                 mcbsp1: mcbsp@40122000 {
 594                         compatible = "ti,omap4-mcbsp";
 595                         reg = <0x40122000 0xff>, /* MPU private access */
 596                               <0x49022000 0xff>; /* L3 Interconnect */
 597                         reg-names = "mpu", "dma";
 598                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 599                         interrupt-names = "common";
 600                         ti,buffer-size = <128>;
 601                         ti,hwmods = "mcbsp1";
 602                         dmas = <&sdma 33>,
 603                                <&sdma 34>;
 604                         dma-names = "tx", "rx";
 605                         status = "disabled";
 606                 };
 607
 608                 mcbsp2: mcbsp@40124000 {
 609                         compatible = "ti,omap4-mcbsp";
 610                         reg = <0x40124000 0xff>, /* MPU private access */
 611                               <0x49024000 0xff>; /* L3 Interconnect */
 612                         reg-names = "mpu", "dma";
 613                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 614                         interrupt-names = "common";
 615                         ti,buffer-size = <128>;
 616                         ti,hwmods = "mcbsp2";
 617                         dmas = <&sdma 17>,
 618                                <&sdma 18>;
 619                         dma-names = "tx", "rx";
 620                         status = "disabled";
 621                 };
 622
 623                 mcbsp3: mcbsp@40126000 {
 624                         compatible = "ti,omap4-mcbsp";
 625                         reg = <0x40126000 0xff>, /* MPU private access */
 626                               <0x49026000 0xff>; /* L3 Interconnect */
 627                         reg-names = "mpu", "dma";
 628                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 629                         interrupt-names = "common";
 630                         ti,buffer-size = <128>;
 631                         ti,hwmods = "mcbsp3";
 632                         dmas = <&sdma 19>,
 633                                <&sdma 20>;
 634                         dma-names = "tx", "rx";
 635                         status = "disabled";
 636                 };
 637
 638                 mailbox: mailbox@4a0f4000 {
 639                         compatible = "ti,omap4-mailbox";
 640                         reg = <0x4a0f4000 0x200>;
 641                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 642                         ti,hwmods = "mailbox";
 643                         ti,mbox-num-users = <3>;
 644                         ti,mbox-num-fifos = <8>;
 645                 };
 646
 647                 timer1: timer@4ae18000 {
 648                         compatible = "ti,omap5430-timer";
 649                         reg = <0x4ae18000 0x80>;
 650                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 651                         ti,hwmods = "timer1";
 652                         ti,timer-alwon;
 653                 };
 654
 655                 timer2: timer@48032000 {
 656                         compatible = "ti,omap5430-timer";
 657                         reg = <0x48032000 0x80>;
 658                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 659                         ti,hwmods = "timer2";
 660                 };
 661
 662                 timer3: timer@48034000 {
 663                         compatible = "ti,omap5430-timer";
 664                         reg = <0x48034000 0x80>;
 665                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 666                         ti,hwmods = "timer3";
 667                 };
 668
 669                 timer4: timer@48036000 {
 670                         compatible = "ti,omap5430-timer";
 671                         reg = <0x48036000 0x80>;
 672                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 673                         ti,hwmods = "timer4";
 674                 };
 675
 676                 timer5: timer@40138000 {
 677                         compatible = "ti,omap5430-timer";
 678                         reg = <0x40138000 0x80>,
 679                               <0x49038000 0x80>;
 680                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 681                         ti,hwmods = "timer5";
 682                         ti,timer-dsp;
 683                         ti,timer-pwm;
 684                 };
 685
 686                 timer6: timer@4013a000 {
 687                         compatible = "ti,omap5430-timer";
 688                         reg = <0x4013a000 0x80>,
 689                               <0x4903a000 0x80>;
 690                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 691                         ti,hwmods = "timer6";
 692                         ti,timer-dsp;
 693                         ti,timer-pwm;
 694                 };
 695
 696                 timer7: timer@4013c000 {
 697                         compatible = "ti,omap5430-timer";
 698                         reg = <0x4013c000 0x80>,
 699                               <0x4903c000 0x80>;
 700                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 701                         ti,hwmods = "timer7";
 702                         ti,timer-dsp;
 703                 };
 704
 705                 timer8: timer@4013e000 {
 706                         compatible = "ti,omap5430-timer";
 707                         reg = <0x4013e000 0x80>,
 708                               <0x4903e000 0x80>;
 709                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 710                         ti,hwmods = "timer8";
 711                         ti,timer-dsp;
 712                         ti,timer-pwm;
 713                 };
 714
 715                 timer9: timer@4803e000 {
 716                         compatible = "ti,omap5430-timer";
 717                         reg = <0x4803e000 0x80>;
 718                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 719                         ti,hwmods = "timer9";
 720                         ti,timer-pwm;
 721                 };
 722
 723                 timer10: timer@48086000 {
 724                         compatible = "ti,omap5430-timer";
 725                         reg = <0x48086000 0x80>;
 726                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 727                         ti,hwmods = "timer10";
 728                         ti,timer-pwm;
 729                 };
 730
 731                 timer11: timer@48088000 {
 732                         compatible = "ti,omap5430-timer";
 733                         reg = <0x48088000 0x80>;
 734                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 735                         ti,hwmods = "timer11";
 736                         ti,timer-pwm;
 737                 };
 738
 739                 wdt2: wdt@4ae14000 {
 740                         compatible = "ti,omap5-wdt", "ti,omap3-wdt";
 741                         reg = <0x4ae14000 0x80>;
 742                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 743                         ti,hwmods = "wd_timer2";
 744                 };
 745
 746                 dmm@4e000000 {
 747                         compatible = "ti,omap5-dmm";
 748                         reg = <0x4e000000 0x800>;
 749                         interrupts = <0 113 0x4>;
 750                         ti,hwmods = "dmm";
 751                 };
 752
 753                 emif1: emif@4c000000 {
 754                         compatible      = "ti,emif-4d5";
 755                         ti,hwmods       = "emif1";
 756                         ti,no-idle-on-init;
 757                         phy-type        = <2>; /* DDR PHY type: Intelli PHY */
 758                         reg = <0x4c000000 0x400>;
 759                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 760                         hw-caps-read-idle-ctrl;
 761                         hw-caps-ll-interface;
 762                         hw-caps-temp-alert;
 763                 };
 764
 765                 emif2: emif@4d000000 {
 766                         compatible      = "ti,emif-4d5";
 767                         ti,hwmods       = "emif2";
 768                         ti,no-idle-on-init;
 769                         phy-type        = <2>; /* DDR PHY type: Intelli PHY */
 770                         reg = <0x4d000000 0x400>;
 771                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 772                         hw-caps-read-idle-ctrl;
 773                         hw-caps-ll-interface;
 774                         hw-caps-temp-alert;
 775                 };
 776
 777                 omap_control_usb2phy: control-phy@4a002300 {
 778                         compatible = "ti,control-phy-usb2";
 779                         reg = <0x4a002300 0x4>;
 780                         reg-names = "power";
 781                 };
 782
 783                 omap_control_usb3phy: control-phy@4a002370 {
 784                         compatible = "ti,control-phy-pipe3";
 785                         reg = <0x4a002370 0x4>;
 786                         reg-names = "power";
 787                 };
 788
 789                 usb3: omap_dwc3@4a020000 {
 790                         compatible = "ti,dwc3";
 791                         ti,hwmods = "usb_otg_ss";
 792                         reg = <0x4a020000 0x10000>;
 793                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 794                         #address-cells = <1>;
 795                         #size-cells = <1>;
 796                         utmi-mode = <2>;
 797                         ranges;
 798                         dwc3@4a030000 {
 799                                 compatible = "snps,dwc3";
 800                                 reg = <0x4a030000 0x10000>;
 801                                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 802                                 phys = <&usb2_phy>, <&usb3_phy>;
 803                                 phy-names = "usb2-phy", "usb3-phy";
 804                                 dr_mode = "peripheral";
 805                                 tx-fifo-resize;
 806                         };
 807                 };
 808
 809                 ocp2scp@4a080000 {
 810                         compatible = "ti,omap-ocp2scp";
 811                         #address-cells = <1>;
 812                         #size-cells = <1>;
 813                         reg = <0x4a080000 0x20>;
 814                         ranges;
 815                         ti,hwmods = "ocp2scp1";
 816                         usb2_phy: usb2phy@4a084000 {
 817                                 compatible = "ti,omap-usb2";
 818                                 reg = <0x4a084000 0x7c>;
 819                                 ctrl-module = <&omap_control_usb2phy>;
 820                                 clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>;
 821                                 clock-names = "wkupclk", "refclk";
 822                                 #phy-cells = <0>;
 823                         };
 824
 825                         usb3_phy: usb3phy@4a084400 {
 826                                 compatible = "ti,omap-usb3";
 827                                 reg = <0x4a084400 0x80>,
 828                                       <0x4a084800 0x64>,
 829                                       <0x4a084c00 0x40>;
 830                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
 831                                 ctrl-module = <&omap_control_usb3phy>;
 832                                 clocks = <&usb_phy_cm_clk32k>,
 833                                          <&sys_clkin>,
 834                                          <&usb_otg_ss_refclk960m>;
 835                                 clock-names =   "wkupclk",
 836                                                 "sysclk",
 837                                                 "refclk";
 838                                 #phy-cells = <0>;
 839                         };
 840                 };
 841
 842                 usbhstll: usbhstll@4a062000 {
 843                         compatible = "ti,usbhs-tll";
 844                         reg = <0x4a062000 0x1000>;
 845                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 846                         ti,hwmods = "usb_tll_hs";
 847                 };
 848
 849                 usbhshost: usbhshost@4a064000 {
 850                         compatible = "ti,usbhs-host";
 851                         reg = <0x4a064000 0x800>;
 852                         ti,hwmods = "usb_host_hs";
 853                         #address-cells = <1>;
 854                         #size-cells = <1>;
 855                         ranges;
 856                         clocks = <&l3init_60m_fclk>,
 857                                  <&xclk60mhsp1_ck>,
 858                                  <&xclk60mhsp2_ck>;
 859                         clock-names = "refclk_60m_int",
 860                                       "refclk_60m_ext_p1",
 861                                       "refclk_60m_ext_p2";
 862
 863                         usbhsohci: ohci@4a064800 {
 864                                 compatible = "ti,ohci-omap3";
 865                                 reg = <0x4a064800 0x400>;
 866                                 interrupt-parent = <&gic>;
 867                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 868                         };
 869
 870                         usbhsehci: ehci@4a064c00 {
 871                                 compatible = "ti,ehci-omap";
 872                                 reg = <0x4a064c00 0x400>;
 873                                 interrupt-parent = <&gic>;
 874                                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 875                         };
 876                 };
 877
 878                 bandgap: bandgap@4a0021e0 {
 879                         reg = <0x4a0021e0 0xc
 880                                0x4a00232c 0xc
 881                                0x4a002380 0x2c
 882                                0x4a0023C0 0x3c>;
 883                         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 884                         compatible = "ti,omap5430-bandgap";
 885
 886                         #thermal-sensor-cells = <1>;
 887                 };
 888
 889                 omap_control_sata: control-phy@4a002374 {
 890                         compatible = "ti,control-phy-pipe3";
 891                         reg = <0x4a002374 0x4>;
 892                         reg-names = "power";
 893                         clocks = <&sys_clkin>;
 894                         clock-names = "sysclk";
 895                 };
 896
 897                 /* OCP2SCP3 */
 898                 ocp2scp@4a090000 {
 899                         compatible = "ti,omap-ocp2scp";
 900                         #address-cells = <1>;
 901                         #size-cells = <1>;
 902                         reg = <0x4a090000 0x20>;
 903                         ranges;
 904                         ti,hwmods = "ocp2scp3";
 905                         sata_phy: phy@4a096000 {
 906                                 compatible = "ti,phy-pipe3-sata";
 907                                 reg = <0x4A096000 0x80>, /* phy_rx */
 908                                       <0x4A096400 0x64>, /* phy_tx */
 909                                       <0x4A096800 0x40>; /* pll_ctrl */
 910                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
 911                                 ctrl-module = <&omap_control_sata>;
 912                                 clocks = <&sys_clkin>;
 913                                 clock-names = "sysclk";
 914                                 #phy-cells = <0>;
 915                         };
 916                 };
 917
 918                 sata: sata@4a141100 {
 919                         compatible = "snps,dwc-ahci";
 920                         reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
 921                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 922                         phys = <&sata_phy>;
 923                         phy-names = "sata-phy";
 924                         clocks = <&sata_ref_clk>;
 925                         ti,hwmods = "sata";
 926                 };
 927
 928                 dss: dss@58000000 {
 929                         compatible = "ti,omap5-dss";
 930                         reg = <0x58000000 0x80>;
 931                         status = "disabled";
 932                         ti,hwmods = "dss_core";
 933                         clocks = <&dss_dss_clk>;
 934                         clock-names = "fck";
 935                         #address-cells = <1>;
 936                         #size-cells = <1>;
 937                         ranges;
 938
 939                         dispc@58001000 {
 940                                 compatible = "ti,omap5-dispc";
 941                                 reg = <0x58001000 0x1000>;
 942                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 943                                 ti,hwmods = "dss_dispc";
 944                                 clocks = <&dss_dss_clk>;
 945                                 clock-names = "fck";
 946                         };
 947
 948                         dsi1: encoder@58004000 {
 949                                 compatible = "ti,omap5-dsi";
 950                                 reg = <0x58004000 0x200>,
 951                                       <0x58004200 0x40>,
 952                                       <0x58004300 0x40>;
 953                                 reg-names = "proto", "phy", "pll";
 954                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 955                                 status = "disabled";
 956                                 ti,hwmods = "dss_dsi1";
 957                                 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
 958                                 clock-names = "fck", "sys_clk";
 959                         };
 960
 961                         dsi2: encoder@58005000 {
 962                                 compatible = "ti,omap5-dsi";
 963                                 reg = <0x58009000 0x200>,
 964                                       <0x58009200 0x40>,
 965                                       <0x58009300 0x40>;
 966                                 reg-names = "proto", "phy", "pll";
 967                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 968                                 status = "disabled";
 969                                 ti,hwmods = "dss_dsi2";
 970                                 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
 971                                 clock-names = "fck", "sys_clk";
 972                         };
 973
 974                         hdmi: encoder@58060000 {
 975                                 compatible = "ti,omap5-hdmi";
 976                                 reg = <0x58040000 0x200>,
 977                                       <0x58040200 0x80>,
 978                                       <0x58040300 0x80>,
 979                                       <0x58060000 0x19000>;
 980                                 reg-names = "wp", "pll", "phy", "core";
 981                                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 982                                 status = "disabled";
 983                                 ti,hwmods = "dss_hdmi";
 984                                 clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
 985                                 clock-names = "fck", "sys_clk";
 986                                 dmas = <&sdma 76>;
 987                                 dma-names = "audio_tx";
 988                         };
 989                 };
 990
 991                 abb_mpu: regulator-abb-mpu {
 992                         compatible = "ti,abb-v2";
 993                         regulator-name = "abb_mpu";
 994                         #address-cells = <0>;
 995                         #size-cells = <0>;
 996                         clocks = <&sys_clkin>;
 997                         ti,settling-time = <50>;
 998                         ti,clock-cycles = <16>;
 999
1000                         reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
1001                               <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
1002                         reg-names = "base-address", "int-address",
1003                                     "efuse-address", "ldo-address";
1004                         ti,tranxdone-status-mask = <0x80>;
1005                         /* LDOVBBMPU_MUX_CTRL */
1006                         ti,ldovbb-override-mask = <0x400>;
1007                         /* LDOVBBMPU_VSET_OUT */
1008                         ti,ldovbb-vset-mask = <0x1F>;
1009
1010                         /*
1011                          * NOTE: only FBB mode used but actual vset will
1012                          * determine final biasing
1013                          */
1014                         ti,abb_info = <
1015                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1016                         1060000         0       0x0     0 0x02000000 0x01F00000
1017                         1250000         0       0x4     0 0x02000000 0x01F00000
1018                         >;
1019                 };
1020
1021                 abb_mm: regulator-abb-mm {
1022                         compatible = "ti,abb-v2";
1023                         regulator-name = "abb_mm";
1024                         #address-cells = <0>;
1025                         #size-cells = <0>;
1026                         clocks = <&sys_clkin>;
1027                         ti,settling-time = <50>;
1028                         ti,clock-cycles = <16>;
1029
1030                         reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
1031                               <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
1032                         reg-names = "base-address", "int-address",
1033                                     "efuse-address", "ldo-address";
1034                         ti,tranxdone-status-mask = <0x80000000>;
1035                         /* LDOVBBMM_MUX_CTRL */
1036                         ti,ldovbb-override-mask = <0x400>;
1037                         /* LDOVBBMM_VSET_OUT */
1038                         ti,ldovbb-vset-mask = <0x1F>;
1039
1040                         /*
1041                          * NOTE: only FBB mode used but actual vset will
1042                          * determine final biasing
1043                          */
1044                         ti,abb_info = <
1045                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1046                         1025000         0       0x0     0 0x02000000 0x01F00000
1047                         1120000         0       0x4     0 0x02000000 0x01F00000
1048                         >;
1049                 };
1050         };
1051 };
1052
1053 /include/ "omap54xx-clocks.dtsi"