arch/arm/boot/dts/omap5-l4-abe.dtsi

   1 &l4_abe {                                               /* 0x40100000 */
   2         compatible = "ti,omap5-l4-abe", "simple-bus";
   3         reg = <0x40100000 0x400>,
   4               <0x40100400 0x400>;
   5         reg-names = "la", "ap";
   6         #address-cells = <1>;
   7         #size-cells = <1>;
   8         ranges = <0x00000000 0x40100000 0x100000>,      /* segment 0 */
   9                  <0x49000000 0x49000000 0x100000>;
  10         segment@0 {                                     /* 0x40100000 */
  11                 compatible = "simple-bus";
  12                 #address-cells = <1>;
  13                 #size-cells = <1>;
  14                 ranges =
  15                          /* CPU to L4 ABE mapping */
  16                          <0x00000000 0x00000000 0x000400>,      /* ap 0 */
  17                          <0x00000400 0x00000400 0x000400>,      /* ap 1 */
  18                          <0x00022000 0x00022000 0x001000>,      /* ap 2 */
  19                          <0x00023000 0x00023000 0x001000>,      /* ap 3 */
  20                          <0x00024000 0x00024000 0x001000>,      /* ap 4 */
  21                          <0x00025000 0x00025000 0x001000>,      /* ap 5 */
  22                          <0x00026000 0x00026000 0x001000>,      /* ap 6 */
  23                          <0x00027000 0x00027000 0x001000>,      /* ap 7 */
  24                          <0x00028000 0x00028000 0x001000>,      /* ap 8 */
  25                          <0x00029000 0x00029000 0x001000>,      /* ap 9 */
  26                          <0x0002a000 0x0002a000 0x001000>,      /* ap 10 */
  27                          <0x0002b000 0x0002b000 0x001000>,      /* ap 11 */
  28                          <0x0002e000 0x0002e000 0x001000>,      /* ap 12 */
  29                          <0x0002f000 0x0002f000 0x001000>,      /* ap 13 */
  30                          <0x00030000 0x00030000 0x001000>,      /* ap 14 */
  31                          <0x00031000 0x00031000 0x001000>,      /* ap 15 */
  32                          <0x00032000 0x00032000 0x001000>,      /* ap 16 */
  33                          <0x00033000 0x00033000 0x001000>,      /* ap 17 */
  34                          <0x00038000 0x00038000 0x001000>,      /* ap 18 */
  35                          <0x00039000 0x00039000 0x001000>,      /* ap 19 */
  36                          <0x0003a000 0x0003a000 0x001000>,      /* ap 20 */
  37                          <0x0003b000 0x0003b000 0x001000>,      /* ap 21 */
  38                          <0x0003c000 0x0003c000 0x001000>,      /* ap 22 */
  39                          <0x0003d000 0x0003d000 0x001000>,      /* ap 23 */
  40                          <0x0003e000 0x0003e000 0x001000>,      /* ap 24 */
  41                          <0x0003f000 0x0003f000 0x001000>,      /* ap 25 */
  42                          <0x00080000 0x00080000 0x010000>,      /* ap 26 */
  43                          <0x00080000 0x00080000 0x001000>,      /* ap 27 */
  44                          <0x000a0000 0x000a0000 0x010000>,      /* ap 28 */
  45                          <0x000a0000 0x000a0000 0x001000>,      /* ap 29 */
  46                          <0x000c0000 0x000c0000 0x010000>,      /* ap 30 */
  47                          <0x000c0000 0x000c0000 0x001000>,      /* ap 31 */
  48                          <0x000f1000 0x000f1000 0x001000>,      /* ap 32 */
  49                          <0x000f2000 0x000f2000 0x001000>,      /* ap 33 */
  50
  51                          /* L3 to L4 ABE mapping */
  52                          <0x49000000 0x49000000 0x000400>,      /* ap 0 */
  53                          <0x49000400 0x49000400 0x000400>,      /* ap 1 */
  54                          <0x49022000 0x49022000 0x001000>,      /* ap 2 */
  55                          <0x49023000 0x49023000 0x001000>,      /* ap 3 */
  56                          <0x49024000 0x49024000 0x001000>,      /* ap 4 */
  57                          <0x49025000 0x49025000 0x001000>,      /* ap 5 */
  58                          <0x49026000 0x49026000 0x001000>,      /* ap 6 */
  59                          <0x49027000 0x49027000 0x001000>,      /* ap 7 */
  60                          <0x49028000 0x49028000 0x001000>,      /* ap 8 */
  61                          <0x49029000 0x49029000 0x001000>,      /* ap 9 */
  62                          <0x4902a000 0x4902a000 0x001000>,      /* ap 10 */
  63                          <0x4902b000 0x4902b000 0x001000>,      /* ap 11 */
  64                          <0x4902e000 0x4902e000 0x001000>,      /* ap 12 */
  65                          <0x4902f000 0x4902f000 0x001000>,      /* ap 13 */
  66                          <0x49030000 0x49030000 0x001000>,      /* ap 14 */
  67                          <0x49031000 0x49031000 0x001000>,      /* ap 15 */
  68                          <0x49032000 0x49032000 0x001000>,      /* ap 16 */
  69                          <0x49033000 0x49033000 0x001000>,      /* ap 17 */
  70                          <0x49038000 0x49038000 0x001000>,      /* ap 18 */
  71                          <0x49039000 0x49039000 0x001000>,      /* ap 19 */
  72                          <0x4903a000 0x4903a000 0x001000>,      /* ap 20 */
  73                          <0x4903b000 0x4903b000 0x001000>,      /* ap 21 */
  74                          <0x4903c000 0x4903c000 0x001000>,      /* ap 22 */
  75                          <0x4903d000 0x4903d000 0x001000>,      /* ap 23 */
  76                          <0x4903e000 0x4903e000 0x001000>,      /* ap 24 */
  77                          <0x4903f000 0x4903f000 0x001000>,      /* ap 25 */
  78                          <0x49080000 0x49080000 0x010000>,      /* ap 26 */
  79                          <0x49080000 0x49080000 0x001000>,      /* ap 27 */
  80                          <0x490a0000 0x490a0000 0x010000>,      /* ap 28 */
  81                          <0x490a0000 0x490a0000 0x001000>,      /* ap 29 */
  82                          <0x490c0000 0x490c0000 0x010000>,      /* ap 30 */
  83                          <0x490c0000 0x490c0000 0x001000>,      /* ap 31 */
  84                          <0x490f1000 0x490f1000 0x001000>,      /* ap 32 */
  85                          <0x490f2000 0x490f2000 0x001000>;      /* ap 33 */
  86
  87                 target-module@22000 {                   /* 0x40122000, ap 2 02.0 */
  88                         compatible = "ti,sysc-omap2", "ti,sysc";
  89                         ti,hwmods = "mcbsp1";
  90                         reg = <0x2208c 0x4>;
  91                         reg-names = "sysc";
  92                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
  93                                          SYSC_OMAP2_ENAWAKEUP |
  94                                          SYSC_OMAP2_SOFTRESET)>;
  95                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  96                                         <SYSC_IDLE_NO>,
  97                                         <SYSC_IDLE_SMART>;
  98                         /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
  99                         clocks = <&abe_clkctrl OMAP5_MCBSP1_CLKCTRL 0>;
 100                         clock-names = "fck";
 101                         #address-cells = <1>;
 102                         #size-cells = <1>;
 103                         ranges = <0x0 0x22000 0x1000>,
 104                                  <0x49022000 0x49022000 0x1000>;
 105
 106                         mcbsp1: mcbsp@0 {
 107                                 compatible = "ti,omap4-mcbsp";
 108                                 reg = <0x0 0xff>, /* MPU private access */
 109                                       <0x49022000 0xff>; /* L3 Interconnect */
 110                                 reg-names = "mpu", "dma";
 111                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 112                                 interrupt-names = "common";
 113                                 ti,buffer-size = <128>;
 114                                 dmas = <&sdma 33>,
 115                                        <&sdma 34>;
 116                                 dma-names = "tx", "rx";
 117                                 status = "disabled";
 118                         };
 119                 };
 120
 121                 target-module@24000 {                   /* 0x40124000, ap 4 04.0 */
 122                         compatible = "ti,sysc-omap2", "ti,sysc";
 123                         ti,hwmods = "mcbsp2";
 124                         reg = <0x2408c 0x4>;
 125                         reg-names = "sysc";
 126                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
 127                                          SYSC_OMAP2_ENAWAKEUP |
 128                                          SYSC_OMAP2_SOFTRESET)>;
 129                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 130                                         <SYSC_IDLE_NO>,
 131                                         <SYSC_IDLE_SMART>;
 132                         /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
 133                         clocks = <&abe_clkctrl OMAP5_MCBSP2_CLKCTRL 0>;
 134                         clock-names = "fck";
 135                         #address-cells = <1>;
 136                         #size-cells = <1>;
 137                         ranges = <0x0 0x24000 0x1000>,
 138                                  <0x49024000 0x49024000 0x1000>;
 139
 140                         mcbsp2: mcbsp@0 {
 141                                 compatible = "ti,omap4-mcbsp";
 142                                 reg = <0x0 0xff>, /* MPU private access */
 143                                       <0x49024000 0xff>; /* L3 Interconnect */
 144                                 reg-names = "mpu", "dma";
 145                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 146                                 interrupt-names = "common";
 147                                 ti,buffer-size = <128>;
 148                                 dmas = <&sdma 17>,
 149                                        <&sdma 18>;
 150                                 dma-names = "tx", "rx";
 151                                 status = "disabled";
 152                         };
 153                 };
 154
 155                 target-module@26000 {                   /* 0x40126000, ap 6 06.0 */
 156                         compatible = "ti,sysc-omap2", "ti,sysc";
 157                         ti,hwmods = "mcbsp3";
 158                         reg = <0x2608c 0x4>;
 159                         reg-names = "sysc";
 160                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
 161                                          SYSC_OMAP2_ENAWAKEUP |
 162                                          SYSC_OMAP2_SOFTRESET)>;
 163                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 164                                         <SYSC_IDLE_NO>,
 165                                         <SYSC_IDLE_SMART>;
 166                         /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
 167                         clocks = <&abe_clkctrl OMAP5_MCBSP3_CLKCTRL 0>;
 168                         clock-names = "fck";
 169                         #address-cells = <1>;
 170                         #size-cells = <1>;
 171                         ranges = <0x0 0x26000 0x1000>,
 172                                  <0x49026000 0x49026000 0x1000>;
 173
 174                         mcbsp3: mcbsp@0 {
 175                                 compatible = "ti,omap4-mcbsp";
 176                                 reg = <0x0 0xff>, /* MPU private access */
 177                                       <0x49026000 0xff>; /* L3 Interconnect */
 178                                 reg-names = "mpu", "dma";
 179                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 180                                 interrupt-names = "common";
 181                                 ti,buffer-size = <128>;
 182                                 dmas = <&sdma 19>,
 183                                        <&sdma 20>;
 184                                 dma-names = "tx", "rx";
 185                                 status = "disabled";
 186                         };
 187                 };
 188
 189                 target-module@28000 {                   /* 0x40128000, ap 8 08.0 */
 190                         compatible = "ti,sysc";
 191                         status = "disabled";
 192                         #address-cells = <1>;
 193                         #size-cells = <1>;
 194                         ranges = <0x0 0x28000 0x1000>,
 195                                  <0x49028000 0x49028000 0x1000>;
 196                 };
 197
 198                 target-module@2a000 {                   /* 0x4012a000, ap 10 0a.0 */
 199                         compatible = "ti,sysc";
 200                         status = "disabled";
 201                         #address-cells = <1>;
 202                         #size-cells = <1>;
 203                         ranges = <0x0 0x2a000 0x1000>,
 204                                  <0x4902a000 0x4902a000 0x1000>;
 205                 };
 206
 207                 target-module@2e000 {                   /* 0x4012e000, ap 12 0c.0 */
 208                         compatible = "ti,sysc-omap4", "ti,sysc";
 209                         ti,hwmods = "dmic";
 210                         reg = <0x2e000 0x4>,
 211                               <0x2e010 0x4>;
 212                         reg-names = "rev", "sysc";
 213                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
 214                                          SYSC_OMAP4_SOFTRESET)>;
 215                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 216                                         <SYSC_IDLE_NO>,
 217                                         <SYSC_IDLE_SMART>,
 218                                         <SYSC_IDLE_SMART_WKUP>;
 219                         /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
 220                         clocks = <&abe_clkctrl OMAP5_DMIC_CLKCTRL 0>;
 221                         clock-names = "fck";
 222                         #address-cells = <1>;
 223                         #size-cells = <1>;
 224                         ranges = <0x0 0x2e000 0x1000>,
 225                                  <0x4902e000 0x4902e000 0x1000>;
 226
 227                         dmic: dmic@0 {
 228                                 compatible = "ti,omap4-dmic";
 229                                 reg = <0x0 0x7f>, /* MPU private access */
 230                                       <0x4902e000 0x7f>; /* L3 Interconnect */
 231                                 reg-names = "mpu", "dma";
 232                                 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 233                                 dmas = <&sdma 67>;
 234                                 dma-names = "up_link";
 235                                 status = "disabled";
 236                         };
 237                 };
 238
 239                 target-module@30000 {                   /* 0x40130000, ap 14 0e.0 */
 240                         compatible = "ti,sysc";
 241                         status = "disabled";
 242                         #address-cells = <1>;
 243                         #size-cells = <1>;
 244                         ranges = <0x0 0x30000 0x1000>,
 245                                  <0x49030000 0x49030000 0x1000>;
 246                 };
 247
 248                 mcpdm_module: target-module@32000 {     /* 0x40132000, ap 16 10.0 */
 249                         compatible = "ti,sysc-omap4", "ti,sysc";
 250                         ti,hwmods = "mcpdm";
 251                         reg = <0x32000 0x4>,
 252                               <0x32010 0x4>;
 253                         reg-names = "rev", "sysc";
 254                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
 255                                          SYSC_OMAP4_SOFTRESET)>;
 256                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 257                                         <SYSC_IDLE_NO>,
 258                                         <SYSC_IDLE_SMART>,
 259                                         <SYSC_IDLE_SMART_WKUP>;
 260                         /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
 261                         clocks = <&abe_clkctrl OMAP5_MCPDM_CLKCTRL 0>;
 262                         clock-names = "fck";
 263                         #address-cells = <1>;
 264                         #size-cells = <1>;
 265                         ranges = <0x0 0x32000 0x1000>,
 266                                  <0x49032000 0x49032000 0x1000>;
 267
 268                         /* Must be only enabled for boards with pdmclk wired */
 269                         status = "disabled";
 270
 271                         mcpdm: mcpdm@0 {
 272                                 compatible = "ti,omap4-mcpdm";
 273                                 reg = <0x0 0x7f>, /* MPU private access */
 274                                       <0x49032000 0x7f>; /* L3 Interconnect */
 275                                 reg-names = "mpu", "dma";
 276                                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 277                                 dmas = <&sdma 65>,
 278                                        <&sdma 66>;
 279                                 dma-names = "up_link", "dn_link";
 280                         };
 281                 };
 282
 283                 target-module@38000 {                   /* 0x40138000, ap 18 12.0 */
 284                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
 285                         ti,hwmods = "timer5";
 286                         reg = <0x38000 0x4>,
 287                               <0x38010 0x4>;
 288                         reg-names = "rev", "sysc";
 289                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
 290                                          SYSC_OMAP4_SOFTRESET)>;
 291                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 292                                         <SYSC_IDLE_NO>,
 293                                         <SYSC_IDLE_SMART>,
 294                                         <SYSC_IDLE_SMART_WKUP>;
 295                         /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
 296                         clocks = <&abe_clkctrl OMAP5_TIMER5_CLKCTRL 0>;
 297                         clock-names = "fck";
 298                         #address-cells = <1>;
 299                         #size-cells = <1>;
 300                         ranges = <0x0 0x38000 0x1000>,
 301                                  <0x49038000 0x49038000 0x1000>;
 302
 303                         timer5: timer@0 {
 304                                 compatible = "ti,omap5430-timer";
 305                                 reg = <0x0 0x80>,
 306                                       <0x49038000 0x80>;
 307                                 clocks = <&abe_clkctrl OMAP5_TIMER5_CLKCTRL 24>;
 308                                 clock-names = "fck";
 309                                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 310                                 ti,timer-dsp;
 311                                 ti,timer-pwm;
 312                         };
 313                 };
 314
 315                 target-module@3a000 {                   /* 0x4013a000, ap 20 14.0 */
 316                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
 317                         ti,hwmods = "timer6";
 318                         reg = <0x3a000 0x4>,
 319                               <0x3a010 0x4>;
 320                         reg-names = "rev", "sysc";
 321                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
 322                                          SYSC_OMAP4_SOFTRESET)>;
 323                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 324                                         <SYSC_IDLE_NO>,
 325                                         <SYSC_IDLE_SMART>,
 326                                         <SYSC_IDLE_SMART_WKUP>;
 327                         /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
 328                         clocks = <&abe_clkctrl OMAP5_TIMER6_CLKCTRL 0>;
 329                         clock-names = "fck";
 330                         #address-cells = <1>;
 331                         #size-cells = <1>;
 332                         ranges = <0x0 0x3a000 0x1000>,
 333                                  <0x4903a000 0x4903a000 0x1000>;
 334
 335                         timer6: timer@0 {
 336                                 compatible = "ti,omap5430-timer";
 337                                 reg = <0x0 0x80>,
 338                                       <0x4903a000 0x80>;
 339                                 clocks = <&abe_clkctrl OMAP5_TIMER6_CLKCTRL 24>;
 340                                 clock-names = "fck";
 341                                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 342                                 ti,timer-dsp;
 343                                 ti,timer-pwm;
 344                         };
 345                 };
 346
 347                 target-module@3c000 {                   /* 0x4013c000, ap 22 16.0 */
 348                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
 349                         ti,hwmods = "timer7";
 350                         reg = <0x3c000 0x4>,
 351                               <0x3c010 0x4>;
 352                         reg-names = "rev", "sysc";
 353                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
 354                                          SYSC_OMAP4_SOFTRESET)>;
 355                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 356                                         <SYSC_IDLE_NO>,
 357                                         <SYSC_IDLE_SMART>,
 358                                         <SYSC_IDLE_SMART_WKUP>;
 359                         /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
 360                         clocks = <&abe_clkctrl OMAP5_TIMER7_CLKCTRL 0>;
 361                         clock-names = "fck";
 362                         #address-cells = <1>;
 363                         #size-cells = <1>;
 364                         ranges = <0x0 0x3c000 0x1000>,
 365                                  <0x4903c000 0x4903c000 0x1000>;
 366
 367                         timer7: timer@0 {
 368                                 compatible = "ti,omap5430-timer";
 369                                 reg = <0x0 0x80>,
 370                                       <0x4903c000 0x80>;
 371                                 clocks = <&abe_clkctrl OMAP5_TIMER7_CLKCTRL 24>;
 372                                 clock-names = "fck";
 373                                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 374                                 ti,timer-dsp;
 375                         };
 376                 };
 377
 378                 target-module@3e000 {                   /* 0x4013e000, ap 24 18.0 */
 379                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
 380                         ti,hwmods = "timer8";
 381                         reg = <0x3e000 0x4>,
 382                               <0x3e010 0x4>;
 383                         reg-names = "rev", "sysc";
 384                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
 385                                          SYSC_OMAP4_SOFTRESET)>;
 386                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 387                                         <SYSC_IDLE_NO>,
 388                                         <SYSC_IDLE_SMART>,
 389                                         <SYSC_IDLE_SMART_WKUP>;
 390                         /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
 391                         clocks = <&abe_clkctrl OMAP5_TIMER8_CLKCTRL 0>;
 392                         clock-names = "fck";
 393                         #address-cells = <1>;
 394                         #size-cells = <1>;
 395                         ranges = <0x0 0x3e000 0x1000>,
 396                                  <0x4903e000 0x4903e000 0x1000>;
 397
 398                         timer8: timer@0 {
 399                                 compatible = "ti,omap5430-timer";
 400                                 reg = <0x0 0x80>,
 401                                       <0x4903e000 0x80>;
 402                                 clocks = <&abe_clkctrl OMAP5_TIMER8_CLKCTRL 24>;
 403                                 clock-names = "fck";
 404                                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 405                                 ti,timer-dsp;
 406                                 ti,timer-pwm;
 407                         };
 408                 };
 409
 410                 target-module@80000 {                   /* 0x40180000, ap 26 1a.0 */
 411                         compatible = "ti,sysc";
 412                         status = "disabled";
 413                         #address-cells = <1>;
 414                         #size-cells = <1>;
 415                         ranges = <0x0 0x80000 0x10000>,
 416                                  <0x49080000 0x49080000 0x10000>;
 417                 };
 418
 419                 target-module@a0000 {                   /* 0x401a0000, ap 28 1c.0 */
 420                         compatible = "ti,sysc";
 421                         status = "disabled";
 422                         #address-cells = <1>;
 423                         #size-cells = <1>;
 424                         ranges = <0x0 0xa0000 0x10000>,
 425                                  <0x490a0000 0x490a0000 0x10000>;
 426                 };
 427
 428                 target-module@c0000 {                   /* 0x401c0000, ap 30 1e.0 */
 429                         compatible = "ti,sysc";
 430                         status = "disabled";
 431                         #address-cells = <1>;
 432                         #size-cells = <1>;
 433                         ranges = <0x0 0xc0000 0x10000>,
 434                                  <0x490c0000 0x490c0000 0x10000>;
 435                 };
 436
 437                 target-module@f1000 {                   /* 0x401f1000, ap 32 20.0 */
 438                         compatible = "ti,sysc";
 439                         status = "disabled";
 440                         #address-cells = <1>;
 441                         #size-cells = <1>;
 442                         ranges = <0x0 0xf1000 0x1000>,
 443                                  <0x490f1000 0x490f1000 0x1000>;
 444                 };
 445         };
 446 };
 447