arch/arm/boot/dts/omap5-l4-abe.dtsi

   1 &l4_abe {                                               /* 0x40100000 */
   2         compatible = "ti,omap5-l4-abe", "simple-bus";
   3         reg = <0x40100000 0x400>,
   4               <0x40100400 0x400>;
   5         reg-names = "la", "ap";
   6         #address-cells = <1>;
   7         #size-cells = <1>;
   8         ranges = <0x00000000 0x40100000 0x100000>,      /* segment 0 */
   9                  <0x49000000 0x49000000 0x100000>;
  10         segment@0 {                                     /* 0x40100000 */
  11                 compatible = "simple-bus";
  12                 #address-cells = <1>;
  13                 #size-cells = <1>;
  14                 ranges =
  15                          /* CPU to L4 ABE mapping */
  16                          <0x00000000 0x00000000 0x000400>,      /* ap 0 */
  17                          <0x00000400 0x00000400 0x000400>,      /* ap 1 */
  18                          <0x00022000 0x00022000 0x001000>,      /* ap 2 */
  19                          <0x00023000 0x00023000 0x001000>,      /* ap 3 */
  20                          <0x00024000 0x00024000 0x001000>,      /* ap 4 */
  21                          <0x00025000 0x00025000 0x001000>,      /* ap 5 */
  22                          <0x00026000 0x00026000 0x001000>,      /* ap 6 */
  23                          <0x00027000 0x00027000 0x001000>,      /* ap 7 */
  24                          <0x00028000 0x00028000 0x001000>,      /* ap 8 */
  25                          <0x00029000 0x00029000 0x001000>,      /* ap 9 */
  26                          <0x0002a000 0x0002a000 0x001000>,      /* ap 10 */
  27                          <0x0002b000 0x0002b000 0x001000>,      /* ap 11 */
  28                          <0x0002e000 0x0002e000 0x001000>,      /* ap 12 */
  29                          <0x0002f000 0x0002f000 0x001000>,      /* ap 13 */
  30                          <0x00030000 0x00030000 0x001000>,      /* ap 14 */
  31                          <0x00031000 0x00031000 0x001000>,      /* ap 15 */
  32                          <0x00032000 0x00032000 0x001000>,      /* ap 16 */
  33                          <0x00033000 0x00033000 0x001000>,      /* ap 17 */
  34                          <0x00038000 0x00038000 0x001000>,      /* ap 18 */
  35                          <0x00039000 0x00039000 0x001000>,      /* ap 19 */
  36                          <0x0003a000 0x0003a000 0x001000>,      /* ap 20 */
  37                          <0x0003b000 0x0003b000 0x001000>,      /* ap 21 */
  38                          <0x0003c000 0x0003c000 0x001000>,      /* ap 22 */
  39                          <0x0003d000 0x0003d000 0x001000>,      /* ap 23 */
  40                          <0x0003e000 0x0003e000 0x001000>,      /* ap 24 */
  41                          <0x0003f000 0x0003f000 0x001000>,      /* ap 25 */
  42                          <0x00080000 0x00080000 0x010000>,      /* ap 26 */
  43                          <0x00080000 0x00080000 0x001000>,      /* ap 27 */
  44                          <0x000a0000 0x000a0000 0x010000>,      /* ap 28 */
  45                          <0x000a0000 0x000a0000 0x001000>,      /* ap 29 */
  46                          <0x000c0000 0x000c0000 0x010000>,      /* ap 30 */
  47                          <0x000c0000 0x000c0000 0x001000>,      /* ap 31 */
  48                          <0x000f1000 0x000f1000 0x001000>,      /* ap 32 */
  49                          <0x000f2000 0x000f2000 0x001000>,      /* ap 33 */
  50
  51                          /* L3 to L4 ABE mapping */
  52                          <0x49000000 0x49000000 0x000400>,      /* ap 0 */
  53                          <0x49000400 0x49000400 0x000400>,      /* ap 1 */
  54                          <0x49022000 0x49022000 0x001000>,      /* ap 2 */
  55                          <0x49023000 0x49023000 0x001000>,      /* ap 3 */
  56                          <0x49024000 0x49024000 0x001000>,      /* ap 4 */
  57                          <0x49025000 0x49025000 0x001000>,      /* ap 5 */
  58                          <0x49026000 0x49026000 0x001000>,      /* ap 6 */
  59                          <0x49027000 0x49027000 0x001000>,      /* ap 7 */
  60                          <0x49028000 0x49028000 0x001000>,      /* ap 8 */
  61                          <0x49029000 0x49029000 0x001000>,      /* ap 9 */
  62                          <0x4902a000 0x4902a000 0x001000>,      /* ap 10 */
  63                          <0x4902b000 0x4902b000 0x001000>,      /* ap 11 */
  64                          <0x4902e000 0x4902e000 0x001000>,      /* ap 12 */
  65                          <0x4902f000 0x4902f000 0x001000>,      /* ap 13 */
  66                          <0x49030000 0x49030000 0x001000>,      /* ap 14 */
  67                          <0x49031000 0x49031000 0x001000>,      /* ap 15 */
  68                          <0x49032000 0x49032000 0x001000>,      /* ap 16 */
  69                          <0x49033000 0x49033000 0x001000>,      /* ap 17 */
  70                          <0x49038000 0x49038000 0x001000>,      /* ap 18 */
  71                          <0x49039000 0x49039000 0x001000>,      /* ap 19 */
  72                          <0x4903a000 0x4903a000 0x001000>,      /* ap 20 */
  73                          <0x4903b000 0x4903b000 0x001000>,      /* ap 21 */
  74                          <0x4903c000 0x4903c000 0x001000>,      /* ap 22 */
  75                          <0x4903d000 0x4903d000 0x001000>,      /* ap 23 */
  76                          <0x4903e000 0x4903e000 0x001000>,      /* ap 24 */
  77                          <0x4903f000 0x4903f000 0x001000>,      /* ap 25 */
  78                          <0x49080000 0x49080000 0x010000>,      /* ap 26 */
  79                          <0x49080000 0x49080000 0x001000>,      /* ap 27 */
  80                          <0x490a0000 0x490a0000 0x010000>,      /* ap 28 */
  81                          <0x490a0000 0x490a0000 0x001000>,      /* ap 29 */
  82                          <0x490c0000 0x490c0000 0x010000>,      /* ap 30 */
  83                          <0x490c0000 0x490c0000 0x001000>,      /* ap 31 */
  84                          <0x490f1000 0x490f1000 0x001000>,      /* ap 32 */
  85                          <0x490f2000 0x490f2000 0x001000>;      /* ap 33 */
  86
  87                 target-module@22000 {                   /* 0x40122000, ap 2 02.0 */
  88                         compatible = "ti,sysc-omap2", "ti,sysc";
  89                         reg = <0x2208c 0x4>;
  90                         reg-names = "sysc";
  91                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
  92                                          SYSC_OMAP2_ENAWAKEUP |
  93                                          SYSC_OMAP2_SOFTRESET)>;
  94                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  95                                         <SYSC_IDLE_NO>,
  96                                         <SYSC_IDLE_SMART>;
  97                         /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
  98                         clocks = <&abe_clkctrl OMAP5_MCBSP1_CLKCTRL 0>;
  99                         clock-names = "fck";
 100                         #address-cells = <1>;
 101                         #size-cells = <1>;
 102                         ranges = <0x0 0x22000 0x1000>,
 103                                  <0x49022000 0x49022000 0x1000>;
 104
 105                         mcbsp1: mcbsp@0 {
 106                                 compatible = "ti,omap4-mcbsp";
 107                                 reg = <0x0 0xff>, /* MPU private access */
 108                                       <0x49022000 0xff>; /* L3 Interconnect */
 109                                 reg-names = "mpu", "dma";
 110                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 111                                 interrupt-names = "common";
 112                                 ti,buffer-size = <128>;
 113                                 dmas = <&sdma 33>,
 114                                        <&sdma 34>;
 115                                 dma-names = "tx", "rx";
 116                                 status = "disabled";
 117                         };
 118                 };
 119
 120                 target-module@24000 {                   /* 0x40124000, ap 4 04.0 */
 121                         compatible = "ti,sysc-omap2", "ti,sysc";
 122                         reg = <0x2408c 0x4>;
 123                         reg-names = "sysc";
 124                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
 125                                          SYSC_OMAP2_ENAWAKEUP |
 126                                          SYSC_OMAP2_SOFTRESET)>;
 127                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 128                                         <SYSC_IDLE_NO>,
 129                                         <SYSC_IDLE_SMART>;
 130                         /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
 131                         clocks = <&abe_clkctrl OMAP5_MCBSP2_CLKCTRL 0>;
 132                         clock-names = "fck";
 133                         #address-cells = <1>;
 134                         #size-cells = <1>;
 135                         ranges = <0x0 0x24000 0x1000>,
 136                                  <0x49024000 0x49024000 0x1000>;
 137
 138                         mcbsp2: mcbsp@0 {
 139                                 compatible = "ti,omap4-mcbsp";
 140                                 reg = <0x0 0xff>, /* MPU private access */
 141                                       <0x49024000 0xff>; /* L3 Interconnect */
 142                                 reg-names = "mpu", "dma";
 143                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 144                                 interrupt-names = "common";
 145                                 ti,buffer-size = <128>;
 146                                 dmas = <&sdma 17>,
 147                                        <&sdma 18>;
 148                                 dma-names = "tx", "rx";
 149                                 status = "disabled";
 150                         };
 151                 };
 152
 153                 target-module@26000 {                   /* 0x40126000, ap 6 06.0 */
 154                         compatible = "ti,sysc-omap2", "ti,sysc";
 155                         reg = <0x2608c 0x4>;
 156                         reg-names = "sysc";
 157                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
 158                                          SYSC_OMAP2_ENAWAKEUP |
 159                                          SYSC_OMAP2_SOFTRESET)>;
 160                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 161                                         <SYSC_IDLE_NO>,
 162                                         <SYSC_IDLE_SMART>;
 163                         /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
 164                         clocks = <&abe_clkctrl OMAP5_MCBSP3_CLKCTRL 0>;
 165                         clock-names = "fck";
 166                         #address-cells = <1>;
 167                         #size-cells = <1>;
 168                         ranges = <0x0 0x26000 0x1000>,
 169                                  <0x49026000 0x49026000 0x1000>;
 170
 171                         mcbsp3: mcbsp@0 {
 172                                 compatible = "ti,omap4-mcbsp";
 173                                 reg = <0x0 0xff>, /* MPU private access */
 174                                       <0x49026000 0xff>; /* L3 Interconnect */
 175                                 reg-names = "mpu", "dma";
 176                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 177                                 interrupt-names = "common";
 178                                 ti,buffer-size = <128>;
 179                                 dmas = <&sdma 19>,
 180                                        <&sdma 20>;
 181                                 dma-names = "tx", "rx";
 182                                 status = "disabled";
 183                         };
 184                 };
 185
 186                 target-module@28000 {                   /* 0x40128000, ap 8 08.0 */
 187                         compatible = "ti,sysc";
 188                         status = "disabled";
 189                         #address-cells = <1>;
 190                         #size-cells = <1>;
 191                         ranges = <0x0 0x28000 0x1000>,
 192                                  <0x49028000 0x49028000 0x1000>;
 193                 };
 194
 195                 target-module@2a000 {                   /* 0x4012a000, ap 10 0a.0 */
 196                         compatible = "ti,sysc";
 197                         status = "disabled";
 198                         #address-cells = <1>;
 199                         #size-cells = <1>;
 200                         ranges = <0x0 0x2a000 0x1000>,
 201                                  <0x4902a000 0x4902a000 0x1000>;
 202                 };
 203
 204                 target-module@2e000 {                   /* 0x4012e000, ap 12 0c.0 */
 205                         compatible = "ti,sysc-omap4", "ti,sysc";
 206                         ti,hwmods = "dmic";
 207                         reg = <0x2e000 0x4>,
 208                               <0x2e010 0x4>;
 209                         reg-names = "rev", "sysc";
 210                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
 211                                          SYSC_OMAP4_SOFTRESET)>;
 212                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 213                                         <SYSC_IDLE_NO>,
 214                                         <SYSC_IDLE_SMART>,
 215                                         <SYSC_IDLE_SMART_WKUP>;
 216                         /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
 217                         clocks = <&abe_clkctrl OMAP5_DMIC_CLKCTRL 0>;
 218                         clock-names = "fck";
 219                         #address-cells = <1>;
 220                         #size-cells = <1>;
 221                         ranges = <0x0 0x2e000 0x1000>,
 222                                  <0x4902e000 0x4902e000 0x1000>;
 223
 224                         dmic: dmic@0 {
 225                                 compatible = "ti,omap4-dmic";
 226                                 reg = <0x0 0x7f>, /* MPU private access */
 227                                       <0x4902e000 0x7f>; /* L3 Interconnect */
 228                                 reg-names = "mpu", "dma";
 229                                 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 230                                 dmas = <&sdma 67>;
 231                                 dma-names = "up_link";
 232                                 status = "disabled";
 233                         };
 234                 };
 235
 236                 target-module@30000 {                   /* 0x40130000, ap 14 0e.0 */
 237                         compatible = "ti,sysc";
 238                         status = "disabled";
 239                         #address-cells = <1>;
 240                         #size-cells = <1>;
 241                         ranges = <0x0 0x30000 0x1000>,
 242                                  <0x49030000 0x49030000 0x1000>;
 243                 };
 244
 245                 mcpdm_module: target-module@32000 {     /* 0x40132000, ap 16 10.0 */
 246                         compatible = "ti,sysc-omap4", "ti,sysc";
 247                         ti,hwmods = "mcpdm";
 248                         reg = <0x32000 0x4>,
 249                               <0x32010 0x4>;
 250                         reg-names = "rev", "sysc";
 251                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
 252                                          SYSC_OMAP4_SOFTRESET)>;
 253                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 254                                         <SYSC_IDLE_NO>,
 255                                         <SYSC_IDLE_SMART>,
 256                                         <SYSC_IDLE_SMART_WKUP>;
 257                         /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
 258                         clocks = <&abe_clkctrl OMAP5_MCPDM_CLKCTRL 0>;
 259                         clock-names = "fck";
 260                         #address-cells = <1>;
 261                         #size-cells = <1>;
 262                         ranges = <0x0 0x32000 0x1000>,
 263                                  <0x49032000 0x49032000 0x1000>;
 264
 265                         /* Must be only enabled for boards with pdmclk wired */
 266                         status = "disabled";
 267
 268                         mcpdm: mcpdm@0 {
 269                                 compatible = "ti,omap4-mcpdm";
 270                                 reg = <0x0 0x7f>, /* MPU private access */
 271                                       <0x49032000 0x7f>; /* L3 Interconnect */
 272                                 reg-names = "mpu", "dma";
 273                                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 274                                 dmas = <&sdma 65>,
 275                                        <&sdma 66>;
 276                                 dma-names = "up_link", "dn_link";
 277                         };
 278                 };
 279
 280                 target-module@38000 {                   /* 0x40138000, ap 18 12.0 */
 281                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
 282                         ti,hwmods = "timer5";
 283                         reg = <0x38000 0x4>,
 284                               <0x38010 0x4>;
 285                         reg-names = "rev", "sysc";
 286                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
 287                                          SYSC_OMAP4_SOFTRESET)>;
 288                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 289                                         <SYSC_IDLE_NO>,
 290                                         <SYSC_IDLE_SMART>,
 291                                         <SYSC_IDLE_SMART_WKUP>;
 292                         /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
 293                         clocks = <&abe_clkctrl OMAP5_TIMER5_CLKCTRL 0>;
 294                         clock-names = "fck";
 295                         #address-cells = <1>;
 296                         #size-cells = <1>;
 297                         ranges = <0x0 0x38000 0x1000>,
 298                                  <0x49038000 0x49038000 0x1000>;
 299
 300                         timer5: timer@0 {
 301                                 compatible = "ti,omap5430-timer";
 302                                 reg = <0x0 0x80>,
 303                                       <0x49038000 0x80>;
 304                                 clocks = <&abe_clkctrl OMAP5_TIMER5_CLKCTRL 24>;
 305                                 clock-names = "fck";
 306                                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 307                                 ti,timer-dsp;
 308                                 ti,timer-pwm;
 309                         };
 310                 };
 311
 312                 target-module@3a000 {                   /* 0x4013a000, ap 20 14.0 */
 313                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
 314                         ti,hwmods = "timer6";
 315                         reg = <0x3a000 0x4>,
 316                               <0x3a010 0x4>;
 317                         reg-names = "rev", "sysc";
 318                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
 319                                          SYSC_OMAP4_SOFTRESET)>;
 320                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 321                                         <SYSC_IDLE_NO>,
 322                                         <SYSC_IDLE_SMART>,
 323                                         <SYSC_IDLE_SMART_WKUP>;
 324                         /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
 325                         clocks = <&abe_clkctrl OMAP5_TIMER6_CLKCTRL 0>;
 326                         clock-names = "fck";
 327                         #address-cells = <1>;
 328                         #size-cells = <1>;
 329                         ranges = <0x0 0x3a000 0x1000>,
 330                                  <0x4903a000 0x4903a000 0x1000>;
 331
 332                         timer6: timer@0 {
 333                                 compatible = "ti,omap5430-timer";
 334                                 reg = <0x0 0x80>,
 335                                       <0x4903a000 0x80>;
 336                                 clocks = <&abe_clkctrl OMAP5_TIMER6_CLKCTRL 24>;
 337                                 clock-names = "fck";
 338                                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 339                                 ti,timer-dsp;
 340                                 ti,timer-pwm;
 341                         };
 342                 };
 343
 344                 target-module@3c000 {                   /* 0x4013c000, ap 22 16.0 */
 345                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
 346                         ti,hwmods = "timer7";
 347                         reg = <0x3c000 0x4>,
 348                               <0x3c010 0x4>;
 349                         reg-names = "rev", "sysc";
 350                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
 351                                          SYSC_OMAP4_SOFTRESET)>;
 352                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 353                                         <SYSC_IDLE_NO>,
 354                                         <SYSC_IDLE_SMART>,
 355                                         <SYSC_IDLE_SMART_WKUP>;
 356                         /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
 357                         clocks = <&abe_clkctrl OMAP5_TIMER7_CLKCTRL 0>;
 358                         clock-names = "fck";
 359                         #address-cells = <1>;
 360                         #size-cells = <1>;
 361                         ranges = <0x0 0x3c000 0x1000>,
 362                                  <0x4903c000 0x4903c000 0x1000>;
 363
 364                         timer7: timer@0 {
 365                                 compatible = "ti,omap5430-timer";
 366                                 reg = <0x0 0x80>,
 367                                       <0x4903c000 0x80>;
 368                                 clocks = <&abe_clkctrl OMAP5_TIMER7_CLKCTRL 24>;
 369                                 clock-names = "fck";
 370                                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 371                                 ti,timer-dsp;
 372                         };
 373                 };
 374
 375                 target-module@3e000 {                   /* 0x4013e000, ap 24 18.0 */
 376                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
 377                         ti,hwmods = "timer8";
 378                         reg = <0x3e000 0x4>,
 379                               <0x3e010 0x4>;
 380                         reg-names = "rev", "sysc";
 381                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
 382                                          SYSC_OMAP4_SOFTRESET)>;
 383                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 384                                         <SYSC_IDLE_NO>,
 385                                         <SYSC_IDLE_SMART>,
 386                                         <SYSC_IDLE_SMART_WKUP>;
 387                         /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
 388                         clocks = <&abe_clkctrl OMAP5_TIMER8_CLKCTRL 0>;
 389                         clock-names = "fck";
 390                         #address-cells = <1>;
 391                         #size-cells = <1>;
 392                         ranges = <0x0 0x3e000 0x1000>,
 393                                  <0x4903e000 0x4903e000 0x1000>;
 394
 395                         timer8: timer@0 {
 396                                 compatible = "ti,omap5430-timer";
 397                                 reg = <0x0 0x80>,
 398                                       <0x4903e000 0x80>;
 399                                 clocks = <&abe_clkctrl OMAP5_TIMER8_CLKCTRL 24>;
 400                                 clock-names = "fck";
 401                                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 402                                 ti,timer-dsp;
 403                                 ti,timer-pwm;
 404                         };
 405                 };
 406
 407                 target-module@80000 {                   /* 0x40180000, ap 26 1a.0 */
 408                         compatible = "ti,sysc";
 409                         status = "disabled";
 410                         #address-cells = <1>;
 411                         #size-cells = <1>;
 412                         ranges = <0x0 0x80000 0x10000>,
 413                                  <0x49080000 0x49080000 0x10000>;
 414                 };
 415
 416                 target-module@a0000 {                   /* 0x401a0000, ap 28 1c.0 */
 417                         compatible = "ti,sysc";
 418                         status = "disabled";
 419                         #address-cells = <1>;
 420                         #size-cells = <1>;
 421                         ranges = <0x0 0xa0000 0x10000>,
 422                                  <0x490a0000 0x490a0000 0x10000>;
 423                 };
 424
 425                 target-module@c0000 {                   /* 0x401c0000, ap 30 1e.0 */
 426                         compatible = "ti,sysc";
 427                         status = "disabled";
 428                         #address-cells = <1>;
 429                         #size-cells = <1>;
 430                         ranges = <0x0 0xc0000 0x10000>,
 431                                  <0x490c0000 0x490c0000 0x10000>;
 432                 };
 433
 434                 target-module@f1000 {                   /* 0x401f1000, ap 32 20.0 */
 435                         compatible = "ti,sysc";
 436                         status = "disabled";
 437                         #address-cells = <1>;
 438                         #size-cells = <1>;
 439                         ranges = <0x0 0xf1000 0x1000>,
 440                                  <0x490f1000 0x490f1000 0x1000>;
 441                 };
 442         };
 443 };
 444