arch/arm/boot/dts/mt7623.dtsi

   1 /*
   2  * Copyright (c) 2017 MediaTek Inc.
   3  * Author: John Crispin <john@phrozen.org>
   4  *         Sean Wang <sean.wang@mediatek.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <dt-bindings/interrupt-controller/irq.h>
  17 #include <dt-bindings/interrupt-controller/arm-gic.h>
  18 #include <dt-bindings/clock/mt2701-clk.h>
  19 #include <dt-bindings/pinctrl/mt7623-pinfunc.h>
  20 #include <dt-bindings/power/mt2701-power.h>
  21 #include <dt-bindings/gpio/gpio.h>
  22 #include <dt-bindings/phy/phy.h>
  23 #include <dt-bindings/reset/mt2701-resets.h>
  24 #include <dt-bindings/thermal/thermal.h>
  25 #include "skeleton64.dtsi"
  26
  27 / {
  28         compatible = "mediatek,mt7623";
  29         interrupt-parent = <&sysirq>;
  30
  31         cpu_opp_table: opp_table {
  32                 compatible = "operating-points-v2";
  33                 opp-shared;
  34
  35                 opp-98000000 {
  36                         opp-hz = /bits/ 64 <98000000>;
  37                         opp-microvolt = <1050000>;
  38                 };
  39
  40                 opp-198000000 {
  41                         opp-hz = /bits/ 64 <198000000>;
  42                         opp-microvolt = <1050000>;
  43                 };
  44
  45                 opp-398000000 {
  46                         opp-hz = /bits/ 64 <398000000>;
  47                         opp-microvolt = <1050000>;
  48                 };
  49
  50                 opp-598000000 {
  51                         opp-hz = /bits/ 64 <598000000>;
  52                         opp-microvolt = <1050000>;
  53                 };
  54
  55                 opp-747500000 {
  56                         opp-hz = /bits/ 64 <747500000>;
  57                         opp-microvolt = <1050000>;
  58                 };
  59
  60                 opp-1040000000 {
  61                         opp-hz = /bits/ 64 <1040000000>;
  62                         opp-microvolt = <1150000>;
  63                 };
  64
  65                 opp-1196000000 {
  66                         opp-hz = /bits/ 64 <1196000000>;
  67                         opp-microvolt = <1200000>;
  68                 };
  69
  70                 opp-1300000000 {
  71                         opp-hz = /bits/ 64 <1300000000>;
  72                         opp-microvolt = <1300000>;
  73                 };
  74         };
  75
  76         cpus {
  77                 #address-cells = <1>;
  78                 #size-cells = <0>;
  79                 enable-method = "mediatek,mt6589-smp";
  80
  81                 cpu0: cpu@0 {
  82                         device_type = "cpu";
  83                         compatible = "arm,cortex-a7";
  84                         reg = <0x0>;
  85                         clocks = <&infracfg CLK_INFRA_CPUSEL>,
  86                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
  87                         clock-names = "cpu", "intermediate";
  88                         operating-points-v2 = <&cpu_opp_table>;
  89                         #cooling-cells = <2>;
  90                         clock-frequency = <1300000000>;
  91                 };
  92
  93                 cpu1: cpu@1 {
  94                         device_type = "cpu";
  95                         compatible = "arm,cortex-a7";
  96                         reg = <0x1>;
  97                         operating-points-v2 = <&cpu_opp_table>;
  98                         clock-frequency = <1300000000>;
  99                 };
 100
 101                 cpu2: cpu@2 {
 102                         device_type = "cpu";
 103                         compatible = "arm,cortex-a7";
 104                         reg = <0x2>;
 105                         operating-points-v2 = <&cpu_opp_table>;
 106                         clock-frequency = <1300000000>;
 107                 };
 108
 109                 cpu3: cpu@3 {
 110                         device_type = "cpu";
 111                         compatible = "arm,cortex-a7";
 112                         reg = <0x3>;
 113                         operating-points-v2 = <&cpu_opp_table>;
 114                         clock-frequency = <1300000000>;
 115                 };
 116         };
 117
 118         system_clk: dummy13m {
 119                 compatible = "fixed-clock";
 120                 clock-frequency = <13000000>;
 121                 #clock-cells = <0>;
 122         };
 123
 124         rtc32k: oscillator@1 {
 125                 compatible = "fixed-clock";
 126                 #clock-cells = <0>;
 127                 clock-frequency = <32000>;
 128                 clock-output-names = "rtc32k";
 129         };
 130
 131         clk26m: oscillator@0 {
 132                 compatible = "fixed-clock";
 133                 #clock-cells = <0>;
 134                 clock-frequency = <26000000>;
 135                 clock-output-names = "clk26m";
 136         };
 137
 138         thermal-zones {
 139                         cpu_thermal: cpu_thermal {
 140                                 polling-delay-passive = <1000>;
 141                                 polling-delay = <1000>;
 142
 143                                 thermal-sensors = <&thermal 0>;
 144
 145                                 trips {
 146                                         cpu_passive: cpu_passive {
 147                                                 temperature = <47000>;
 148                                                 hysteresis = <2000>;
 149                                                 type = "passive";
 150                                         };
 151
 152                                         cpu_active: cpu_active {
 153                                                 temperature = <67000>;
 154                                                 hysteresis = <2000>;
 155                                                 type = "active";
 156                                         };
 157
 158                                         cpu_hot: cpu_hot {
 159                                                 temperature = <87000>;
 160                                                 hysteresis = <2000>;
 161                                                 type = "hot";
 162                                         };
 163
 164                                         cpu_crit {
 165                                                 temperature = <107000>;
 166                                                 hysteresis = <2000>;
 167                                                 type = "critical";
 168                                         };
 169                                 };
 170
 171                         cooling-maps {
 172                                 map0 {
 173                                         trip = <&cpu_passive>;
 174                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 175                                 };
 176
 177                                 map1 {
 178                                         trip = <&cpu_active>;
 179                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 180                                 };
 181
 182                                 map2 {
 183                                         trip = <&cpu_hot>;
 184                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 185                                 };
 186                         };
 187                 };
 188         };
 189
 190         timer {
 191                 compatible = "arm,armv7-timer";
 192                 interrupt-parent = <&gic>;
 193                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 194                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 195                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 196                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 197                 clock-frequency = <13000000>;
 198                 arm,cpu-registers-not-fw-configured;
 199         };
 200
 201         topckgen: syscon@10000000 {
 202                 compatible = "mediatek,mt7623-topckgen",
 203                              "mediatek,mt2701-topckgen",
 204                              "syscon";
 205                 reg = <0 0x10000000 0 0x1000>;
 206                 #clock-cells = <1>;
 207         };
 208
 209         infracfg: syscon@10001000 {
 210                 compatible = "mediatek,mt7623-infracfg",
 211                              "mediatek,mt2701-infracfg",
 212                              "syscon";
 213                 reg = <0 0x10001000 0 0x1000>;
 214                 #clock-cells = <1>;
 215                 #reset-cells = <1>;
 216         };
 217
 218         pericfg: syscon@10003000 {
 219                 compatible =  "mediatek,mt7623-pericfg",
 220                               "mediatek,mt2701-pericfg",
 221                               "syscon";
 222                 reg = <0 0x10003000 0 0x1000>;
 223                 #clock-cells = <1>;
 224                 #reset-cells = <1>;
 225         };
 226
 227         pio: pinctrl@10005000 {
 228                 compatible = "mediatek,mt7623-pinctrl";
 229                 reg = <0 0x1000b000 0 0x1000>;
 230                 mediatek,pctl-regmap = <&syscfg_pctl_a>;
 231                 pins-are-numbered;
 232                 gpio-controller;
 233                 #gpio-cells = <2>;
 234                 interrupt-controller;
 235                 interrupt-parent = <&gic>;
 236                 #interrupt-cells = <2>;
 237                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 238                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 239         };
 240
 241         syscfg_pctl_a: syscfg@10005000 {
 242                 compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon";
 243                 reg = <0 0x10005000 0 0x1000>;
 244         };
 245
 246         scpsys: scpsys@10006000 {
 247                 compatible = "mediatek,mt7623-scpsys",
 248                              "mediatek,mt2701-scpsys",
 249                              "syscon";
 250                 #power-domain-cells = <1>;
 251                 reg = <0 0x10006000 0 0x1000>;
 252                 infracfg = <&infracfg>;
 253                 clocks = <&topckgen CLK_TOP_MM_SEL>,
 254                          <&topckgen CLK_TOP_MFG_SEL>,
 255                          <&topckgen CLK_TOP_ETHIF_SEL>;
 256                 clock-names = "mm", "mfg", "ethif";
 257         };
 258
 259         watchdog: watchdog@10007000 {
 260                 compatible = "mediatek,mt7623-wdt",
 261                              "mediatek,mt6589-wdt";
 262                 reg = <0 0x10007000 0 0x100>;
 263         };
 264
 265         timer: timer@10008000 {
 266                 compatible = "mediatek,mt7623-timer",
 267                              "mediatek,mt6577-timer";
 268                 reg = <0 0x10008000 0 0x80>;
 269                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
 270                 clocks = <&system_clk>, <&rtc32k>;
 271                 clock-names = "system-clk", "rtc-clk";
 272         };
 273
 274         pwrap: pwrap@1000d000 {
 275                 compatible = "mediatek,mt7623-pwrap",
 276                              "mediatek,mt2701-pwrap";
 277                 reg = <0 0x1000d000 0 0x1000>;
 278                 reg-names = "pwrap";
 279                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 280                 resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>;
 281                 reset-names = "pwrap";
 282                 clocks = <&infracfg CLK_INFRA_PMICSPI>,
 283                          <&infracfg CLK_INFRA_PMICWRAP>;
 284                 clock-names = "spi", "wrap";
 285         };
 286
 287         cir: cir@10013000 {
 288                 compatible = "mediatek,mt7623-cir";
 289                 reg = <0 0x10013000 0 0x1000>;
 290                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
 291                 clocks = <&infracfg CLK_INFRA_IRRX>;
 292                 clock-names = "clk";
 293                 status = "disabled";
 294         };
 295
 296         sysirq: interrupt-controller@10200100 {
 297                 compatible = "mediatek,mt7623-sysirq",
 298                              "mediatek,mt6577-sysirq";
 299                 interrupt-controller;
 300                 #interrupt-cells = <3>;
 301                 interrupt-parent = <&gic>;
 302                 reg = <0 0x10200100 0 0x1c>;
 303         };
 304
 305         efuse: efuse@10206000 {
 306                 compatible = "mediatek,mt7623-efuse",
 307                              "mediatek,mt8173-efuse";
 308                 reg = <0 0x10206000 0 0x1000>;
 309                 #address-cells = <1>;
 310                 #size-cells = <1>;
 311                 thermal_calibration_data: calib@424 {
 312                         reg = <0x424 0xc>;
 313                 };
 314         };
 315
 316         apmixedsys: syscon@10209000 {
 317                 compatible = "mediatek,mt7623-apmixedsys",
 318                              "mediatek,mt2701-apmixedsys",
 319                              "syscon";
 320                 reg = <0 0x10209000 0 0x1000>;
 321                 #clock-cells = <1>;
 322         };
 323
 324         rng: rng@1020f000 {
 325                 compatible = "mediatek,mt7623-rng";
 326                 reg = <0 0x1020f000 0 0x1000>;
 327                 clocks = <&infracfg CLK_INFRA_TRNG>;
 328                 clock-names = "rng";
 329         };
 330
 331         gic: interrupt-controller@10211000 {
 332                 compatible = "arm,cortex-a7-gic";
 333                 interrupt-controller;
 334                 #interrupt-cells = <3>;
 335                 interrupt-parent = <&gic>;
 336                 reg = <0 0x10211000 0 0x1000>,
 337                       <0 0x10212000 0 0x2000>,
 338                       <0 0x10214000 0 0x2000>,
 339                       <0 0x10216000 0 0x2000>;
 340         };
 341
 342         auxadc: adc@11001000 {
 343                 compatible = "mediatek,mt7623-auxadc",
 344                              "mediatek,mt2701-auxadc";
 345                 reg = <0 0x11001000 0 0x1000>;
 346                 clocks = <&pericfg CLK_PERI_AUXADC>;
 347                 clock-names = "main";
 348                 #io-channel-cells = <1>;
 349         };
 350
 351         uart0: serial@11002000 {
 352                 compatible = "mediatek,mt7623-uart",
 353                              "mediatek,mt6577-uart";
 354                 reg = <0 0x11002000 0 0x400>;
 355                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
 356                 clocks = <&pericfg CLK_PERI_UART0_SEL>,
 357                          <&pericfg CLK_PERI_UART0>;
 358                 clock-names = "baud", "bus";
 359                 status = "disabled";
 360         };
 361
 362         uart1: serial@11003000 {
 363                 compatible = "mediatek,mt7623-uart",
 364                              "mediatek,mt6577-uart";
 365                 reg = <0 0x11003000 0 0x400>;
 366                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
 367                 clocks = <&pericfg CLK_PERI_UART1_SEL>,
 368                          <&pericfg CLK_PERI_UART1>;
 369                 clock-names = "baud", "bus";
 370                 status = "disabled";
 371         };
 372
 373         uart2: serial@11004000 {
 374                 compatible = "mediatek,mt7623-uart",
 375                              "mediatek,mt6577-uart";
 376                 reg = <0 0x11004000 0 0x400>;
 377                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
 378                 clocks = <&pericfg CLK_PERI_UART2_SEL>,
 379                          <&pericfg CLK_PERI_UART2>;
 380                 clock-names = "baud", "bus";
 381                 status = "disabled";
 382         };
 383
 384         uart3: serial@11005000 {
 385                 compatible = "mediatek,mt7623-uart",
 386                              "mediatek,mt6577-uart";
 387                 reg = <0 0x11005000 0 0x400>;
 388                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
 389                 clocks = <&pericfg CLK_PERI_UART3_SEL>,
 390                          <&pericfg CLK_PERI_UART3>;
 391                 clock-names = "baud", "bus";
 392                 status = "disabled";
 393         };
 394
 395         pwm: pwm@11006000 {
 396                 compatible = "mediatek,mt7623-pwm";
 397                 reg = <0 0x11006000 0 0x1000>;
 398                 #pwm-cells = <2>;
 399                 clocks = <&topckgen CLK_TOP_PWM_SEL>,
 400                          <&pericfg CLK_PERI_PWM>,
 401                          <&pericfg CLK_PERI_PWM1>,
 402                          <&pericfg CLK_PERI_PWM2>,
 403                          <&pericfg CLK_PERI_PWM3>,
 404                          <&pericfg CLK_PERI_PWM4>,
 405                          <&pericfg CLK_PERI_PWM5>;
 406                 clock-names = "top", "main", "pwm1", "pwm2",
 407                               "pwm3", "pwm4", "pwm5";
 408                 status = "disabled";
 409         };
 410
 411         i2c0: i2c@11007000 {
 412                 compatible = "mediatek,mt7623-i2c",
 413                              "mediatek,mt6577-i2c";
 414                 reg = <0 0x11007000 0 0x70>,
 415                       <0 0x11000200 0 0x80>;
 416                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
 417                 clock-div = <16>;
 418                 clocks = <&pericfg CLK_PERI_I2C0>,
 419                          <&pericfg CLK_PERI_AP_DMA>;
 420                 clock-names = "main", "dma";
 421                 #address-cells = <1>;
 422                 #size-cells = <0>;
 423                 status = "disabled";
 424         };
 425
 426         i2c1: i2c@11008000 {
 427                 compatible = "mediatek,mt7623-i2c",
 428                              "mediatek,mt6577-i2c";
 429                 reg = <0 0x11008000 0 0x70>,
 430                       <0 0x11000280 0 0x80>;
 431                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
 432                 clock-div = <16>;
 433                 clocks = <&pericfg CLK_PERI_I2C1>,
 434                          <&pericfg CLK_PERI_AP_DMA>;
 435                 clock-names = "main", "dma";
 436                 #address-cells = <1>;
 437                 #size-cells = <0>;
 438                 status = "disabled";
 439         };
 440
 441         i2c2: i2c@11009000 {
 442                 compatible = "mediatek,mt7623-i2c",
 443                              "mediatek,mt6577-i2c";
 444                 reg = <0 0x11009000 0 0x70>,
 445                       <0 0x11000300 0 0x80>;
 446                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
 447                 clock-div = <16>;
 448                 clocks = <&pericfg CLK_PERI_I2C2>,
 449                          <&pericfg CLK_PERI_AP_DMA>;
 450                 clock-names = "main", "dma";
 451                 #address-cells = <1>;
 452                 #size-cells = <0>;
 453                 status = "disabled";
 454         };
 455
 456         spi0: spi@1100a000 {
 457                 compatible = "mediatek,mt7623-spi",
 458                              "mediatek,mt2701-spi";
 459                 #address-cells = <1>;
 460                 #size-cells = <0>;
 461                 reg = <0 0x1100a000 0 0x100>;
 462                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
 463                 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 464                          <&topckgen CLK_TOP_SPI0_SEL>,
 465                          <&pericfg CLK_PERI_SPI0>;
 466                 clock-names = "parent-clk", "sel-clk", "spi-clk";
 467                 status = "disabled";
 468         };
 469
 470         thermal: thermal@1100b000 {
 471                 #thermal-sensor-cells = <1>;
 472                 compatible = "mediatek,mt7623-thermal",
 473                              "mediatek,mt2701-thermal";
 474                 reg = <0 0x1100b000 0 0x1000>;
 475                 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
 476                 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
 477                 clock-names = "therm", "auxadc";
 478                 resets = <&pericfg MT2701_PERI_THERM_SW_RST>;
 479                 reset-names = "therm";
 480                 mediatek,auxadc = <&auxadc>;
 481                 mediatek,apmixedsys = <&apmixedsys>;
 482                 nvmem-cells = <&thermal_calibration_data>;
 483                 nvmem-cell-names = "calibration-data";
 484         };
 485
 486         nandc: nfi@1100d000 {
 487                 compatible = "mediatek,mt7623-nfc",
 488                              "mediatek,mt2701-nfc";
 489                 reg = <0 0x1100d000 0 0x1000>;
 490                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
 491                 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
 492                 clocks = <&pericfg CLK_PERI_NFI>,
 493                          <&pericfg CLK_PERI_NFI_PAD>;
 494                 clock-names = "nfi_clk", "pad_clk";
 495                 status = "disabled";
 496                 ecc-engine = <&bch>;
 497                 #address-cells = <1>;
 498                 #size-cells = <0>;
 499         };
 500
 501         bch: ecc@1100e000 {
 502                 compatible = "mediatek,mt7623-ecc",
 503                              "mediatek,mt2701-ecc";
 504                 reg = <0 0x1100e000 0 0x1000>;
 505                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
 506                 clocks = <&pericfg CLK_PERI_NFI_ECC>;
 507                 clock-names = "nfiecc_clk";
 508                 status = "disabled";
 509         };
 510
 511         spi1: spi@11016000 {
 512                 compatible = "mediatek,mt7623-spi",
 513                              "mediatek,mt2701-spi";
 514                 #address-cells = <1>;
 515                 #size-cells = <0>;
 516                 reg = <0 0x11016000 0 0x100>;
 517                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
 518                 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 519                          <&topckgen CLK_TOP_SPI1_SEL>,
 520                          <&pericfg CLK_PERI_SPI1>;
 521                 clock-names = "parent-clk", "sel-clk", "spi-clk";
 522                 status = "disabled";
 523         };
 524
 525         spi2: spi@11017000 {
 526                 compatible = "mediatek,mt7623-spi",
 527                              "mediatek,mt2701-spi";
 528                 #address-cells = <1>;
 529                 #size-cells = <0>;
 530                 reg = <0 0x11017000 0 0x1000>;
 531                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
 532                 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 533                          <&topckgen CLK_TOP_SPI2_SEL>,
 534                          <&pericfg CLK_PERI_SPI2>;
 535                 clock-names = "parent-clk", "sel-clk", "spi-clk";
 536                 status = "disabled";
 537         };
 538
 539         afe: audio-controller@11220000 {
 540                 compatible = "mediatek,mt7623-audio",
 541                              "mediatek,mt2701-audio";
 542                 reg = <0 0x11220000 0 0x2000>,
 543                       <0 0x112a0000 0 0x20000>;
 544                 interrupts =  <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
 545                               <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
 546                 interrupt-names = "afe", "asys";
 547                 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
 548
 549                 clocks = <&infracfg CLK_INFRA_AUDIO>,
 550                          <&topckgen CLK_TOP_AUD_MUX1_SEL>,
 551                          <&topckgen CLK_TOP_AUD_MUX2_SEL>,
 552                          <&topckgen CLK_TOP_AUD_MUX1_DIV>,
 553                          <&topckgen CLK_TOP_AUD_MUX2_DIV>,
 554                          <&topckgen CLK_TOP_AUD_48K_TIMING>,
 555                          <&topckgen CLK_TOP_AUD_44K_TIMING>,
 556                          <&topckgen CLK_TOP_AUDPLL_MUX_SEL>,
 557                          <&topckgen CLK_TOP_APLL_SEL>,
 558                          <&topckgen CLK_TOP_AUD1PLL_98M>,
 559                          <&topckgen CLK_TOP_AUD2PLL_90M>,
 560                          <&topckgen CLK_TOP_HADDS2PLL_98M>,
 561                          <&topckgen CLK_TOP_HADDS2PLL_294M>,
 562                          <&topckgen CLK_TOP_AUDPLL>,
 563                          <&topckgen CLK_TOP_AUDPLL_D4>,
 564                          <&topckgen CLK_TOP_AUDPLL_D8>,
 565                          <&topckgen CLK_TOP_AUDPLL_D16>,
 566                          <&topckgen CLK_TOP_AUDPLL_D24>,
 567                          <&topckgen CLK_TOP_AUDINTBUS_SEL>,
 568                          <&clk26m>,
 569                          <&topckgen CLK_TOP_SYSPLL1_D4>,
 570                          <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
 571                          <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
 572                          <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
 573                          <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
 574                          <&topckgen CLK_TOP_AUD_K5_SRC_SEL>,
 575                          <&topckgen CLK_TOP_AUD_K6_SRC_SEL>,
 576                          <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
 577                          <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
 578                          <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
 579                          <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
 580                          <&topckgen CLK_TOP_AUD_K5_SRC_DIV>,
 581                          <&topckgen CLK_TOP_AUD_K6_SRC_DIV>,
 582                          <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
 583                          <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
 584                          <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
 585                          <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
 586                          <&topckgen CLK_TOP_AUD_I2S5_MCLK>,
 587                          <&topckgen CLK_TOP_AUD_I2S6_MCLK>,
 588                          <&topckgen CLK_TOP_ASM_M_SEL>,
 589                          <&topckgen CLK_TOP_ASM_H_SEL>,
 590                          <&topckgen CLK_TOP_UNIVPLL2_D4>,
 591                          <&topckgen CLK_TOP_UNIVPLL2_D2>,
 592                          <&topckgen CLK_TOP_SYSPLL_D5>;
 593
 594                 clock-names = "infra_sys_audio_clk",
 595                          "top_audio_mux1_sel",
 596                          "top_audio_mux2_sel",
 597                          "top_audio_mux1_div",
 598                          "top_audio_mux2_div",
 599                          "top_audio_48k_timing",
 600                          "top_audio_44k_timing",
 601                          "top_audpll_mux_sel",
 602                          "top_apll_sel",
 603                          "top_aud1_pll_98M",
 604                          "top_aud2_pll_90M",
 605                          "top_hadds2_pll_98M",
 606                          "top_hadds2_pll_294M",
 607                          "top_audpll",
 608                          "top_audpll_d4",
 609                          "top_audpll_d8",
 610                          "top_audpll_d16",
 611                          "top_audpll_d24",
 612                          "top_audintbus_sel",
 613                          "clk_26m",
 614                          "top_syspll1_d4",
 615                          "top_aud_k1_src_sel",
 616                          "top_aud_k2_src_sel",
 617                          "top_aud_k3_src_sel",
 618                          "top_aud_k4_src_sel",
 619                          "top_aud_k5_src_sel",
 620                          "top_aud_k6_src_sel",
 621                          "top_aud_k1_src_div",
 622                          "top_aud_k2_src_div",
 623                          "top_aud_k3_src_div",
 624                          "top_aud_k4_src_div",
 625                          "top_aud_k5_src_div",
 626                          "top_aud_k6_src_div",
 627                          "top_aud_i2s1_mclk",
 628                          "top_aud_i2s2_mclk",
 629                          "top_aud_i2s3_mclk",
 630                          "top_aud_i2s4_mclk",
 631                          "top_aud_i2s5_mclk",
 632                          "top_aud_i2s6_mclk",
 633                          "top_asm_m_sel",
 634                          "top_asm_h_sel",
 635                          "top_univpll2_d4",
 636                          "top_univpll2_d2",
 637                          "top_syspll_d5";
 638         };
 639
 640         mmc0: mmc@11230000 {
 641                 compatible = "mediatek,mt7623-mmc",
 642                              "mediatek,mt2701-mmc";
 643                 reg = <0 0x11230000 0 0x1000>;
 644                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
 645                 clocks = <&pericfg CLK_PERI_MSDC30_0>,
 646                          <&topckgen CLK_TOP_MSDC30_0_SEL>;
 647                 clock-names = "source", "hclk";
 648                 status = "disabled";
 649         };
 650
 651         mmc1: mmc@11240000 {
 652                 compatible = "mediatek,mt7623-mmc",
 653                              "mediatek,mt2701-mmc";
 654                 reg = <0 0x11240000 0 0x1000>;
 655                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_LOW>;
 656                 clocks = <&pericfg CLK_PERI_MSDC30_1>,
 657                          <&topckgen CLK_TOP_MSDC30_1_SEL>;
 658                 clock-names = "source", "hclk";
 659                 status = "disabled";
 660         };
 661
 662         hifsys: syscon@1a000000 {
 663                 compatible = "mediatek,mt7623-hifsys",
 664                              "mediatek,mt2701-hifsys",
 665                              "syscon";
 666                 reg = <0 0x1a000000 0 0x1000>;
 667                 #clock-cells = <1>;
 668                 #reset-cells = <1>;
 669         };
 670
 671         usb1: usb@1a1c0000 {
 672                 compatible = "mediatek,mt7623-xhci",
 673                              "mediatek,mt8173-xhci";
 674                 reg = <0 0x1a1c0000 0 0x1000>,
 675                       <0 0x1a1c4700 0 0x0100>;
 676                 reg-names = "mac", "ippc";
 677                 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
 678                 clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
 679                          <&topckgen CLK_TOP_ETHIF_SEL>;
 680                 clock-names = "sys_ck", "ref_ck";
 681                 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
 682                 phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
 683                 status = "disabled";
 684         };
 685
 686         u3phy1: usb-phy@1a1c4000 {
 687                 compatible = "mediatek,mt7623-u3phy",
 688                              "mediatek,mt2701-u3phy";
 689                 reg = <0 0x1a1c4000 0 0x0700>;
 690                 #address-cells = <2>;
 691                 #size-cells = <2>;
 692                 ranges;
 693                 status = "disabled";
 694
 695                 u2port0: usb-phy@1a1c4800 {
 696                         reg = <0 0x1a1c4800 0 0x0100>;
 697                         clocks = <&topckgen CLK_TOP_USB_PHY48M>;
 698                         clock-names = "ref";
 699                         #phy-cells = <1>;
 700                         status = "okay";
 701                 };
 702
 703                 u3port0: usb-phy@1a1c4900 {
 704                         reg = <0 0x1a1c4900 0 0x0700>;
 705                         clocks = <&clk26m>;
 706                         clock-names = "ref";
 707                         #phy-cells = <1>;
 708                         status = "okay";
 709                 };
 710         };
 711
 712         usb2: usb@1a240000 {
 713                 compatible = "mediatek,mt7623-xhci",
 714                              "mediatek,mt8173-xhci";
 715                 reg = <0 0x1a240000 0 0x1000>,
 716                       <0 0x1a244700 0 0x0100>;
 717                 reg-names = "mac", "ippc";
 718                 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
 719                 clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
 720                          <&topckgen CLK_TOP_ETHIF_SEL>;
 721                 clock-names = "sys_ck", "ref_ck";
 722                 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
 723                 phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
 724                 status = "disabled";
 725         };
 726
 727         u3phy2: usb-phy@1a244000 {
 728                 compatible = "mediatek,mt7623-u3phy",
 729                              "mediatek,mt2701-u3phy";
 730                 reg = <0 0x1a244000 0 0x0700>;
 731                 #address-cells = <2>;
 732                 #size-cells = <2>;
 733                 ranges;
 734                 status = "disabled";
 735
 736                 u2port1: usb-phy@1a244800 {
 737                         reg = <0 0x1a244800 0 0x0100>;
 738                         clocks = <&topckgen CLK_TOP_USB_PHY48M>;
 739                         clock-names = "ref";
 740                         #phy-cells = <1>;
 741                         status = "okay";
 742                 };
 743
 744                 u3port1: usb-phy@1a244900 {
 745                         reg = <0 0x1a244900 0 0x0700>;
 746                         clocks = <&clk26m>;
 747                         clock-names = "ref";
 748                         #phy-cells = <1>;
 749                         status = "okay";
 750                 };
 751         };
 752
 753         ethsys: syscon@1b000000 {
 754                 compatible = "mediatek,mt7623-ethsys",
 755                              "mediatek,mt2701-ethsys",
 756                              "syscon";
 757                 reg = <0 0x1b000000 0 0x1000>;
 758                 #clock-cells = <1>;
 759                 #reset-cells = <1>;
 760         };
 761
 762         eth: ethernet@1b100000 {
 763                 compatible = "mediatek,mt7623-eth",
 764                              "mediatek,mt2701-eth",
 765                              "syscon";
 766                 reg = <0 0x1b100000 0 0x20000>;
 767                 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
 768                              <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
 769                              <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
 770                 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
 771                          <&ethsys CLK_ETHSYS_ESW>,
 772                          <&ethsys CLK_ETHSYS_GP1>,
 773                          <&ethsys CLK_ETHSYS_GP2>,
 774                          <&apmixedsys CLK_APMIXED_TRGPLL>;
 775                 clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
 776                 resets = <&ethsys MT2701_ETHSYS_FE_RST>,
 777                          <&ethsys MT2701_ETHSYS_GMAC_RST>,
 778                          <&ethsys MT2701_ETHSYS_PPE_RST>;
 779                 reset-names = "fe", "gmac", "ppe";
 780                 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
 781                 mediatek,ethsys = <&ethsys>;
 782                 mediatek,pctl = <&syscfg_pctl_a>;
 783                 #address-cells = <1>;
 784                 #size-cells = <0>;
 785                 status = "disabled";
 786         };
 787
 788         crypto: crypto@1b240000 {
 789                 compatible = "mediatek,eip97-crypto";
 790                 reg = <0 0x1b240000 0 0x20000>;
 791                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>,
 792                              <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>,
 793                              <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,
 794                              <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,
 795                              <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
 796                 clocks = <&ethsys CLK_ETHSYS_CRYPTO>;
 797                 clock-names = "cryp";
 798                 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
 799                 status = "disabled";
 800         };
 801 };