arch/arm/boot/dts/ls1021a.dtsi

   1 /*
   2  * Copyright 2013-2014 Freescale Semiconductor, Inc.
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of
  12  *     the License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  *     You should have received a copy of the GNU General Public
  20  *     License along with this file; if not, write to the Free
  21  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  22  *     MA 02110-1301 USA
  23  *
  24  * Or, alternatively,
  25  *
  26  *  b) Permission is hereby granted, free of charge, to any person
  27  *     obtaining a copy of this software and associated documentation
  28  *     files (the "Software"), to deal in the Software without
  29  *     restriction, including without limitation the rights to use,
  30  *     copy, modify, merge, publish, distribute, sublicense, and/or
  31  *     sell copies of the Software, and to permit persons to whom the
  32  *     Software is furnished to do so, subject to the following
  33  *     conditions:
  34  *
  35  *     The above copyright notice and this permission notice shall be
  36  *     included in all copies or substantial portions of the Software.
  37  *
  38  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  39  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  40  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  41  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  42  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  43  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  44  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  45  *     OTHER DEALINGS IN THE SOFTWARE.
  46  */
  47
  48 #include "skeleton64.dtsi"
  49 #include <dt-bindings/interrupt-controller/arm-gic.h>
  50
  51 / {
  52         compatible = "fsl,ls1021a";
  53         interrupt-parent = <&gic>;
  54
  55         aliases {
  56                 serial0 = &lpuart0;
  57                 serial1 = &lpuart1;
  58                 serial2 = &lpuart2;
  59                 serial3 = &lpuart3;
  60                 serial4 = &lpuart4;
  61                 serial5 = &lpuart5;
  62                 sysclk = &sysclk;
  63         };
  64
  65         cpus {
  66                 #address-cells = <1>;
  67                 #size-cells = <0>;
  68
  69                 cpu@f00 {
  70                         compatible = "arm,cortex-a7";
  71                         device_type = "cpu";
  72                         reg = <0xf00>;
  73                         clocks = <&cluster1_clk>;
  74                 };
  75
  76                 cpu@f01 {
  77                         compatible = "arm,cortex-a7";
  78                         device_type = "cpu";
  79                         reg = <0xf01>;
  80                         clocks = <&cluster1_clk>;
  81                 };
  82         };
  83
  84         timer {
  85                 compatible = "arm,armv7-timer";
  86                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  87                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  88                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  89                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
  90         };
  91
  92         pmu {
  93                 compatible = "arm,cortex-a7-pmu";
  94                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
  95                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
  96         };
  97
  98         soc {
  99                 compatible = "simple-bus";
 100                 #address-cells = <2>;
 101                 #size-cells = <2>;
 102                 device_type = "soc";
 103                 interrupt-parent = <&gic>;
 104                 ranges;
 105
 106                 gic: interrupt-controller@1400000 {
 107                         compatible = "arm,cortex-a7-gic";
 108                         #interrupt-cells = <3>;
 109                         interrupt-controller;
 110                         reg = <0x0 0x1401000 0x0 0x1000>,
 111                               <0x0 0x1402000 0x0 0x1000>,
 112                               <0x0 0x1404000 0x0 0x2000>,
 113                               <0x0 0x1406000 0x0 0x2000>;
 114                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 115
 116                 };
 117
 118                 ifc: ifc@1530000 {
 119                         compatible = "fsl,ifc", "simple-bus";
 120                         reg = <0x0 0x1530000 0x0 0x10000>;
 121                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 122                 };
 123
 124                 dcfg: dcfg@1ee0000 {
 125                         compatible = "fsl,ls1021a-dcfg", "syscon";
 126                         reg = <0x0 0x1ee0000 0x0 0x10000>;
 127                         big-endian;
 128                 };
 129
 130                 esdhc: esdhc@1560000 {
 131                         compatible = "fsl,esdhc";
 132                         reg = <0x0 0x1560000 0x0 0x10000>;
 133                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 134                         clock-frequency = <0>;
 135                         voltage-ranges = <1800 1800 3300 3300>;
 136                         sdhci,auto-cmd12;
 137                         big-endian;
 138                         bus-width = <4>;
 139                         status = "disabled";
 140                 };
 141
 142                 scfg: scfg@1570000 {
 143                         compatible = "fsl,ls1021a-scfg", "syscon";
 144                         reg = <0x0 0x1570000 0x0 0x10000>;
 145                         big-endian;
 146                 };
 147
 148                 clockgen: clocking@1ee1000 {
 149                         #address-cells = <1>;
 150                         #size-cells = <1>;
 151                         ranges = <0x0 0x0 0x1ee1000 0x10000>;
 152
 153                         sysclk: sysclk {
 154                                 compatible = "fixed-clock";
 155                                 #clock-cells = <0>;
 156                                 clock-output-names = "sysclk";
 157                         };
 158
 159                         cga_pll1: pll@800 {
 160                                 compatible = "fsl,qoriq-core-pll-2.0";
 161                                 #clock-cells = <1>;
 162                                 reg = <0x800 0x10>;
 163                                 clocks = <&sysclk>;
 164                                 clock-output-names = "cga-pll1", "cga-pll1-div2",
 165                                                      "cga-pll1-div4";
 166                         };
 167
 168                         platform_clk: pll@c00 {
 169                                 compatible = "fsl,qoriq-core-pll-2.0";
 170                                 #clock-cells = <1>;
 171                                 reg = <0xc00 0x10>;
 172                                 clocks = <&sysclk>;
 173                                 clock-output-names = "platform-clk", "platform-clk-div2";
 174                         };
 175
 176                         cluster1_clk: clk0c0@0 {
 177                                 compatible = "fsl,qoriq-core-mux-2.0";
 178                                 #clock-cells = <0>;
 179                                 reg = <0x0 0x10>;
 180                                 clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4";
 181                                 clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>;
 182                                 clock-output-names = "cluster1-clk";
 183                         };
 184                 };
 185
 186                 dspi0: dspi@2100000 {
 187                         compatible = "fsl,vf610-dspi";
 188                         #address-cells = <1>;
 189                         #size-cells = <0>;
 190                         reg = <0x0 0x2100000 0x0 0x10000>;
 191                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 192                         clock-names = "dspi";
 193                         clocks = <&platform_clk 1>;
 194                         spi-num-chipselects = <5>;
 195                         big-endian;
 196                         status = "disabled";
 197                 };
 198
 199                 dspi1: dspi@2110000 {
 200                         compatible = "fsl,vf610-dspi";
 201                         #address-cells = <1>;
 202                         #size-cells = <0>;
 203                         reg = <0x0 0x2110000 0x0 0x10000>;
 204                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 205                         clock-names = "dspi";
 206                         clocks = <&platform_clk 1>;
 207                         spi-num-chipselects = <5>;
 208                         big-endian;
 209                         status = "disabled";
 210                 };
 211
 212                 i2c0: i2c@2180000 {
 213                         compatible = "fsl,vf610-i2c";
 214                         #address-cells = <1>;
 215                         #size-cells = <0>;
 216                         reg = <0x0 0x2180000 0x0 0x10000>;
 217                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 218                         clock-names = "i2c";
 219                         clocks = <&platform_clk 1>;
 220                         status = "disabled";
 221                 };
 222
 223                 i2c1: i2c@2190000 {
 224                         compatible = "fsl,vf610-i2c";
 225                         #address-cells = <1>;
 226                         #size-cells = <0>;
 227                         reg = <0x0 0x2190000 0x0 0x10000>;
 228                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 229                         clock-names = "i2c";
 230                         clocks = <&platform_clk 1>;
 231                         status = "disabled";
 232                 };
 233
 234                 i2c2: i2c@21a0000 {
 235                         compatible = "fsl,vf610-i2c";
 236                         #address-cells = <1>;
 237                         #size-cells = <0>;
 238                         reg = <0x0 0x21a0000 0x0 0x10000>;
 239                         interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 240                         clock-names = "i2c";
 241                         clocks = <&platform_clk 1>;
 242                         status = "disabled";
 243                 };
 244
 245                 uart0: serial@21c0500 {
 246                         compatible = "fsl,16550-FIFO64", "ns16550a";
 247                         reg = <0x0 0x21c0500 0x0 0x100>;
 248                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 249                         clock-frequency = <0>;
 250                         fifo-size = <15>;
 251                         status = "disabled";
 252                 };
 253
 254                 uart1: serial@21c0600 {
 255                         compatible = "fsl,16550-FIFO64", "ns16550a";
 256                         reg = <0x0 0x21c0600 0x0 0x100>;
 257                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 258                         clock-frequency = <0>;
 259                         fifo-size = <15>;
 260                         status = "disabled";
 261                 };
 262
 263                 uart2: serial@21d0500 {
 264                         compatible = "fsl,16550-FIFO64", "ns16550a";
 265                         reg = <0x0 0x21d0500 0x0 0x100>;
 266                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 267                         clock-frequency = <0>;
 268                         fifo-size = <15>;
 269                         status = "disabled";
 270                 };
 271
 272                 uart3: serial@21d0600 {
 273                         compatible = "fsl,16550-FIFO64", "ns16550a";
 274                         reg = <0x0 0x21d0600 0x0 0x100>;
 275                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 276                         clock-frequency = <0>;
 277                         fifo-size = <15>;
 278                         status = "disabled";
 279                 };
 280
 281                 lpuart0: serial@2950000 {
 282                         compatible = "fsl,ls1021a-lpuart";
 283                         reg = <0x0 0x2950000 0x0 0x1000>;
 284                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 285                         clocks = <&sysclk>;
 286                         clock-names = "ipg";
 287                         status = "disabled";
 288                 };
 289
 290                 lpuart1: serial@2960000 {
 291                         compatible = "fsl,ls1021a-lpuart";
 292                         reg = <0x0 0x2960000 0x0 0x1000>;
 293                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 294                         clocks = <&platform_clk 1>;
 295                         clock-names = "ipg";
 296                         status = "disabled";
 297                 };
 298
 299                 lpuart2: serial@2970000 {
 300                         compatible = "fsl,ls1021a-lpuart";
 301                         reg = <0x0 0x2970000 0x0 0x1000>;
 302                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 303                         clocks = <&platform_clk 1>;
 304                         clock-names = "ipg";
 305                         status = "disabled";
 306                 };
 307
 308                 lpuart3: serial@2980000 {
 309                         compatible = "fsl,ls1021a-lpuart";
 310                         reg = <0x0 0x2980000 0x0 0x1000>;
 311                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 312                         clocks = <&platform_clk 1>;
 313                         clock-names = "ipg";
 314                         status = "disabled";
 315                 };
 316
 317                 lpuart4: serial@2990000 {
 318                         compatible = "fsl,ls1021a-lpuart";
 319                         reg = <0x0 0x2990000 0x0 0x1000>;
 320                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 321                         clocks = <&platform_clk 1>;
 322                         clock-names = "ipg";
 323                         status = "disabled";
 324                 };
 325
 326                 lpuart5: serial@29a0000 {
 327                         compatible = "fsl,ls1021a-lpuart";
 328                         reg = <0x0 0x29a0000 0x0 0x1000>;
 329                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 330                         clocks = <&platform_clk 1>;
 331                         clock-names = "ipg";
 332                         status = "disabled";
 333                 };
 334
 335                 wdog0: watchdog@2ad0000 {
 336                         compatible = "fsl,imx21-wdt";
 337                         reg = <0x0 0x2ad0000 0x0 0x10000>;
 338                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 339                         clocks = <&platform_clk 1>;
 340                         clock-names = "wdog-en";
 341                         big-endian;
 342                 };
 343
 344                 sai1: sai@2b50000 {
 345                         compatible = "fsl,vf610-sai";
 346                         reg = <0x0 0x2b50000 0x0 0x10000>;
 347                         interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 348                         clocks = <&platform_clk 1>;
 349                         clock-names = "sai";
 350                         dma-names = "tx", "rx";
 351                         dmas = <&edma0 1 47>,
 352                                <&edma0 1 46>;
 353                         big-endian;
 354                         status = "disabled";
 355                 };
 356
 357                 sai2: sai@2b60000 {
 358                         compatible = "fsl,vf610-sai";
 359                         reg = <0x0 0x2b60000 0x0 0x10000>;
 360                         interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
 361                         clocks = <&platform_clk 1>;
 362                         clock-names = "sai";
 363                         dma-names = "tx", "rx";
 364                         dmas = <&edma0 1 45>,
 365                                <&edma0 1 44>;
 366                         big-endian;
 367                         status = "disabled";
 368                 };
 369
 370                 edma0: edma@2c00000 {
 371                         #dma-cells = <2>;
 372                         compatible = "fsl,vf610-edma";
 373                         reg = <0x0 0x2c00000 0x0 0x10000>,
 374                               <0x0 0x2c10000 0x0 0x10000>,
 375                               <0x0 0x2c20000 0x0 0x10000>;
 376                         interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 377                                      <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
 378                         interrupt-names = "edma-tx", "edma-err";
 379                         dma-channels = <32>;
 380                         big-endian;
 381                         clock-names = "dmamux0", "dmamux1";
 382                         clocks = <&platform_clk 1>,
 383                                  <&platform_clk 1>;
 384                 };
 385
 386                 mdio0: mdio@2d24000 {
 387                         compatible = "gianfar";
 388                         device_type = "mdio";
 389                         #address-cells = <1>;
 390                         #size-cells = <0>;
 391                         reg = <0x0 0x2d24000 0x0 0x4000>;
 392                 };
 393
 394                 usb@8600000 {
 395                         compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
 396                         reg = <0x0 0x8600000 0x0 0x1000>;
 397                         interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
 398                         dr_mode = "host";
 399                         phy_type = "ulpi";
 400                 };
 401
 402                 usb3@3100000 {
 403                         compatible = "snps,dwc3";
 404                         reg = <0x0 0x3100000 0x0 0x10000>;
 405                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 406                         dr_mode = "host";
 407                 };
 408         };
 409 };