arch/arm/boot/dts/ls1021a.dtsi

   1 /*
   2  * Copyright 2013-2014 Freescale Semiconductor, Inc.
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of
  12  *     the License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  *     You should have received a copy of the GNU General Public
  20  *     License along with this file; if not, write to the Free
  21  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  22  *     MA 02110-1301 USA
  23  *
  24  * Or, alternatively,
  25  *
  26  *  b) Permission is hereby granted, free of charge, to any person
  27  *     obtaining a copy of this software and associated documentation
  28  *     files (the "Software"), to deal in the Software without
  29  *     restriction, including without limitation the rights to use,
  30  *     copy, modify, merge, publish, distribute, sublicense, and/or
  31  *     sell copies of the Software, and to permit persons to whom the
  32  *     Software is furnished to do so, subject to the following
  33  *     conditions:
  34  *
  35  *     The above copyright notice and this permission notice shall be
  36  *     included in all copies or substantial portions of the Software.
  37  *
  38  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  39  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  40  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  41  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  42  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  43  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  44  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  45  *     OTHER DEALINGS IN THE SOFTWARE.
  46  */
  47
  48 #include "skeleton64.dtsi"
  49 #include <dt-bindings/interrupt-controller/arm-gic.h>
  50 #include <dt-bindings/thermal/thermal.h>
  51
  52 / {
  53         compatible = "fsl,ls1021a";
  54         interrupt-parent = <&gic>;
  55
  56         aliases {
  57                 crypto = &crypto;
  58                 ethernet0 = &enet0;
  59                 ethernet1 = &enet1;
  60                 ethernet2 = &enet2;
  61                 serial0 = &lpuart0;
  62                 serial1 = &lpuart1;
  63                 serial2 = &lpuart2;
  64                 serial3 = &lpuart3;
  65                 serial4 = &lpuart4;
  66                 serial5 = &lpuart5;
  67                 sysclk = &sysclk;
  68         };
  69
  70         cpus {
  71                 #address-cells = <1>;
  72                 #size-cells = <0>;
  73
  74                 cpu0: cpu@f00 {
  75                         compatible = "arm,cortex-a7";
  76                         device_type = "cpu";
  77                         reg = <0xf00>;
  78                         clocks = <&clockgen 1 0>;
  79                         #cooling-cells = <2>;
  80                 };
  81
  82                 cpu1: cpu@f01 {
  83                         compatible = "arm,cortex-a7";
  84                         device_type = "cpu";
  85                         reg = <0xf01>;
  86                         clocks = <&clockgen 1 0>;
  87                         #cooling-cells = <2>;
  88                 };
  89         };
  90
  91         sysclk: sysclk {
  92                 compatible = "fixed-clock";
  93                 #clock-cells = <0>;
  94                 clock-frequency = <100000000>;
  95                 clock-output-names = "sysclk";
  96         };
  97
  98         timer {
  99                 compatible = "arm,armv7-timer";
 100                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 101                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 102                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 103                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 104         };
 105
 106         pmu {
 107                 compatible = "arm,cortex-a7-pmu";
 108                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 109                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
 110                 interrupt-affinity = <&cpu0>, <&cpu1>;
 111         };
 112
 113         reboot {
 114                 compatible = "syscon-reboot";
 115                 regmap = <&dcfg>;
 116                 offset = <0xb0>;
 117                 mask = <0x02>;
 118         };
 119
 120         soc {
 121                 compatible = "simple-bus";
 122                 #address-cells = <2>;
 123                 #size-cells = <2>;
 124                 device_type = "soc";
 125                 interrupt-parent = <&gic>;
 126                 ranges;
 127
 128                 gic: interrupt-controller@1400000 {
 129                         compatible = "arm,gic-400", "arm,cortex-a7-gic";
 130                         #interrupt-cells = <3>;
 131                         interrupt-controller;
 132                         reg = <0x0 0x1401000 0x0 0x1000>,
 133                               <0x0 0x1402000 0x0 0x2000>,
 134                               <0x0 0x1404000 0x0 0x2000>,
 135                               <0x0 0x1406000 0x0 0x2000>;
 136                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 137
 138                 };
 139
 140                 msi1: msi-controller@1570e00 {
 141                         compatible = "fsl,ls1021a-msi";
 142                         reg = <0x0 0x1570e00 0x0 0x8>;
 143                         msi-controller;
 144                         interrupts =  <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
 145                 };
 146
 147                 msi2: msi-controller@1570e08 {
 148                         compatible = "fsl,ls1021a-msi";
 149                         reg = <0x0 0x1570e08 0x0 0x8>;
 150                         msi-controller;
 151                         interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
 152                 };
 153
 154                 ifc: ifc@1530000 {
 155                         compatible = "fsl,ifc", "simple-bus";
 156                         reg = <0x0 0x1530000 0x0 0x10000>;
 157                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 158                 };
 159
 160                 dcfg: dcfg@1ee0000 {
 161                         compatible = "fsl,ls1021a-dcfg", "syscon";
 162                         reg = <0x0 0x1ee0000 0x0 0x10000>;
 163                         big-endian;
 164                 };
 165
 166                 qspi: spi@1550000 {
 167                         compatible = "fsl,ls1021a-qspi";
 168                         #address-cells = <1>;
 169                         #size-cells = <0>;
 170                         reg = <0x0 0x1550000 0x0 0x10000>,
 171                               <0x0 0x40000000 0x0 0x40000000>;
 172                         reg-names = "QuadSPI", "QuadSPI-memory";
 173                         interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
 174                         clock-names = "qspi_en", "qspi";
 175                         clocks = <&clockgen 4 1>, <&clockgen 4 1>;
 176                         big-endian;
 177                         status = "disabled";
 178                 };
 179
 180                 esdhc: esdhc@1560000 {
 181                         compatible = "fsl,ls1021a-esdhc", "fsl,esdhc";
 182                         reg = <0x0 0x1560000 0x0 0x10000>;
 183                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 184                         clock-frequency = <0>;
 185                         voltage-ranges = <1800 1800 3300 3300>;
 186                         sdhci,auto-cmd12;
 187                         big-endian;
 188                         bus-width = <4>;
 189                         status = "disabled";
 190                 };
 191
 192                 sata: sata@3200000 {
 193                         compatible = "fsl,ls1021a-ahci";
 194                         reg = <0x0 0x3200000 0x0 0x10000>,
 195                               <0x0 0x20220520 0x0 0x4>;
 196                         reg-names = "ahci", "sata-ecc";
 197                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 198                         clocks = <&clockgen 4 1>;
 199                         dma-coherent;
 200                         status = "disabled";
 201                 };
 202
 203                 scfg: scfg@1570000 {
 204                         compatible = "fsl,ls1021a-scfg", "syscon";
 205                         reg = <0x0 0x1570000 0x0 0x10000>;
 206                         big-endian;
 207                 };
 208
 209                 crypto: crypto@1700000 {
 210                         compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
 211                         fsl,sec-era = <7>;
 212                         #address-cells = <1>;
 213                         #size-cells = <1>;
 214                         reg              = <0x0 0x1700000 0x0 0x100000>;
 215                         ranges           = <0x0 0x0 0x1700000 0x100000>;
 216                         interrupts       = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 217
 218                         sec_jr0: jr@10000 {
 219                                 compatible = "fsl,sec-v5.0-job-ring",
 220                                      "fsl,sec-v4.0-job-ring";
 221                                 reg = <0x10000 0x10000>;
 222                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 223                         };
 224
 225                         sec_jr1: jr@20000 {
 226                                 compatible = "fsl,sec-v5.0-job-ring",
 227                                      "fsl,sec-v4.0-job-ring";
 228                                 reg = <0x20000 0x10000>;
 229                                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 230                         };
 231
 232                         sec_jr2: jr@30000 {
 233                                 compatible = "fsl,sec-v5.0-job-ring",
 234                                      "fsl,sec-v4.0-job-ring";
 235                                 reg = <0x30000 0x10000>;
 236                                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 237                         };
 238
 239                         sec_jr3: jr@40000 {
 240                                 compatible = "fsl,sec-v5.0-job-ring",
 241                                      "fsl,sec-v4.0-job-ring";
 242                                 reg = <0x40000 0x10000>;
 243                                 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 244                         };
 245
 246                 };
 247
 248                 clockgen: clocking@1ee1000 {
 249                         compatible = "fsl,ls1021a-clockgen";
 250                         reg = <0x0 0x1ee1000 0x0 0x1000>;
 251                         #clock-cells = <2>;
 252                         clocks = <&sysclk>;
 253                 };
 254
 255                 tmu: tmu@1f00000 {
 256                         compatible = "fsl,qoriq-tmu";
 257                         reg = <0x0 0x1f00000 0x0 0x10000>;
 258                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 259                         fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x30061>;
 260                         fsl,tmu-calibration = <0x00000000 0x0000000f
 261                                                0x00000001 0x00000017
 262                                                0x00000002 0x0000001e
 263                                                0x00000003 0x00000026
 264                                                0x00000004 0x0000002e
 265                                                0x00000005 0x00000035
 266                                                0x00000006 0x0000003d
 267                                                0x00000007 0x00000044
 268                                                0x00000008 0x0000004c
 269                                                0x00000009 0x00000053
 270                                                0x0000000a 0x0000005b
 271                                                0x0000000b 0x00000064
 272
 273                                                0x00010000 0x00000011
 274                                                0x00010001 0x0000001c
 275                                                0x00010002 0x00000024
 276                                                0x00010003 0x0000002b
 277                                                0x00010004 0x00000034
 278                                                0x00010005 0x00000039
 279                                                0x00010006 0x00000042
 280                                                0x00010007 0x0000004c
 281                                                0x00010008 0x00000051
 282                                                0x00010009 0x0000005a
 283                                                0x0001000a 0x00000063
 284
 285                                                0x00020000 0x00000013
 286                                                0x00020001 0x00000019
 287                                                0x00020002 0x00000024
 288                                                0x00020003 0x0000002c
 289                                                0x00020004 0x00000035
 290                                                0x00020005 0x0000003d
 291                                                0x00020006 0x00000046
 292                                                0x00020007 0x00000050
 293                                                0x00020008 0x00000059
 294
 295                                                0x00030000 0x00000002
 296                                                0x00030001 0x0000000d
 297                                                0x00030002 0x00000019
 298                                                0x00030003 0x00000024>;
 299                         #thermal-sensor-cells = <1>;
 300                 };
 301
 302                 thermal-zones {
 303                         cpu_thermal: cpu-thermal {
 304                                 polling-delay-passive = <1000>;
 305                                 polling-delay = <5000>;
 306
 307                                 thermal-sensors = <&tmu 0>;
 308
 309                                 trips {
 310                                         cpu_alert: cpu-alert {
 311                                                 temperature = <85000>;
 312                                                 hysteresis = <2000>;
 313                                                 type = "passive";
 314                                         };
 315                                         cpu_crit: cpu-crit {
 316                                                 temperature = <95000>;
 317                                                 hysteresis = <2000>;
 318                                                 type = "critical";
 319                                         };
 320                                 };
 321
 322                                 cooling-maps {
 323                                         map0 {
 324                                                 trip = <&cpu_alert>;
 325                                                 cooling-device =
 326                                                         <&cpu0 THERMAL_NO_LIMIT
 327                                                         THERMAL_NO_LIMIT>,
 328                                                         <&cpu1 THERMAL_NO_LIMIT
 329                                                         THERMAL_NO_LIMIT>;
 330                                         };
 331                                 };
 332                         };
 333                 };
 334
 335                 dspi0: spi@2100000 {
 336                         compatible = "fsl,ls1021a-v1.0-dspi";
 337                         #address-cells = <1>;
 338                         #size-cells = <0>;
 339                         reg = <0x0 0x2100000 0x0 0x10000>;
 340                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 341                         clock-names = "dspi";
 342                         clocks = <&clockgen 4 1>;
 343                         spi-num-chipselects = <6>;
 344                         big-endian;
 345                         status = "disabled";
 346                 };
 347
 348                 dspi1: spi@2110000 {
 349                         compatible = "fsl,ls1021a-v1.0-dspi";
 350                         #address-cells = <1>;
 351                         #size-cells = <0>;
 352                         reg = <0x0 0x2110000 0x0 0x10000>;
 353                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 354                         clock-names = "dspi";
 355                         clocks = <&clockgen 4 1>;
 356                         spi-num-chipselects = <6>;
 357                         big-endian;
 358                         status = "disabled";
 359                 };
 360
 361                 i2c0: i2c@2180000 {
 362                         compatible = "fsl,vf610-i2c";
 363                         #address-cells = <1>;
 364                         #size-cells = <0>;
 365                         reg = <0x0 0x2180000 0x0 0x10000>;
 366                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 367                         clock-names = "i2c";
 368                         clocks = <&clockgen 4 1>;
 369                         dma-names = "tx", "rx";
 370                         dmas = <&edma0 1 39>, <&edma0 1 38>;
 371                         status = "disabled";
 372                 };
 373
 374                 i2c1: i2c@2190000 {
 375                         compatible = "fsl,vf610-i2c";
 376                         #address-cells = <1>;
 377                         #size-cells = <0>;
 378                         reg = <0x0 0x2190000 0x0 0x10000>;
 379                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 380                         clock-names = "i2c";
 381                         clocks = <&clockgen 4 1>;
 382                         dma-names = "tx", "rx";
 383                         dmas = <&edma0 1 37>, <&edma0 1 36>;
 384                         status = "disabled";
 385                 };
 386
 387                 i2c2: i2c@21a0000 {
 388                         compatible = "fsl,vf610-i2c";
 389                         #address-cells = <1>;
 390                         #size-cells = <0>;
 391                         reg = <0x0 0x21a0000 0x0 0x10000>;
 392                         interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 393                         clock-names = "i2c";
 394                         clocks = <&clockgen 4 1>;
 395                         dma-names = "tx", "rx";
 396                         dmas = <&edma0 1 35>, <&edma0 1 34>;
 397                         status = "disabled";
 398                 };
 399
 400                 uart0: serial@21c0500 {
 401                         compatible = "fsl,16550-FIFO64", "ns16550a";
 402                         reg = <0x0 0x21c0500 0x0 0x100>;
 403                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 404                         clock-frequency = <0>;
 405                         fifo-size = <15>;
 406                         status = "disabled";
 407                 };
 408
 409                 uart1: serial@21c0600 {
 410                         compatible = "fsl,16550-FIFO64", "ns16550a";
 411                         reg = <0x0 0x21c0600 0x0 0x100>;
 412                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 413                         clock-frequency = <0>;
 414                         fifo-size = <15>;
 415                         status = "disabled";
 416                 };
 417
 418                 uart2: serial@21d0500 {
 419                         compatible = "fsl,16550-FIFO64", "ns16550a";
 420                         reg = <0x0 0x21d0500 0x0 0x100>;
 421                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 422                         clock-frequency = <0>;
 423                         fifo-size = <15>;
 424                         status = "disabled";
 425                 };
 426
 427                 uart3: serial@21d0600 {
 428                         compatible = "fsl,16550-FIFO64", "ns16550a";
 429                         reg = <0x0 0x21d0600 0x0 0x100>;
 430                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 431                         clock-frequency = <0>;
 432                         fifo-size = <15>;
 433                         status = "disabled";
 434                 };
 435
 436                 gpio0: gpio@2300000 {
 437                         compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
 438                         reg = <0x0 0x2300000 0x0 0x10000>;
 439                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 440                         gpio-controller;
 441                         #gpio-cells = <2>;
 442                         interrupt-controller;
 443                         #interrupt-cells = <2>;
 444                 };
 445
 446                 gpio1: gpio@2310000 {
 447                         compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
 448                         reg = <0x0 0x2310000 0x0 0x10000>;
 449                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 450                         gpio-controller;
 451                         #gpio-cells = <2>;
 452                         interrupt-controller;
 453                         #interrupt-cells = <2>;
 454                 };
 455
 456                 gpio2: gpio@2320000 {
 457                         compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
 458                         reg = <0x0 0x2320000 0x0 0x10000>;
 459                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 460                         gpio-controller;
 461                         #gpio-cells = <2>;
 462                         interrupt-controller;
 463                         #interrupt-cells = <2>;
 464                 };
 465
 466                 gpio3: gpio@2330000 {
 467                         compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
 468                         reg = <0x0 0x2330000 0x0 0x10000>;
 469                         interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
 470                         gpio-controller;
 471                         #gpio-cells = <2>;
 472                         interrupt-controller;
 473                         #interrupt-cells = <2>;
 474                 };
 475
 476                 lpuart0: serial@2950000 {
 477                         compatible = "fsl,ls1021a-lpuart";
 478                         reg = <0x0 0x2950000 0x0 0x1000>;
 479                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 480                         clocks = <&sysclk>;
 481                         clock-names = "ipg";
 482                         status = "disabled";
 483                 };
 484
 485                 lpuart1: serial@2960000 {
 486                         compatible = "fsl,ls1021a-lpuart";
 487                         reg = <0x0 0x2960000 0x0 0x1000>;
 488                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 489                         clocks = <&clockgen 4 1>;
 490                         clock-names = "ipg";
 491                         status = "disabled";
 492                 };
 493
 494                 lpuart2: serial@2970000 {
 495                         compatible = "fsl,ls1021a-lpuart";
 496                         reg = <0x0 0x2970000 0x0 0x1000>;
 497                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 498                         clocks = <&clockgen 4 1>;
 499                         clock-names = "ipg";
 500                         status = "disabled";
 501                 };
 502
 503                 lpuart3: serial@2980000 {
 504                         compatible = "fsl,ls1021a-lpuart";
 505                         reg = <0x0 0x2980000 0x0 0x1000>;
 506                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 507                         clocks = <&clockgen 4 1>;
 508                         clock-names = "ipg";
 509                         status = "disabled";
 510                 };
 511
 512                 lpuart4: serial@2990000 {
 513                         compatible = "fsl,ls1021a-lpuart";
 514                         reg = <0x0 0x2990000 0x0 0x1000>;
 515                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 516                         clocks = <&clockgen 4 1>;
 517                         clock-names = "ipg";
 518                         status = "disabled";
 519                 };
 520
 521                 lpuart5: serial@29a0000 {
 522                         compatible = "fsl,ls1021a-lpuart";
 523                         reg = <0x0 0x29a0000 0x0 0x1000>;
 524                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 525                         clocks = <&clockgen 4 1>;
 526                         clock-names = "ipg";
 527                         status = "disabled";
 528                 };
 529
 530                 pwm0: pwm@29d0000 {
 531                         compatible = "fsl,vf610-ftm-pwm";
 532                         #pwm-cells = <3>;
 533                         reg = <0x0 0x29d0000 0x0 0x10000>;
 534                         clock-names = "ftm_sys", "ftm_ext",
 535                                 "ftm_fix", "ftm_cnt_clk_en";
 536                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
 537                                 <&clockgen 4 1>, <&clockgen 4 1>;
 538                         big-endian;
 539                         status = "disabled";
 540                 };
 541
 542                 pwm1: pwm@29e0000 {
 543                         compatible = "fsl,vf610-ftm-pwm";
 544                         #pwm-cells = <3>;
 545                         reg = <0x0 0x29e0000 0x0 0x10000>;
 546                         clock-names = "ftm_sys", "ftm_ext",
 547                                 "ftm_fix", "ftm_cnt_clk_en";
 548                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
 549                                 <&clockgen 4 1>, <&clockgen 4 1>;
 550                         big-endian;
 551                         status = "disabled";
 552                 };
 553
 554                 pwm2: pwm@29f0000 {
 555                         compatible = "fsl,vf610-ftm-pwm";
 556                         #pwm-cells = <3>;
 557                         reg = <0x0 0x29f0000 0x0 0x10000>;
 558                         clock-names = "ftm_sys", "ftm_ext",
 559                                 "ftm_fix", "ftm_cnt_clk_en";
 560                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
 561                                 <&clockgen 4 1>, <&clockgen 4 1>;
 562                         big-endian;
 563                         status = "disabled";
 564                 };
 565
 566                 pwm3: pwm@2a00000 {
 567                         compatible = "fsl,vf610-ftm-pwm";
 568                         #pwm-cells = <3>;
 569                         reg = <0x0 0x2a00000 0x0 0x10000>;
 570                         clock-names = "ftm_sys", "ftm_ext",
 571                                 "ftm_fix", "ftm_cnt_clk_en";
 572                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
 573                                 <&clockgen 4 1>, <&clockgen 4 1>;
 574                         big-endian;
 575                         status = "disabled";
 576                 };
 577
 578                 pwm4: pwm@2a10000 {
 579                         compatible = "fsl,vf610-ftm-pwm";
 580                         #pwm-cells = <3>;
 581                         reg = <0x0 0x2a10000 0x0 0x10000>;
 582                         clock-names = "ftm_sys", "ftm_ext",
 583                                 "ftm_fix", "ftm_cnt_clk_en";
 584                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
 585                                 <&clockgen 4 1>, <&clockgen 4 1>;
 586                         big-endian;
 587                         status = "disabled";
 588                 };
 589
 590                 pwm5: pwm@2a20000 {
 591                         compatible = "fsl,vf610-ftm-pwm";
 592                         #pwm-cells = <3>;
 593                         reg = <0x0 0x2a20000 0x0 0x10000>;
 594                         clock-names = "ftm_sys", "ftm_ext",
 595                                 "ftm_fix", "ftm_cnt_clk_en";
 596                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
 597                                 <&clockgen 4 1>, <&clockgen 4 1>;
 598                         big-endian;
 599                         status = "disabled";
 600                 };
 601
 602                 pwm6: pwm@2a30000 {
 603                         compatible = "fsl,vf610-ftm-pwm";
 604                         #pwm-cells = <3>;
 605                         reg = <0x0 0x2a30000 0x0 0x10000>;
 606                         clock-names = "ftm_sys", "ftm_ext",
 607                                 "ftm_fix", "ftm_cnt_clk_en";
 608                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
 609                                 <&clockgen 4 1>, <&clockgen 4 1>;
 610                         big-endian;
 611                         status = "disabled";
 612                 };
 613
 614                 pwm7: pwm@2a40000 {
 615                         compatible = "fsl,vf610-ftm-pwm";
 616                         #pwm-cells = <3>;
 617                         reg = <0x0 0x2a40000 0x0 0x10000>;
 618                         clock-names = "ftm_sys", "ftm_ext",
 619                                 "ftm_fix", "ftm_cnt_clk_en";
 620                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
 621                                 <&clockgen 4 1>, <&clockgen 4 1>;
 622                         big-endian;
 623                         status = "disabled";
 624                 };
 625
 626                 wdog0: watchdog@2ad0000 {
 627                         compatible = "fsl,imx21-wdt";
 628                         reg = <0x0 0x2ad0000 0x0 0x10000>;
 629                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 630                         clocks = <&clockgen 4 1>;
 631                         clock-names = "wdog-en";
 632                         big-endian;
 633                 };
 634
 635                 sai1: sai@2b50000 {
 636                         #sound-dai-cells = <0>;
 637                         compatible = "fsl,vf610-sai";
 638                         reg = <0x0 0x2b50000 0x0 0x10000>;
 639                         interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 640                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
 641                                  <&clockgen 4 1>, <&clockgen 4 1>;
 642                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 643                         dma-names = "tx", "rx";
 644                         dmas = <&edma0 1 47>,
 645                                <&edma0 1 46>;
 646                         status = "disabled";
 647                 };
 648
 649                 sai2: sai@2b60000 {
 650                         #sound-dai-cells = <0>;
 651                         compatible = "fsl,vf610-sai";
 652                         reg = <0x0 0x2b60000 0x0 0x10000>;
 653                         interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
 654                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
 655                                  <&clockgen 4 1>, <&clockgen 4 1>;
 656                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 657                         dma-names = "tx", "rx";
 658                         dmas = <&edma0 1 45>,
 659                                <&edma0 1 44>;
 660                         status = "disabled";
 661                 };
 662
 663                 edma0: edma@2c00000 {
 664                         #dma-cells = <2>;
 665                         compatible = "fsl,vf610-edma";
 666                         reg = <0x0 0x2c00000 0x0 0x10000>,
 667                               <0x0 0x2c10000 0x0 0x10000>,
 668                               <0x0 0x2c20000 0x0 0x10000>;
 669                         interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 670                                      <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
 671                         interrupt-names = "edma-tx", "edma-err";
 672                         dma-channels = <32>;
 673                         big-endian;
 674                         clock-names = "dmamux0", "dmamux1";
 675                         clocks = <&clockgen 4 1>,
 676                                  <&clockgen 4 1>;
 677                 };
 678
 679                 dcu: dcu@2ce0000 {
 680                         compatible = "fsl,ls1021a-dcu";
 681                         reg = <0x0 0x2ce0000 0x0 0x10000>;
 682                         interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
 683                         clocks = <&clockgen 4 0>,
 684                                 <&clockgen 4 0>;
 685                         clock-names = "dcu", "pix";
 686                         big-endian;
 687                         status = "disabled";
 688                 };
 689
 690                 mdio0: mdio@2d24000 {
 691                         compatible = "gianfar";
 692                         device_type = "mdio";
 693                         #address-cells = <1>;
 694                         #size-cells = <0>;
 695                         reg = <0x0 0x2d24000 0x0 0x4000>,
 696                               <0x0 0x2d10030 0x0 0x4>;
 697                 };
 698
 699                 ptp_clock@2d10e00 {
 700                         compatible = "fsl,etsec-ptp";
 701                         reg = <0x0 0x2d10e00 0x0 0xb0>;
 702                         interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
 703                         fsl,tclk-period = <5>;
 704                         fsl,tmr-prsc    = <2>;
 705                         fsl,tmr-add     = <0xaaaaaaab>;
 706                         fsl,tmr-fiper1  = <999999995>;
 707                         fsl,tmr-fiper2  = <99990>;
 708                         fsl,max-adj     = <499999999>;
 709                         fsl,extts-fifo;
 710                 };
 711
 712                 enet0: ethernet@2d10000 {
 713                         compatible = "fsl,etsec2";
 714                         device_type = "network";
 715                         #address-cells = <2>;
 716                         #size-cells = <2>;
 717                         interrupt-parent = <&gic>;
 718                         model = "eTSEC";
 719                         fsl,magic-packet;
 720                         ranges;
 721                         dma-coherent;
 722
 723                         queue-group@2d10000 {
 724                                 #address-cells = <2>;
 725                                 #size-cells = <2>;
 726                                 reg = <0x0 0x2d10000 0x0 0x1000>;
 727                                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
 728                                         <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
 729                                         <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
 730                         };
 731
 732                         queue-group@2d14000  {
 733                                 #address-cells = <2>;
 734                                 #size-cells = <2>;
 735                                 reg = <0x0 0x2d14000 0x0 0x1000>;
 736                                 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 737                                         <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 738                                         <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 739                         };
 740                 };
 741
 742                 enet1: ethernet@2d50000 {
 743                         compatible = "fsl,etsec2";
 744                         device_type = "network";
 745                         #address-cells = <2>;
 746                         #size-cells = <2>;
 747                         interrupt-parent = <&gic>;
 748                         model = "eTSEC";
 749                         ranges;
 750                         dma-coherent;
 751
 752                         queue-group@2d50000  {
 753                                 #address-cells = <2>;
 754                                 #size-cells = <2>;
 755                                 reg = <0x0 0x2d50000 0x0 0x1000>;
 756                                 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
 757                                         <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
 758                                         <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 759                         };
 760
 761                         queue-group@2d54000  {
 762                                 #address-cells = <2>;
 763                                 #size-cells = <2>;
 764                                 reg = <0x0 0x2d54000 0x0 0x1000>;
 765                                 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
 766                                         <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
 767                                         <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
 768                         };
 769                 };
 770
 771                 enet2: ethernet@2d90000 {
 772                         compatible = "fsl,etsec2";
 773                         device_type = "network";
 774                         #address-cells = <2>;
 775                         #size-cells = <2>;
 776                         interrupt-parent = <&gic>;
 777                         model = "eTSEC";
 778                         ranges;
 779                         dma-coherent;
 780
 781                         queue-group@2d90000  {
 782                                 #address-cells = <2>;
 783                                 #size-cells = <2>;
 784                                 reg = <0x0 0x2d90000 0x0 0x1000>;
 785                                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
 786                                         <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
 787                                         <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
 788                         };
 789
 790                         queue-group@2d94000  {
 791                                 #address-cells = <2>;
 792                                 #size-cells = <2>;
 793                                 reg = <0x0 0x2d94000 0x0 0x1000>;
 794                                 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
 795                                         <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
 796                                         <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
 797                         };
 798                 };
 799
 800                 usb2: usb@8600000 {
 801                         compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
 802                         reg = <0x0 0x8600000 0x0 0x1000>;
 803                         interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
 804                         dr_mode = "host";
 805                         phy_type = "ulpi";
 806                 };
 807
 808                 usb3: usb3@3100000 {
 809                         compatible = "snps,dwc3";
 810                         reg = <0x0 0x3100000 0x0 0x10000>;
 811                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 812                         dr_mode = "host";
 813                         snps,quirk-frame-length-adjustment = <0x20>;
 814                         snps,dis_rxdet_inp3_quirk;
 815                 };
 816
 817                 pcie@3400000 {
 818                         compatible = "fsl,ls1021a-pcie";
 819                         reg = <0x00 0x03400000 0x0 0x00010000   /* controller registers */
 820                                0x40 0x00000000 0x0 0x00002000>; /* configuration space */
 821                         reg-names = "regs", "config";
 822                         interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
 823                         fsl,pcie-scfg = <&scfg 0>;
 824                         #address-cells = <3>;
 825                         #size-cells = <2>;
 826                         device_type = "pci";
 827                         num-lanes = <4>;
 828                         bus-range = <0x0 0xff>;
 829                         ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
 830                                   0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 831                         msi-parent = <&msi1>, <&msi2>;
 832                         #interrupt-cells = <1>;
 833                         interrupt-map-mask = <0 0 0 7>;
 834                         interrupt-map = <0000 0 0 1 &gic GIC_SPI 91  IRQ_TYPE_LEVEL_HIGH>,
 835                                         <0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
 836                                         <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
 837                                         <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
 838                         status = "disabled";
 839                 };
 840
 841                 pcie@3500000 {
 842                         compatible = "fsl,ls1021a-pcie";
 843                         reg = <0x00 0x03500000 0x0 0x00010000   /* controller registers */
 844                                0x48 0x00000000 0x0 0x00002000>; /* configuration space */
 845                         reg-names = "regs", "config";
 846                         interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
 847                         fsl,pcie-scfg = <&scfg 1>;
 848                         #address-cells = <3>;
 849                         #size-cells = <2>;
 850                         device_type = "pci";
 851                         num-lanes = <4>;
 852                         bus-range = <0x0 0xff>;
 853                         ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
 854                                   0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 855                         msi-parent = <&msi1>, <&msi2>;
 856                         #interrupt-cells = <1>;
 857                         interrupt-map-mask = <0 0 0 7>;
 858                         interrupt-map = <0000 0 0 1 &gic GIC_SPI 92  IRQ_TYPE_LEVEL_HIGH>,
 859                                         <0000 0 0 2 &gic GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
 860                                         <0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
 861                                         <0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
 862                         status = "disabled";
 863                 };
 864
 865                 can0: can@2a70000 {
 866                         compatible = "fsl,ls1021ar2-flexcan";
 867                         reg = <0x0 0x2a70000 0x0 0x1000>;
 868                         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 869                         clocks = <&clockgen 4 1>, <&clockgen 4 1>;
 870                         clock-names = "ipg", "per";
 871                         big-endian;
 872                 };
 873
 874                 can1: can@2a80000 {
 875                         compatible = "fsl,ls1021ar2-flexcan";
 876                         reg = <0x0 0x2a80000 0x0 0x1000>;
 877                         interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 878                         clocks = <&clockgen 4 1>, <&clockgen 4 1>;
 879                         clock-names = "ipg", "per";
 880                         big-endian;
 881                 };
 882
 883                 can2: can@2a90000 {
 884                         compatible = "fsl,ls1021ar2-flexcan";
 885                         reg = <0x0 0x2a90000 0x0 0x1000>;
 886                         interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
 887                         clocks = <&clockgen 4 1>, <&clockgen 4 1>;
 888                         clock-names = "ipg", "per";
 889                         big-endian;
 890                 };
 891
 892                 can3: can@2aa0000 {
 893                         compatible = "fsl,ls1021ar2-flexcan";
 894                         reg = <0x0 0x2aa0000 0x0 0x1000>;
 895                         interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
 896                         clocks = <&clockgen 4 1>, <&clockgen 4 1>;
 897                         clock-names = "ipg", "per";
 898                         big-endian;
 899                 };
 900
 901                 ocram1: sram@10000000 {
 902                         compatible = "mmio-sram";
 903                         reg = <0x0 0x10000000 0x0 0x10000>;
 904                         #address-cells = <1>;
 905                         #size-cells = <1>;
 906                         ranges = <0x0 0x0 0x10000000 0x10000>;
 907                 };
 908
 909                 ocram2: sram@10010000 {
 910                         compatible = "mmio-sram";
 911                         reg = <0x0 0x10010000 0x0 0x10000>;
 912                         #address-cells = <1>;
 913                         #size-cells = <1>;
 914                         ranges = <0x0 0x0 0x10010000 0x10000>;
 915                 };
 916
 917                 qdma: dma-controller@8390000 {
 918                         compatible = "fsl,ls1021a-qdma";
 919                         reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */
 920                               <0x0 0x8389000 0x0 0x1000>, /* Status regs */
 921                               <0x0 0x838a000 0x0 0x2000>; /* Block regs */
 922                         interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
 923                                      <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 924                                      <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 925                         interrupt-names = "qdma-error",
 926                                 "qdma-queue0", "qdma-queue1";
 927                         dma-channels = <8>;
 928                         block-number = <1>;
 929                         block-offset = <0x1000>;
 930                         fsl,dma-queues = <2>;
 931                         status-sizes = <64>;
 932                         queue-sizes = <64 64>;
 933                         big-endian;
 934                 };
 935
 936         };
 937 };