arch/arm/boot/dts/imx7ulp.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2016 Freescale Semiconductor, Inc.
   4  * Copyright 2017-2018 NXP
   5  *   Dong Aisheng <aisheng.dong@nxp.com>
   6  */
   7
   8 #include <dt-bindings/clock/imx7ulp-clock.h>
   9 #include <dt-bindings/gpio/gpio.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11
  12 #include "imx7ulp-pinfunc.h"
  13
  14 / {
  15         interrupt-parent = <&intc>;
  16
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         aliases {
  21                 gpio0 = &gpio_ptc;
  22                 gpio1 = &gpio_ptd;
  23                 gpio2 = &gpio_pte;
  24                 gpio3 = &gpio_ptf;
  25                 i2c0 = &lpi2c6;
  26                 i2c1 = &lpi2c7;
  27                 mmc0 = &usdhc0;
  28                 mmc1 = &usdhc1;
  29                 serial0 = &lpuart4;
  30                 serial1 = &lpuart5;
  31                 serial2 = &lpuart6;
  32                 serial3 = &lpuart7;
  33                 usbphy0 = &usbphy1;
  34         };
  35
  36         cpus {
  37                 #address-cells = <1>;
  38                 #size-cells = <0>;
  39
  40                 cpu0: cpu@0 {
  41                         compatible = "arm,cortex-a7";
  42                         device_type = "cpu";
  43                         reg = <0>;
  44                 };
  45         };
  46
  47         intc: interrupt-controller@40021000 {
  48                 compatible = "arm,cortex-a7-gic";
  49                 #interrupt-cells = <3>;
  50                 interrupt-controller;
  51                 reg = <0x40021000 0x1000>,
  52                       <0x40022000 0x1000>;
  53         };
  54
  55         rosc: clock-rosc {
  56                 compatible = "fixed-clock";
  57                 clock-frequency = <32768>;
  58                 clock-output-names = "rosc";
  59                 #clock-cells = <0>;
  60         };
  61
  62         sosc: clock-sosc {
  63                 compatible = "fixed-clock";
  64                 clock-frequency = <24000000>;
  65                 clock-output-names = "sosc";
  66                 #clock-cells = <0>;
  67         };
  68
  69         sirc: clock-sirc {
  70                 compatible = "fixed-clock";
  71                 clock-frequency = <16000000>;
  72                 clock-output-names = "sirc";
  73                 #clock-cells = <0>;
  74         };
  75
  76         firc: clock-firc {
  77                 compatible = "fixed-clock";
  78                 clock-frequency = <48000000>;
  79                 clock-output-names = "firc";
  80                 #clock-cells = <0>;
  81         };
  82
  83         upll: clock-upll {
  84                 compatible = "fixed-clock";
  85                 clock-frequency = <480000000>;
  86                 clock-output-names = "upll";
  87                 #clock-cells = <0>;
  88         };
  89
  90         mpll: clock-mpll {
  91                 compatible = "fixed-clock";
  92                 clock-frequency = <480000000>;
  93                 clock-output-names = "mpll";
  94                 #clock-cells = <0>;
  95         };
  96
  97         ahbbridge0: bus@40000000 {
  98                 compatible = "simple-bus";
  99                 #address-cells = <1>;
 100                 #size-cells = <1>;
 101                 reg = <0x40000000 0x800000>;
 102                 ranges;
 103
 104                 crypto: crypto@40240000 {
 105                         compatible = "fsl,sec-v4.0";
 106                         #address-cells = <1>;
 107                         #size-cells = <1>;
 108                         reg = <0x40240000 0x10000>;
 109                         ranges = <0 0x40240000 0x10000>;
 110                         clocks = <&pcc2 IMX7ULP_CLK_CAAM>,
 111                                  <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>;
 112                         clock-names = "aclk", "ipg";
 113
 114                         sec_jr0: jr0@1000 {
 115                                 compatible = "fsl,sec-v4.0-job-ring";
 116                                 reg = <0x1000 0x1000>;
 117                                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 118                         };
 119
 120                         sec_jr1: jr1@2000 {
 121                                 compatible = "fsl,sec-v4.0-job-ring";
 122                                 reg = <0x2000 0x1000>;
 123                                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 124                         };
 125                 };
 126
 127                 lpuart4: serial@402d0000 {
 128                         compatible = "fsl,imx7ulp-lpuart";
 129                         reg = <0x402d0000 0x1000>;
 130                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 131                         clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
 132                         clock-names = "ipg";
 133                         assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
 134                         assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
 135                         assigned-clock-rates = <24000000>;
 136                         status = "disabled";
 137                 };
 138
 139                 lpuart5: serial@402e0000 {
 140                         compatible = "fsl,imx7ulp-lpuart";
 141                         reg = <0x402e0000 0x1000>;
 142                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 143                         clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
 144                         clock-names = "ipg";
 145                         assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
 146                         assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
 147                         assigned-clock-rates = <48000000>;
 148                         status = "disabled";
 149                 };
 150
 151                 tpm4: pwm@40250000 {
 152                         compatible = "fsl,imx7ulp-pwm";
 153                         reg = <0x40250000 0x1000>;
 154                         assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
 155                         assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
 156                         clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
 157                         #pwm-cells = <3>;
 158                         status = "disabled";
 159                 };
 160
 161                 tpm5: tpm@40260000 {
 162                         compatible = "fsl,imx7ulp-tpm";
 163                         reg = <0x40260000 0x1000>;
 164                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 165                         clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
 166                                  <&pcc2 IMX7ULP_CLK_LPTPM5>;
 167                         clock-names = "ipg", "per";
 168                 };
 169
 170                 usbotg1: usb@40330000 {
 171                         compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb";
 172                         reg = <0x40330000 0x200>;
 173                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 174                         clocks = <&pcc2 IMX7ULP_CLK_USB0>;
 175                         phys = <&usbphy1>;
 176                         fsl,usbmisc = <&usbmisc1 0>;
 177                         ahb-burst-config = <0x0>;
 178                         tx-burst-size-dword = <0x8>;
 179                         rx-burst-size-dword = <0x8>;
 180                         status = "disabled";
 181                 };
 182
 183                 usbmisc1: usbmisc@40330200 {
 184                         compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc";
 185                         #index-cells = <1>;
 186                         reg = <0x40330200 0x200>;
 187                 };
 188
 189                 usbphy1: usb-phy@40350000 {
 190                         compatible = "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy";
 191                         reg = <0x40350000 0x1000>;
 192                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 193                         clocks = <&pcc2 IMX7ULP_CLK_USB_PHY>;
 194                         #phy-cells = <0>;
 195                 };
 196
 197                 usdhc0: mmc@40370000 {
 198                         compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
 199                         reg = <0x40370000 0x10000>;
 200                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 201                         clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
 202                                  <&scg1 IMX7ULP_CLK_NIC1_DIV>,
 203                                  <&pcc2 IMX7ULP_CLK_USDHC0>;
 204                         clock-names ="ipg", "ahb", "per";
 205                         assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;
 206                         assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
 207                         bus-width = <4>;
 208                         fsl,tuning-start-tap = <20>;
 209                         fsl,tuning-step= <2>;
 210                         status = "disabled";
 211                 };
 212
 213                 usdhc1: mmc@40380000 {
 214                         compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
 215                         reg = <0x40380000 0x10000>;
 216                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 217                         clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
 218                                  <&scg1 IMX7ULP_CLK_NIC1_DIV>,
 219                                  <&pcc2 IMX7ULP_CLK_USDHC1>;
 220                         clock-names ="ipg", "ahb", "per";
 221                         assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC1>;
 222                         assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
 223                         bus-width = <4>;
 224                         fsl,tuning-start-tap = <20>;
 225                         fsl,tuning-step= <2>;
 226                         status = "disabled";
 227                 };
 228
 229                 scg1: clock-controller@403e0000 {
 230                         compatible = "fsl,imx7ulp-scg1";
 231                         reg = <0x403e0000 0x10000>;
 232                         clocks = <&rosc>, <&sosc>, <&sirc>,
 233                                  <&firc>, <&upll>, <&mpll>;
 234                         clock-names = "rosc", "sosc", "sirc",
 235                                       "firc", "upll", "mpll";
 236                         #clock-cells = <1>;
 237                 };
 238
 239                 pcc2: clock-controller@403f0000 {
 240                         compatible = "fsl,imx7ulp-pcc2";
 241                         reg = <0x403f0000 0x10000>;
 242                         #clock-cells = <1>;
 243                         clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
 244                                  <&scg1 IMX7ULP_CLK_NIC1_DIV>,
 245                                  <&scg1 IMX7ULP_CLK_DDR_DIV>,
 246                                  <&scg1 IMX7ULP_CLK_APLL_PFD2>,
 247                                  <&scg1 IMX7ULP_CLK_APLL_PFD1>,
 248                                  <&scg1 IMX7ULP_CLK_APLL_PFD0>,
 249                                  <&scg1 IMX7ULP_CLK_UPLL>,
 250                                  <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
 251                                  <&scg1 IMX7ULP_CLK_MIPI_PLL>,
 252                                  <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
 253                                  <&scg1 IMX7ULP_CLK_ROSC>,
 254                                  <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
 255                         clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
 256                                       "apll_pfd2", "apll_pfd1", "apll_pfd0",
 257                                       "upll", "sosc_bus_clk", "mpll",
 258                                       "firc_bus_clk", "rosc", "spll_bus_clk";
 259                         assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM5>;
 260                         assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
 261                 };
 262
 263                 smc1: clock-controller@40410000 {
 264                         compatible = "fsl,imx7ulp-smc1";
 265                         reg = <0x40410000 0x1000>;
 266                         #clock-cells = <1>;
 267                         clocks = <&scg1 IMX7ULP_CLK_CORE_DIV>,
 268                                  <&scg1 IMX7ULP_CLK_HSRUN_CORE_DIV>;
 269                         clock-names = "divcore", "hsrun_divcore";
 270                 };
 271
 272                 pcc3: clock-controller@40b30000 {
 273                         compatible = "fsl,imx7ulp-pcc3";
 274                         reg = <0x40b30000 0x10000>;
 275                         #clock-cells = <1>;
 276                         clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
 277                                  <&scg1 IMX7ULP_CLK_NIC1_DIV>,
 278                                  <&scg1 IMX7ULP_CLK_DDR_DIV>,
 279                                  <&scg1 IMX7ULP_CLK_APLL_PFD2>,
 280                                  <&scg1 IMX7ULP_CLK_APLL_PFD1>,
 281                                  <&scg1 IMX7ULP_CLK_APLL_PFD0>,
 282                                  <&scg1 IMX7ULP_CLK_UPLL>,
 283                                  <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
 284                                  <&scg1 IMX7ULP_CLK_MIPI_PLL>,
 285                                  <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
 286                                  <&scg1 IMX7ULP_CLK_ROSC>,
 287                                  <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
 288                         clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
 289                                       "apll_pfd2", "apll_pfd1", "apll_pfd0",
 290                                       "upll", "sosc_bus_clk", "mpll",
 291                                       "firc_bus_clk", "rosc", "spll_bus_clk";
 292                 };
 293         };
 294
 295         ahbbridge1: bus@40800000 {
 296                 compatible = "simple-bus";
 297                 #address-cells = <1>;
 298                 #size-cells = <1>;
 299                 reg = <0x40800000 0x800000>;
 300                 ranges;
 301
 302                 lpi2c6: i2c@40a40000 {
 303                         compatible = "fsl,imx7ulp-lpi2c";
 304                         reg = <0x40a40000 0x10000>;
 305                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 306                         clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
 307                         clock-names = "ipg";
 308                         assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
 309                         assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
 310                         assigned-clock-rates = <48000000>;
 311                         status = "disabled";
 312                 };
 313
 314                 lpi2c7: i2c@40a50000 {
 315                         compatible = "fsl,imx7ulp-lpi2c";
 316                         reg = <0x40a50000 0x10000>;
 317                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 318                         clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
 319                         clock-names = "ipg";
 320                         assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
 321                         assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
 322                         assigned-clock-rates = <48000000>;
 323                         status = "disabled";
 324                 };
 325
 326                 lpuart6: serial@40a60000 {
 327                         compatible = "fsl,imx7ulp-lpuart";
 328                         reg = <0x40a60000 0x1000>;
 329                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 330                         clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
 331                         clock-names = "ipg";
 332                         assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
 333                         assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
 334                         assigned-clock-rates = <48000000>;
 335                         status = "disabled";
 336                 };
 337
 338                 lpuart7: serial@40a70000 {
 339                         compatible = "fsl,imx7ulp-lpuart";
 340                         reg = <0x40a70000 0x1000>;
 341                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 342                         clocks = <&pcc3  IMX7ULP_CLK_LPUART7>;
 343                         clock-names = "ipg";
 344                         assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
 345                         assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
 346                         assigned-clock-rates = <48000000>;
 347                         status = "disabled";
 348                 };
 349
 350                 memory-controller@40ab0000 {
 351                         compatible = "fsl,imx7ulp-mmdc", "fsl,imx6q-mmdc";
 352                         reg = <0x40ab0000 0x1000>;
 353                         clocks = <&pcc3 IMX7ULP_CLK_MMDC>;
 354                 };
 355
 356                 iomuxc1: pinctrl@40ac0000 {
 357                         compatible = "fsl,imx7ulp-iomuxc1";
 358                         reg = <0x40ac0000 0x1000>;
 359                 };
 360
 361                 gpio_ptc: gpio@40ae0000 {
 362                         compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
 363                         reg = <0x40ae0000 0x1000 0x400f0000 0x40>;
 364                         gpio-controller;
 365                         #gpio-cells = <2>;
 366                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 367                         interrupt-controller;
 368                         #interrupt-cells = <2>;
 369                         clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
 370                                  <&pcc3 IMX7ULP_CLK_PCTLC>;
 371                         clock-names = "gpio", "port";
 372                         gpio-ranges = <&iomuxc1 0 0 32>;
 373                 };
 374
 375                 gpio_ptd: gpio@40af0000 {
 376                         compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
 377                         reg = <0x40af0000 0x1000 0x400f0040 0x40>;
 378                         gpio-controller;
 379                         #gpio-cells = <2>;
 380                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 381                         interrupt-controller;
 382                         #interrupt-cells = <2>;
 383                         clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
 384                                  <&pcc3 IMX7ULP_CLK_PCTLD>;
 385                         clock-names = "gpio", "port";
 386                         gpio-ranges = <&iomuxc1 0 32 32>;
 387                 };
 388
 389                 gpio_pte: gpio@40b00000 {
 390                         compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
 391                         reg = <0x40b00000 0x1000 0x400f0080 0x40>;
 392                         gpio-controller;
 393                         #gpio-cells = <2>;
 394                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 395                         interrupt-controller;
 396                         #interrupt-cells = <2>;
 397                         clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
 398                                  <&pcc3 IMX7ULP_CLK_PCTLE>;
 399                         clock-names = "gpio", "port";
 400                         gpio-ranges = <&iomuxc1 0 64 32>;
 401                 };
 402
 403                 gpio_ptf: gpio@40b10000 {
 404                         compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
 405                         reg = <0x40b10000 0x1000 0x400f00c0 0x40>;
 406                         gpio-controller;
 407                         #gpio-cells = <2>;
 408                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 409                         interrupt-controller;
 410                         #interrupt-cells = <2>;
 411                         clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
 412                                  <&pcc3 IMX7ULP_CLK_PCTLF>;
 413                         clock-names = "gpio", "port";
 414                         gpio-ranges = <&iomuxc1 0 96 32>;
 415                 };
 416         };
 417
 418         m4aips1: bus@41080000 {
 419                 compatible = "simple-bus";
 420                 #address-cells = <1>;
 421                 #size-cells = <1>;
 422                 reg = <0x41080000 0x80000>;
 423                 ranges;
 424
 425                 sim: sim@410a3000 {
 426                         compatible = "fsl,imx7ulp-sim", "syscon";
 427                         reg = <0x410a3000 0x1000>;
 428                 };
 429
 430                 ocotp: ocotp-ctrl@410a6000 {
 431                         compatible = "fsl,imx7ulp-ocotp", "syscon";
 432                         reg = <0x410a6000 0x4000>;
 433                         clocks = <&scg1 IMX7ULP_CLK_DUMMY>;
 434                 };
 435         };
 436 };