arch/arm/boot/dts/imx7d-cl-som-imx7.dts

   1 /*
   2  * Support for CompuLab CL-SOM-iMX7 System-on-Module
   3  *
   4  * Copyright (C) 2015 CompuLab Ltd. - http://www.compulab.co.il/
   5  * Author: Ilya Ledvich <ilya@compulab.co.il>
   6  *
   7  * This file is dual-licensed: you can use it either under the terms
   8  * of the GPL or the X11 license, at your option. Note that this dual
   9  * licensing only applies to this file, and not this project as a
  10  * whole.
  11  */
  12
  13 /dts-v1/;
  14
  15 #include "imx7d.dtsi"
  16
  17 / {
  18         model = "CompuLab CL-SOM-iMX7";
  19         compatible = "compulab,cl-som-imx7", "fsl,imx7d";
  20
  21         memory@80000000 {
  22                 device_type = "memory";
  23                 reg = <0x80000000 0x10000000>; /* 256 MB - minimal configuration */
  24         };
  25
  26         reg_usb_otg1_vbus: regulator-vbus {
  27                 compatible = "regulator-fixed";
  28                 regulator-name = "usb_otg1_vbus";
  29                 regulator-min-microvolt = <5000000>;
  30                 regulator-max-microvolt = <5000000>;
  31                 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
  32                 enable-active-high;
  33         };
  34 };
  35
  36 &cpu0 {
  37         cpu-supply = <&sw1a_reg>;
  38 };
  39
  40 &fec1 {
  41         pinctrl-names = "default";
  42         pinctrl-0 = <&pinctrl_enet1>;
  43         assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
  44                           <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
  45         assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
  46         assigned-clock-rates = <0>, <100000000>;
  47         phy-mode = "rgmii-id";
  48         phy-handle = <&ethphy0>;
  49         fsl,magic-packet;
  50         status = "okay";
  51
  52         mdio {
  53                 #address-cells = <1>;
  54                 #size-cells = <0>;
  55
  56                 ethphy0: ethernet-phy@0 {
  57                         compatible = "ethernet-phy-ieee802.3-c22";
  58                         reg = <0>;
  59                 };
  60
  61                 ethphy1: ethernet-phy@1 {
  62                         compatible = "ethernet-phy-ieee802.3-c22";
  63                         reg = <1>;
  64                 };
  65         };
  66 };
  67
  68 &fec2 {
  69         pinctrl-names = "default";
  70         pinctrl-0 = <&pinctrl_enet2>;
  71         assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
  72                           <&clks IMX7D_ENET2_TIME_ROOT_CLK>;
  73         assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
  74         assigned-clock-rates = <0>, <100000000>;
  75         phy-mode = "rgmii-id";
  76         phy-handle = <&ethphy1>;
  77         fsl,magic-packet;
  78         status = "okay";
  79 };
  80
  81 &i2c2 {
  82         pinctrl-names = "default";
  83         pinctrl-0 = <&pinctrl_i2c2>;
  84         status = "okay";
  85
  86         pmic: pmic@8 {
  87                 compatible = "fsl,pfuze3000";
  88                 reg = <0x08>;
  89
  90                 regulators {
  91                         sw1a_reg: sw1a {
  92                                 regulator-min-microvolt = <700000>;
  93                                 regulator-max-microvolt = <1475000>;
  94                                 regulator-boot-on;
  95                                 regulator-always-on;
  96                                 regulator-ramp-delay = <6250>;
  97                         };
  98
  99                         /* use sw1c_reg to align with pfuze100/pfuze200 */
 100                         sw1c_reg: sw1b {
 101                                 regulator-min-microvolt = <700000>;
 102                                 regulator-max-microvolt = <1475000>;
 103                                 regulator-boot-on;
 104                                 regulator-always-on;
 105                                 regulator-ramp-delay = <6250>;
 106                         };
 107
 108                         sw2_reg: sw2 {
 109                                 regulator-min-microvolt = <1500000>;
 110                                 regulator-max-microvolt = <1850000>;
 111                                 regulator-boot-on;
 112                                 regulator-always-on;
 113                         };
 114
 115                         sw3a_reg: sw3 {
 116                                 regulator-min-microvolt = <900000>;
 117                                 regulator-max-microvolt = <1650000>;
 118                                 regulator-boot-on;
 119                                 regulator-always-on;
 120                         };
 121
 122                         swbst_reg: swbst {
 123                                 regulator-min-microvolt = <5000000>;
 124                                 regulator-max-microvolt = <5150000>;
 125                         };
 126
 127                         snvs_reg: vsnvs {
 128                                 regulator-min-microvolt = <1000000>;
 129                                 regulator-max-microvolt = <3000000>;
 130                                 regulator-boot-on;
 131                                 regulator-always-on;
 132                         };
 133
 134                         vref_reg: vrefddr {
 135                                 regulator-boot-on;
 136                                 regulator-always-on;
 137                         };
 138
 139                         vgen1_reg: vldo1 {
 140                                 regulator-min-microvolt = <1800000>;
 141                                 regulator-max-microvolt = <3300000>;
 142                                 regulator-always-on;
 143                         };
 144
 145                         vgen2_reg: vldo2 {
 146                                 regulator-min-microvolt = <800000>;
 147                                 regulator-max-microvolt = <1550000>;
 148                         };
 149
 150                         vgen3_reg: vccsd {
 151                                 regulator-min-microvolt = <2850000>;
 152                                 regulator-max-microvolt = <3300000>;
 153                                 regulator-always-on;
 154                         };
 155
 156                         vgen4_reg: v33 {
 157                                 regulator-min-microvolt = <2850000>;
 158                                 regulator-max-microvolt = <3300000>;
 159                                 regulator-always-on;
 160                         };
 161
 162                         vgen5_reg: vldo3 {
 163                                 regulator-min-microvolt = <1800000>;
 164                                 regulator-max-microvolt = <3300000>;
 165                                 regulator-always-on;
 166                         };
 167
 168                         vgen6_reg: vldo4 {
 169                                 regulator-min-microvolt = <1800000>;
 170                                 regulator-max-microvolt = <3300000>;
 171                                 regulator-always-on;
 172                         };
 173                 };
 174         };
 175
 176         pca9555: pca9555@20 {
 177                 compatible = "nxp,pca9555";
 178                 gpio-controller;
 179                 #gpio-cells = <2>;
 180                 reg = <0x20>;
 181         };
 182
 183         eeprom@50 {
 184                 compatible = "atmel,24c08";
 185                 reg = <0x50>;
 186                 pagesize = <16>;
 187         };
 188 };
 189
 190 &uart1 {
 191         pinctrl-names = "default";
 192         pinctrl-0 = <&pinctrl_uart1>;
 193         assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
 194         assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
 195         status = "okay";
 196 };
 197
 198 &usbotg1 {
 199         pinctrl-names = "default";
 200         pinctrl-0 = <&pinctrl_usbotg1>;
 201         vbus-supply = <&reg_usb_otg1_vbus>;
 202         status = "okay";
 203 };
 204
 205 &usdhc3 {
 206         pinctrl-names = "default";
 207         pinctrl-0 = <&pinctrl_usdhc3>;
 208         assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
 209         assigned-clock-rates = <400000000>;
 210         bus-width = <8>;
 211         fsl,tuning-step = <2>;
 212         non-removable;
 213         status = "okay";
 214 };
 215
 216 &iomuxc {
 217         pinctrl_enet1: enet1grp {
 218                 fsl,pins = <
 219                         MX7D_PAD_SD2_CD_B__ENET1_MDIO                   0x30
 220                         MX7D_PAD_SD2_WP__ENET1_MDC                      0x30
 221                         MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC       0x11
 222                         MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0       0x11
 223                         MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1       0x11
 224                         MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2       0x11
 225                         MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3       0x11
 226                         MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x11
 227                         MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC       0x11
 228                         MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0       0x11
 229                         MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1       0x11
 230                         MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2       0x11
 231                         MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3       0x11
 232                         MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x11
 233                 >;
 234         };
 235
 236         pinctrl_enet2: enet2grp {
 237                 fsl,pins = <
 238                         MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC             0x11
 239                         MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0            0x11
 240                         MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1            0x11
 241                         MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2            0x11
 242                         MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3             0x11
 243                         MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL          0x11
 244                         MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC            0x11
 245                         MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0            0x11
 246                         MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1             0x11
 247                         MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2             0x11
 248                         MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3            0x11
 249                         MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL         0x11
 250                 >;
 251         };
 252
 253         pinctrl_i2c2: i2c2grp {
 254                 fsl,pins = <
 255                         MX7D_PAD_I2C2_SDA__I2C2_SDA             0x4000007f
 256                         MX7D_PAD_I2C2_SCL__I2C2_SCL             0x4000007f
 257                 >;
 258         };
 259
 260         pinctrl_uart1: uart1grp {
 261                 fsl,pins = <
 262                         MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX    0x79
 263                         MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX    0x79
 264                 >;
 265         };
 266
 267         pinctrl_usdhc3: usdhc3grp {
 268                 fsl,pins = <
 269                         MX7D_PAD_SD3_CMD__SD3_CMD               0x59
 270                         MX7D_PAD_SD3_CLK__SD3_CLK               0x19
 271                         MX7D_PAD_SD3_DATA0__SD3_DATA0           0x59
 272                         MX7D_PAD_SD3_DATA1__SD3_DATA1           0x59
 273                         MX7D_PAD_SD3_DATA2__SD3_DATA2           0x59
 274                         MX7D_PAD_SD3_DATA3__SD3_DATA3           0x59
 275                         MX7D_PAD_SD3_DATA4__SD3_DATA4           0x59
 276                         MX7D_PAD_SD3_DATA5__SD3_DATA5           0x59
 277                         MX7D_PAD_SD3_DATA6__SD3_DATA6           0x59
 278                         MX7D_PAD_SD3_DATA7__SD3_DATA7           0x59
 279                         MX7D_PAD_SD3_STROBE__SD3_STROBE         0x19
 280                 >;
 281         };
 282 };
 283
 284 &iomuxc_lpsr {
 285         pinctrl_usbotg1: usbotg1grp {
 286                 fsl,pins = <
 287                         MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5     0x14 /* OTG PWREN */
 288                 >;
 289         };
 290 };