arch/arm/boot/dts/imx7-colibri.dtsi

   1 /*
   2  * Copyright 2016 Toradex AG
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 / {
  44         bl: backlight {
  45                 compatible = "pwm-backlight";
  46                 pinctrl-names = "default";
  47                 pinctrl-0 = <&pinctrl_gpio_bl_on>;
  48                 pwms = <&pwm1 0 5000000 0>;
  49                 enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
  50         };
  51
  52         reg_module_3v3: regulator-module-3v3 {
  53                 compatible = "regulator-fixed";
  54                 regulator-name = "+V3.3";
  55                 regulator-min-microvolt = <3300000>;
  56                 regulator-max-microvolt = <3300000>;
  57                 regulator-always-on;
  58         };
  59
  60         reg_module_3v3_avdd: regulator-module-3v3-avdd {
  61                 compatible = "regulator-fixed";
  62                 regulator-name = "+V3.3_AVDD_AUDIO";
  63                 regulator-min-microvolt = <3300000>;
  64                 regulator-max-microvolt = <3300000>;
  65                 regulator-always-on;
  66         };
  67
  68         sound {
  69                 compatible = "simple-audio-card";
  70                 simple-audio-card,name = "imx7-sgtl5000";
  71                 simple-audio-card,format = "i2s";
  72                 simple-audio-card,bitclock-master = <&dailink_master>;
  73                 simple-audio-card,frame-master = <&dailink_master>;
  74                 simple-audio-card,cpu {
  75                         sound-dai = <&sai1>;
  76                 };
  77
  78                 dailink_master: simple-audio-card,codec {
  79                         sound-dai = <&codec>;
  80                         clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
  81                 };
  82         };
  83 };
  84
  85 &adc1 {
  86         vref-supply = <&reg_DCDC3>;
  87 };
  88
  89 &adc2 {
  90         vref-supply = <&reg_DCDC3>;
  91 };
  92
  93 &cpu0 {
  94         cpu-supply = <&reg_DCDC2>;
  95 };
  96
  97 &ecspi3 {
  98         pinctrl-names = "default";
  99         pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs>;
 100         cs-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>;
 101 };
 102
 103 &fec1 {
 104         pinctrl-names = "default", "sleep";
 105         pinctrl-0 = <&pinctrl_enet1>;
 106         pinctrl-1 = <&pinctrl_enet1_sleep>;
 107         clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
 108                 <&clks IMX7D_ENET_AXI_ROOT_CLK>,
 109                 <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
 110                 <&clks IMX7D_PLL_ENET_MAIN_50M_CLK>;
 111         clock-names = "ipg", "ahb", "ptp", "enet_clk_ref";
 112         assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
 113                           <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
 114         assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
 115         assigned-clock-rates = <0>, <100000000>;
 116         phy-mode = "rmii";
 117         phy-supply = <&reg_LDO1>;
 118         fsl,magic-packet;
 119 };
 120
 121 &flexcan1 {
 122         pinctrl-names = "default";
 123         pinctrl-0 = <&pinctrl_flexcan1>;
 124         status = "disabled";
 125 };
 126
 127 &flexcan2 {
 128         pinctrl-names = "default";
 129         pinctrl-0 = <&pinctrl_flexcan2>;
 130         status = "disabled";
 131 };
 132
 133 &gpmi {
 134         pinctrl-names = "default";
 135         pinctrl-0 = <&pinctrl_gpmi_nand>;
 136         fsl,use-minimum-ecc;
 137         nand-on-flash-bbt;
 138         nand-ecc-mode = "hw";
 139 };
 140
 141 &i2c1 {
 142         clock-frequency = <100000>;
 143         pinctrl-names = "default", "gpio";
 144         pinctrl-0 = <&pinctrl_i2c1 &pinctrl_i2c1_int>;
 145         pinctrl-1 = <&pinctrl_i2c1_recovery &pinctrl_i2c1_int>;
 146         scl-gpios = <&gpio1 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 147         sda-gpios = <&gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 148
 149         status = "okay";
 150
 151         codec: sgtl5000@a {
 152                 compatible = "fsl,sgtl5000";
 153                 #sound-dai-cells = <0>;
 154                 reg = <0x0a>;
 155                 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
 156                 pinctrl-names = "default";
 157                 pinctrl-0 = <&pinctrl_sai1_mclk>;
 158                 VDDA-supply = <&reg_module_3v3_avdd>;
 159                 VDDIO-supply = <&reg_module_3v3>;
 160                 VDDD-supply = <&reg_DCDC3>;
 161         };
 162
 163         ad7879@2c {
 164                 compatible = "adi,ad7879-1";
 165                 reg = <0x2c>;
 166                 interrupt-parent = <&gpio1>;
 167                 interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
 168                 touchscreen-max-pressure = <4096>;
 169                 adi,resistance-plate-x = <120>;
 170                 adi,first-conversion-delay = /bits/ 8 <3>;
 171                 adi,acquisition-time = /bits/ 8 <1>;
 172                 adi,median-filter-size = /bits/ 8 <2>;
 173                 adi,averaging = /bits/ 8 <1>;
 174                 adi,conversion-interval = /bits/ 8 <255>;
 175         };
 176
 177         pmic@33 {
 178                 compatible = "ricoh,rn5t567";
 179                 reg = <0x33>;
 180
 181                 regulators {
 182                         reg_DCDC1: DCDC1 {  /* V1.0_SOC */
 183                                 regulator-min-microvolt = <1000000>;
 184                                 regulator-max-microvolt = <1100000>;
 185                                 regulator-boot-on;
 186                                 regulator-always-on;
 187                         };
 188
 189                         reg_DCDC2: DCDC2 { /* V1.1_ARM */
 190                                 regulator-min-microvolt = <975000>;
 191                                 regulator-max-microvolt = <1100000>;
 192                                 regulator-boot-on;
 193                                 regulator-always-on;
 194                         };
 195
 196                         reg_DCDC3: DCDC3 { /* V1.8 */
 197                                 regulator-min-microvolt = <1800000>;
 198                                 regulator-max-microvolt = <1800000>;
 199                                 regulator-boot-on;
 200                                 regulator-always-on;
 201                         };
 202
 203                         reg_DCDC4: DCDC4 { /* V1.35_DRAM */
 204                                 regulator-min-microvolt = <1350000>;
 205                                 regulator-max-microvolt = <1350000>;
 206                                 regulator-boot-on;
 207                                 regulator-always-on;
 208                         };
 209
 210                         reg_LDO1: LDO1 { /* PWR_EN_+V3.3_ETH */
 211                                 regulator-min-microvolt = <1800000>;
 212                                 regulator-max-microvolt = <3300000>;
 213                                 regulator-boot-on;
 214                         };
 215
 216                         reg_LDO2: LDO2 { /* +V1.8_SD */
 217                                 regulator-min-microvolt = <1800000>;
 218                                 regulator-max-microvolt = <3300000>;
 219                                 regulator-boot-on;
 220                                 regulator-always-on;
 221                         };
 222
 223                         reg_LDO3: LDO3 { /* PWR_EN_+V3.3_LPSR */
 224                                 regulator-min-microvolt = <3300000>;
 225                                 regulator-max-microvolt = <3300000>;
 226                                 regulator-boot-on;
 227                                 regulator-always-on;
 228                         };
 229
 230                         reg_LDO4: LDO4 { /* V1.8_LPSR */
 231                                 regulator-min-microvolt = <1800000>;
 232                                 regulator-max-microvolt = <1800000>;
 233                                 regulator-boot-on;
 234                                 regulator-always-on;
 235                         };
 236
 237                         reg_LDO5: LDO5 { /* PWR_EN_+V3.3 */
 238                                 regulator-min-microvolt = <3300000>;
 239                                 regulator-max-microvolt = <3300000>;
 240                                 regulator-boot-on;
 241                                 regulator-always-on;
 242                         };
 243                 };
 244         };
 245 };
 246
 247 &i2c4 {
 248         clock-frequency = <100000>;
 249         pinctrl-names = "default", "gpio";
 250         pinctrl-0 = <&pinctrl_i2c4>;
 251         pinctrl-1 = <&pinctrl_i2c4_recovery>;
 252         scl-gpios = <&gpio7 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 253         sda-gpios = <&gpio7 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 254 };
 255
 256 &lcdif {
 257         pinctrl-names = "default";
 258         pinctrl-0 = <&pinctrl_lcdif_dat
 259                      &pinctrl_lcdif_ctrl>;
 260 };
 261
 262 &pwm1 {
 263         pinctrl-names = "default";
 264         pinctrl-0 = <&pinctrl_pwm1>;
 265 };
 266
 267 &pwm2 {
 268         pinctrl-names = "default";
 269         pinctrl-0 = <&pinctrl_pwm2>;
 270 };
 271
 272 &pwm3 {
 273         pinctrl-names = "default";
 274         pinctrl-0 = <&pinctrl_pwm3>;
 275 };
 276
 277 &pwm4 {
 278         pinctrl-names = "default";
 279         pinctrl-0 = <&pinctrl_pwm4>;
 280 };
 281
 282 &reg_1p0d {
 283         vin-supply = <&reg_DCDC3>;
 284 };
 285
 286 &sai1 {
 287         pinctrl-names = "default";
 288         pinctrl-0 = <&pinctrl_sai1>;
 289         status = "okay";
 290 };
 291
 292 &uart1 {
 293         pinctrl-names = "default";
 294         pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1 &pinctrl_uart1_ctrl2>;
 295         assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
 296         assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
 297         uart-has-rtscts;
 298         fsl,dte-mode;
 299 };
 300
 301 &uart2 {
 302         pinctrl-names = "default";
 303         pinctrl-0 = <&pinctrl_uart2>;
 304         assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>;
 305         assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
 306         uart-has-rtscts;
 307         fsl,dte-mode;
 308 };
 309
 310 &uart3 {
 311         pinctrl-names = "default";
 312         pinctrl-0 = <&pinctrl_uart3>;
 313         assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
 314         assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
 315         fsl,dte-mode;
 316 };
 317
 318 &usbotg1 {
 319         dr_mode = "host";
 320 };
 321
 322 &usdhc1 {
 323         pinctrl-names = "default";
 324         pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>;
 325         no-1-8-v;
 326         cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
 327         disable-wp;
 328         vqmmc-supply = <&reg_LDO2>;
 329 };
 330
 331 &usdhc3 {
 332         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 333         pinctrl-0 = <&pinctrl_usdhc3>;
 334         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 335         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 336         assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
 337         assigned-clock-rates = <400000000>;
 338         bus-width = <8>;
 339         fsl,tuning-step = <2>;
 340         max-frequency = <100000000>;
 341         vmmc-supply = <&reg_module_3v3>;
 342         vqmmc-supply = <&reg_DCDC3>;
 343         non-removable;
 344         sdhci-caps-mask = <0x80000000 0x0>;
 345 };
 346
 347 &iomuxc {
 348         pinctrl-names = "default";
 349         pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 &pinctrl_gpio4
 350                      &pinctrl_gpio7>;
 351
 352         pinctrl_gpio1: gpio1-grp {
 353                 fsl,pins = <
 354                         MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16       0x14 /* SODIMM 77 */
 355                         MX7D_PAD_EPDC_DATA09__GPIO2_IO9         0x14 /* SODIMM 89 */
 356                         MX7D_PAD_EPDC_DATA08__GPIO2_IO8         0x74 /* SODIMM 91 */
 357                         MX7D_PAD_LCD_RESET__GPIO3_IO4           0x14 /* SODIMM 93 */
 358                         MX7D_PAD_EPDC_DATA13__GPIO2_IO13        0x14 /* SODIMM 95 */
 359                         MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11    0x14 /* SODIMM 99 */
 360                         MX7D_PAD_EPDC_DATA10__GPIO2_IO10        0x74 /* SODIMM 105 */
 361                         MX7D_PAD_EPDC_DATA15__GPIO2_IO15        0x74 /* SODIMM 107 */
 362                         MX7D_PAD_EPDC_DATA00__GPIO2_IO0         0x14 /* SODIMM 111 */
 363                         MX7D_PAD_EPDC_DATA01__GPIO2_IO1         0x14 /* SODIMM 113 */
 364                         MX7D_PAD_EPDC_DATA02__GPIO2_IO2         0x14 /* SODIMM 115 */
 365                         MX7D_PAD_EPDC_DATA03__GPIO2_IO3         0x14 /* SODIMM 117 */
 366                         MX7D_PAD_EPDC_DATA04__GPIO2_IO4         0x14 /* SODIMM 119 */
 367                         MX7D_PAD_EPDC_DATA05__GPIO2_IO5         0x14 /* SODIMM 121 */
 368                         MX7D_PAD_EPDC_DATA06__GPIO2_IO6         0x14 /* SODIMM 123 */
 369                         MX7D_PAD_EPDC_DATA07__GPIO2_IO7         0x14 /* SODIMM 125 */
 370                         MX7D_PAD_EPDC_SDCE2__GPIO2_IO22         0x14 /* SODIMM 127 */
 371                         MX7D_PAD_UART3_RTS_B__GPIO4_IO6         0x14 /* SODIMM 131 */
 372                         MX7D_PAD_EPDC_GDRL__GPIO2_IO26          0x14 /* SODIMM 133 */
 373                         MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12       0x14 /* SODIMM 169 */
 374                         MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17       0x14 /* SODIMM 24 */
 375                         MX7D_PAD_SD2_DATA2__GPIO5_IO16          0x14 /* SODIMM 100 */
 376                         MX7D_PAD_SD2_DATA3__GPIO5_IO17          0x14 /* SODIMM 102 */
 377                         MX7D_PAD_EPDC_GDSP__GPIO2_IO27          0x14 /* SODIMM 104 */
 378                         MX7D_PAD_EPDC_BDR0__GPIO2_IO28          0x74 /* SODIMM 106 */
 379                         MX7D_PAD_EPDC_BDR1__GPIO2_IO29          0x14 /* SODIMM 110 */
 380                         MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30       0x14 /* SODIMM 112 */
 381                         MX7D_PAD_EPDC_SDCLK__GPIO2_IO16         0x14 /* SODIMM 114 */
 382                         MX7D_PAD_EPDC_SDLE__GPIO2_IO17          0x14 /* SODIMM 116 */
 383                         MX7D_PAD_EPDC_SDOE__GPIO2_IO18          0x14 /* SODIMM 118 */
 384                         MX7D_PAD_EPDC_SDSHR__GPIO2_IO19         0x14 /* SODIMM 120 */
 385                         MX7D_PAD_EPDC_SDCE0__GPIO2_IO20         0x14 /* SODIMM 122 */
 386                         MX7D_PAD_EPDC_SDCE1__GPIO2_IO21         0x14 /* SODIMM 124 */
 387                         MX7D_PAD_EPDC_DATA14__GPIO2_IO14        0x14 /* SODIMM 126 */
 388                         MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31      0x14 /* SODIMM 128 */
 389                         MX7D_PAD_EPDC_SDCE3__GPIO2_IO23         0x14 /* SODIMM 130 */
 390                         MX7D_PAD_EPDC_GDCLK__GPIO2_IO24         0x14 /* SODIMM 132 */
 391                         MX7D_PAD_EPDC_GDOE__GPIO2_IO25          0x14 /* SODIMM 134 */
 392                         MX7D_PAD_EPDC_DATA12__GPIO2_IO12        0x14 /* SODIMM 150 */
 393                         MX7D_PAD_EPDC_DATA11__GPIO2_IO11        0x14 /* SODIMM 152 */
 394                         MX7D_PAD_SD2_CLK__GPIO5_IO12            0x14 /* SODIMM 184 */
 395                         MX7D_PAD_SD2_CMD__GPIO5_IO13            0x14 /* SODIMM 186 */
 396                 >;
 397         };
 398
 399         pinctrl_gpio2: gpio2-grp { /* On X22 Camera interface */
 400                 fsl,pins = <
 401                         MX7D_PAD_ECSPI2_SS0__GPIO4_IO23         0x14 /* SODIMM 65 */
 402                         MX7D_PAD_SD1_CD_B__GPIO5_IO0            0x74 /* SODIMM 69 */
 403                         MX7D_PAD_I2C4_SDA__GPIO4_IO15           0x14 /* SODIMM 75 */
 404                         MX7D_PAD_ECSPI1_MISO__GPIO4_IO18        0x14 /* SODIMM 79 */
 405                         MX7D_PAD_I2C3_SCL__GPIO4_IO12           0x14 /* SODIMM 81 */
 406                         MX7D_PAD_ECSPI2_MISO__GPIO4_IO22        0x14 /* SODIMM 85 */
 407                         MX7D_PAD_ECSPI1_SS0__GPIO4_IO19         0x14 /* SODIMM 97 */
 408                         MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16        0x14 /* SODIMM 101 */
 409                         MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17        0x14 /* SODIMM 103 */
 410                         MX7D_PAD_I2C3_SDA__GPIO4_IO13           0x14 /* SODIMM 94 */
 411                         MX7D_PAD_I2C4_SCL__GPIO4_IO14           0x14 /* SODIMM 96 */
 412                         MX7D_PAD_SD2_RESET_B__GPIO5_IO11        0x14 /* SODIMM 98 */
 413                 >;
 414         };
 415
 416         pinctrl_gpio3: gpio3-grp { /* LCD 18-23 */
 417                 fsl,pins = <
 418                         MX7D_PAD_LCD_DATA18__GPIO3_IO23         0x14 /* SODIMM 136 */
 419                         MX7D_PAD_LCD_DATA19__GPIO3_IO24         0x14 /* SODIMM 138 */
 420                         MX7D_PAD_LCD_DATA20__GPIO3_IO25         0x14 /* SODIMM 140 */
 421                         MX7D_PAD_LCD_DATA21__GPIO3_IO26         0x14 /* SODIMM 142 */
 422                         MX7D_PAD_LCD_DATA22__GPIO3_IO27         0x74 /* SODIMM 144 */
 423                         MX7D_PAD_LCD_DATA23__GPIO3_IO28         0x74 /* SODIMM 146 */
 424                 >;
 425         };
 426
 427         pinctrl_gpio4: gpio4-grp { /* Alternatively CAN2 */
 428                 fsl,pins = <
 429                         MX7D_PAD_GPIO1_IO15__GPIO1_IO15         0x14 /* SODIMM 178 */
 430                         MX7D_PAD_GPIO1_IO14__GPIO1_IO14         0x14 /* SODIMM 188 */
 431                 >;
 432         };
 433
 434         pinctrl_gpio7: gpio7-grp { /* Alternatively CAN1 */
 435                 fsl,pins = <
 436                         MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3     0x14 /* SODIMM 55 */
 437                         MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2     0x14 /* SODIMM 63 */
 438                 >;
 439         };
 440
 441         pinctrl_i2c1_int: i2c1-int-grp { /* PMIC / TOUCH */
 442                 fsl,pins = <
 443                         MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x79
 444                 >;
 445         };
 446
 447         pinctrl_can_int: can-int-grp {
 448                 fsl,pins = <
 449                         MX7D_PAD_SD1_RESET_B__GPIO5_IO2         0X14 /* SODIMM 73 */
 450                 >;
 451         };
 452
 453         pinctrl_enet1: enet1grp {
 454                 fsl,pins = <
 455                         MX7D_PAD_ENET1_CRS__GPIO7_IO14                  0x14
 456                         MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x73
 457                         MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0       0x73
 458                         MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1       0x73
 459                         MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER           0x73
 460
 461                         MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x73
 462                         MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0       0x73
 463                         MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1       0x73
 464                         MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1          0x73
 465                         MX7D_PAD_SD2_CD_B__ENET1_MDIO                   0x3
 466                         MX7D_PAD_SD2_WP__ENET1_MDC                      0x3
 467                 >;
 468         };
 469
 470         pinctrl_enet1_sleep: enet1sleepgrp {
 471                 fsl,pins = <
 472                         MX7D_PAD_ENET1_RGMII_RX_CTL__GPIO7_IO4          0x0
 473                         MX7D_PAD_ENET1_RGMII_RD0__GPIO7_IO0             0x0
 474                         MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1             0x0
 475                         MX7D_PAD_ENET1_RGMII_RXC__GPIO7_IO5             0x0
 476
 477                         MX7D_PAD_ENET1_RGMII_TX_CTL__GPIO7_IO10         0x0
 478                         MX7D_PAD_ENET1_RGMII_TD0__GPIO7_IO6             0x0
 479                         MX7D_PAD_ENET1_RGMII_TD1__GPIO7_IO7             0x0
 480                         MX7D_PAD_GPIO1_IO12__GPIO1_IO12                 0x0
 481                         MX7D_PAD_SD2_CD_B__GPIO5_IO9                    0x0
 482                         MX7D_PAD_SD2_WP__GPIO5_IO10                     0x0
 483                 >;
 484         };
 485
 486         pinctrl_ecspi3_cs: ecspi3-cs-grp {
 487                 fsl,pins = <
 488                         MX7D_PAD_I2C2_SDA__GPIO4_IO11           0x14
 489                 >;
 490         };
 491
 492         pinctrl_ecspi3: ecspi3-grp {
 493                 fsl,pins = <
 494                         MX7D_PAD_I2C1_SCL__ECSPI3_MISO          0x2
 495                         MX7D_PAD_I2C1_SDA__ECSPI3_MOSI          0x2
 496                         MX7D_PAD_I2C2_SCL__ECSPI3_SCLK          0x2
 497                 >;
 498         };
 499
 500         pinctrl_flexcan1: flexcan1-grp {
 501                 fsl,pins = <
 502                         MX7D_PAD_ENET1_RGMII_RD3__FLEXCAN1_TX   0x79 /* SODIMM 55 */
 503                         MX7D_PAD_ENET1_RGMII_RD2__FLEXCAN1_RX   0x79 /* SODIMM 63 */
 504                 >;
 505         };
 506
 507         pinctrl_flexcan2: flexcan2-grp {
 508                 fsl,pins = <
 509                         MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX        0x79 /* SODIMM 188 */
 510                         MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX        0x79 /* SODIMM 178 */
 511                 >;
 512         };
 513
 514         pinctrl_gpio_bl_on: gpio-bl-on {
 515                 fsl,pins = <
 516                         MX7D_PAD_SD1_WP__GPIO5_IO1              0x14 /* SODIMM 71 */
 517                 >;
 518         };
 519
 520         pinctrl_gpmi_nand: gpmi-nand-grp {
 521                 fsl,pins = <
 522                         MX7D_PAD_SD3_CLK__NAND_CLE              0x71
 523                         MX7D_PAD_SD3_CMD__NAND_ALE              0x71
 524                         MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B       0x71
 525                         MX7D_PAD_SAI1_TX_DATA__NAND_READY_B     0x74
 526                         MX7D_PAD_SD3_STROBE__NAND_RE_B          0x71
 527                         MX7D_PAD_SD3_RESET_B__NAND_WE_B         0x71
 528                         MX7D_PAD_SD3_DATA0__NAND_DATA00         0x71
 529                         MX7D_PAD_SD3_DATA1__NAND_DATA01         0x71
 530                         MX7D_PAD_SD3_DATA2__NAND_DATA02         0x71
 531                         MX7D_PAD_SD3_DATA3__NAND_DATA03         0x71
 532                         MX7D_PAD_SD3_DATA4__NAND_DATA04         0x71
 533                         MX7D_PAD_SD3_DATA5__NAND_DATA05         0x71
 534                         MX7D_PAD_SD3_DATA6__NAND_DATA06         0x71
 535                         MX7D_PAD_SD3_DATA7__NAND_DATA07         0x71
 536                 >;
 537         };
 538
 539         pinctrl_i2c4: i2c4-grp {
 540                 fsl,pins = <
 541                         MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA      0x4000007f
 542                         MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL      0x4000007f
 543                 >;
 544         };
 545
 546         pinctrl_i2c4_recovery: i2c4-recoverygrp {
 547                 fsl,pins = <
 548                         MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8     0x4000007f
 549                         MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9     0x4000007f
 550                 >;
 551         };
 552
 553         pinctrl_lcdif_dat: lcdif-dat-grp {
 554                 fsl,pins = <
 555                         MX7D_PAD_LCD_DATA00__LCD_DATA0          0x79
 556                         MX7D_PAD_LCD_DATA01__LCD_DATA1          0x79
 557                         MX7D_PAD_LCD_DATA02__LCD_DATA2          0x79
 558                         MX7D_PAD_LCD_DATA03__LCD_DATA3          0x79
 559                         MX7D_PAD_LCD_DATA04__LCD_DATA4          0x79
 560                         MX7D_PAD_LCD_DATA05__LCD_DATA5          0x79
 561                         MX7D_PAD_LCD_DATA06__LCD_DATA6          0x79
 562                         MX7D_PAD_LCD_DATA07__LCD_DATA7          0x79
 563                         MX7D_PAD_LCD_DATA08__LCD_DATA8          0x79
 564                         MX7D_PAD_LCD_DATA09__LCD_DATA9          0x79
 565                         MX7D_PAD_LCD_DATA10__LCD_DATA10         0x79
 566                         MX7D_PAD_LCD_DATA11__LCD_DATA11         0x79
 567                         MX7D_PAD_LCD_DATA12__LCD_DATA12         0x79
 568                         MX7D_PAD_LCD_DATA13__LCD_DATA13         0x79
 569                         MX7D_PAD_LCD_DATA14__LCD_DATA14         0x79
 570                         MX7D_PAD_LCD_DATA15__LCD_DATA15         0x79
 571                         MX7D_PAD_LCD_DATA16__LCD_DATA16         0x79
 572                         MX7D_PAD_LCD_DATA17__LCD_DATA17         0x79
 573                 >;
 574         };
 575
 576         pinctrl_lcdif_dat_24: lcdif-dat-24-grp {
 577                 fsl,pins = <
 578                         MX7D_PAD_LCD_DATA18__LCD_DATA18         0x79
 579                         MX7D_PAD_LCD_DATA19__LCD_DATA19         0x79
 580                         MX7D_PAD_LCD_DATA20__LCD_DATA20         0x79
 581                         MX7D_PAD_LCD_DATA21__LCD_DATA21         0x79
 582                         MX7D_PAD_LCD_DATA22__LCD_DATA22         0x79
 583                         MX7D_PAD_LCD_DATA23__LCD_DATA23         0x79
 584                 >;
 585         };
 586
 587         pinctrl_lcdif_ctrl: lcdif-ctrl-grp {
 588                 fsl,pins = <
 589                         MX7D_PAD_LCD_CLK__LCD_CLK               0x79
 590                         MX7D_PAD_LCD_ENABLE__LCD_ENABLE         0x79
 591                         MX7D_PAD_LCD_VSYNC__LCD_VSYNC           0x79
 592                         MX7D_PAD_LCD_HSYNC__LCD_HSYNC           0x79
 593                 >;
 594         };
 595
 596         pinctrl_pwm1: pwm1-grp {
 597                 fsl,pins = <
 598                         MX7D_PAD_GPIO1_IO08__PWM1_OUT           0x79
 599                         MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21        0x4
 600                 >;
 601         };
 602
 603         pinctrl_pwm2: pwm2-grp {
 604                 fsl,pins = <
 605                         MX7D_PAD_GPIO1_IO09__PWM2_OUT           0x79
 606                 >;
 607         };
 608
 609         pinctrl_pwm3: pwm3-grp {
 610                 fsl,pins = <
 611                         MX7D_PAD_GPIO1_IO10__PWM3_OUT           0x79
 612                 >;
 613         };
 614
 615         pinctrl_pwm4: pwm4-grp {
 616                 fsl,pins = <
 617                         MX7D_PAD_GPIO1_IO11__PWM4_OUT           0x79
 618                         MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20        0x4
 619                 >;
 620         };
 621
 622         pinctrl_uart1: uart1-grp {
 623                 fsl,pins = <
 624                         MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX    0x79
 625                         MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX    0x79
 626                         MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS    0x79
 627                         MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS    0x79
 628                 >;
 629         };
 630
 631         pinctrl_uart1_ctrl1: uart1-ctrl1-grp {
 632                 fsl,pins = <
 633                         MX7D_PAD_SD2_DATA1__GPIO5_IO15          0x14 /* DCD */
 634                         MX7D_PAD_SD2_DATA0__GPIO5_IO14          0x14 /* DTR */
 635                 >;
 636         };
 637
 638         pinctrl_uart2: uart2-grp {
 639                 fsl,pins = <
 640                         MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX 0x79
 641                         MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX 0x79
 642                         MX7D_PAD_SAI2_RX_DATA__UART2_DTE_RTS 0x79
 643                         MX7D_PAD_SAI2_TX_DATA__UART2_DTE_CTS 0x79
 644                 >;
 645         };
 646         pinctrl_uart3: uart3-grp {
 647                 fsl,pins = <
 648                         MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX 0x79
 649                         MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX 0x79
 650                 >;
 651         };
 652
 653         pinctrl_usbh_reg: gpio-usbh-vbus {
 654                 fsl,pins = <
 655                         MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 /* SODIMM 129 USBH PEN */
 656                 >;
 657         };
 658
 659         pinctrl_usdhc1: usdhc1-grp {
 660                 fsl,pins = <
 661                         MX7D_PAD_SD1_CMD__SD1_CMD       0x59
 662                         MX7D_PAD_SD1_CLK__SD1_CLK       0x19
 663                         MX7D_PAD_SD1_DATA0__SD1_DATA0   0x59
 664                         MX7D_PAD_SD1_DATA1__SD1_DATA1   0x59
 665                         MX7D_PAD_SD1_DATA2__SD1_DATA2   0x59
 666                         MX7D_PAD_SD1_DATA3__SD1_DATA3   0x59
 667                 >;
 668         };
 669
 670         pinctrl_usdhc3: usdhc3grp {
 671                 fsl,pins = <
 672                         MX7D_PAD_SD3_CMD__SD3_CMD               0x59
 673                         MX7D_PAD_SD3_CLK__SD3_CLK               0x19
 674                         MX7D_PAD_SD3_DATA0__SD3_DATA0           0x59
 675                         MX7D_PAD_SD3_DATA1__SD3_DATA1           0x59
 676                         MX7D_PAD_SD3_DATA2__SD3_DATA2           0x59
 677                         MX7D_PAD_SD3_DATA3__SD3_DATA3           0x59
 678                         MX7D_PAD_SD3_DATA4__SD3_DATA4           0x59
 679                         MX7D_PAD_SD3_DATA5__SD3_DATA5           0x59
 680                         MX7D_PAD_SD3_DATA6__SD3_DATA6           0x59
 681                         MX7D_PAD_SD3_DATA7__SD3_DATA7           0x59
 682                         MX7D_PAD_SD3_STROBE__SD3_STROBE         0x19
 683                 >;
 684         };
 685
 686         pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
 687                 fsl,pins = <
 688                         MX7D_PAD_SD3_CMD__SD3_CMD               0x5a
 689                         MX7D_PAD_SD3_CLK__SD3_CLK               0x1a
 690                         MX7D_PAD_SD3_DATA0__SD3_DATA0           0x5a
 691                         MX7D_PAD_SD3_DATA1__SD3_DATA1           0x5a
 692                         MX7D_PAD_SD3_DATA2__SD3_DATA2           0x5a
 693                         MX7D_PAD_SD3_DATA3__SD3_DATA3           0x5a
 694                         MX7D_PAD_SD3_DATA4__SD3_DATA4           0x5a
 695                         MX7D_PAD_SD3_DATA5__SD3_DATA5           0x5a
 696                         MX7D_PAD_SD3_DATA6__SD3_DATA6           0x5a
 697                         MX7D_PAD_SD3_DATA7__SD3_DATA7           0x5a
 698                         MX7D_PAD_SD3_STROBE__SD3_STROBE         0x1a
 699                 >;
 700         };
 701
 702         pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
 703                 fsl,pins = <
 704                         MX7D_PAD_SD3_CMD__SD3_CMD               0x5b
 705                         MX7D_PAD_SD3_CLK__SD3_CLK               0x1b
 706                         MX7D_PAD_SD3_DATA0__SD3_DATA0           0x5b
 707                         MX7D_PAD_SD3_DATA1__SD3_DATA1           0x5b
 708                         MX7D_PAD_SD3_DATA2__SD3_DATA2           0x5b
 709                         MX7D_PAD_SD3_DATA3__SD3_DATA3           0x5b
 710                         MX7D_PAD_SD3_DATA4__SD3_DATA4           0x5b
 711                         MX7D_PAD_SD3_DATA5__SD3_DATA5           0x5b
 712                         MX7D_PAD_SD3_DATA6__SD3_DATA6           0x5b
 713                         MX7D_PAD_SD3_DATA7__SD3_DATA7           0x5b
 714                         MX7D_PAD_SD3_STROBE__SD3_STROBE         0x1b
 715                 >;
 716         };
 717
 718         pinctrl_sai1: sai1-grp {
 719                 fsl,pins = <
 720                         MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK     0x1f
 721                         MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC     0x1f
 722                         MX7D_PAD_ENET1_COL__SAI1_TX_DATA0       0x30
 723                         MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0    0x1f
 724                 >;
 725         };
 726
 727         pinctrl_sai1_mclk: sai1grp_mclk {
 728                 fsl,pins = <
 729                         MX7D_PAD_SAI1_MCLK__SAI1_MCLK           0x1f
 730                 >;
 731         };
 732 };
 733
 734 &iomuxc_lpsr {
 735         pinctrl-names = "default";
 736         pinctrl-0 = <&pinctrl_gpio_lpsr>;
 737
 738         pinctrl_gpio_lpsr: gpio1-grp {
 739                 fsl,pins = <
 740                         MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1     0x59
 741                         MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2     0x59
 742                         MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3     0x59
 743                 >;
 744         };
 745
 746         pinctrl_i2c1: i2c1-grp {
 747                 fsl,pins = <
 748                         MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA      0x4000007f
 749                         MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL      0x4000007f
 750                 >;
 751         };
 752
 753         pinctrl_i2c1_recovery: i2c1-recoverygrp {
 754                 fsl,pins = <
 755                         MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4     0x4000007f
 756                         MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5     0x4000007f
 757                 >;
 758         };
 759
 760         pinctrl_cd_usdhc1: usdhc1-cd-grp {
 761                 fsl,pins = <
 762                         MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0     0x59 /* CD */
 763                 >;
 764         };
 765
 766         pinctrl_uart1_ctrl2: uart1-ctrl2-grp {
 767                 fsl,pins = <
 768                         MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7     0x14 /* DSR */
 769                         MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6     0x14 /* RI */
 770                 >;
 771         };
 772 };