arch/arm/boot/dts/imx6ul.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Copyright 2015 Freescale Semiconductor, Inc.
   4
   5 #include <dt-bindings/clock/imx6ul-clock.h>
   6 #include <dt-bindings/gpio/gpio.h>
   7 #include <dt-bindings/input/input.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include "imx6ul-pinfunc.h"
  10
  11 / {
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14         /*
  15          * The decompressor and also some bootloaders rely on a
  16          * pre-existing /chosen node to be available to insert the
  17          * command line and merge other ATAGS info.
  18          * Also for U-Boot there must be a pre-existing /memory node.
  19          */
  20         chosen {};
  21         memory { device_type = "memory"; };
  22
  23         aliases {
  24                 ethernet0 = &fec1;
  25                 ethernet1 = &fec2;
  26                 gpio0 = &gpio1;
  27                 gpio1 = &gpio2;
  28                 gpio2 = &gpio3;
  29                 gpio3 = &gpio4;
  30                 gpio4 = &gpio5;
  31                 i2c0 = &i2c1;
  32                 i2c1 = &i2c2;
  33                 i2c2 = &i2c3;
  34                 i2c3 = &i2c4;
  35                 mmc0 = &usdhc1;
  36                 mmc1 = &usdhc2;
  37                 serial0 = &uart1;
  38                 serial1 = &uart2;
  39                 serial2 = &uart3;
  40                 serial3 = &uart4;
  41                 serial4 = &uart5;
  42                 serial5 = &uart6;
  43                 serial6 = &uart7;
  44                 serial7 = &uart8;
  45                 sai1 = &sai1;
  46                 sai2 = &sai2;
  47                 sai3 = &sai3;
  48                 spi0 = &ecspi1;
  49                 spi1 = &ecspi2;
  50                 spi2 = &ecspi3;
  51                 spi3 = &ecspi4;
  52                 usbphy0 = &usbphy1;
  53                 usbphy1 = &usbphy2;
  54         };
  55
  56         cpus {
  57                 #address-cells = <1>;
  58                 #size-cells = <0>;
  59
  60                 cpu0: cpu@0 {
  61                         compatible = "arm,cortex-a7";
  62                         device_type = "cpu";
  63                         reg = <0>;
  64                         clock-latency = <61036>; /* two CLK32 periods */
  65                         #cooling-cells = <2>;
  66                         operating-points = <
  67                                 /* kHz  uV */
  68                                 696000  1275000
  69                                 528000  1175000
  70                                 396000  1025000
  71                                 198000  950000
  72                         >;
  73                         fsl,soc-operating-points = <
  74                                 /* KHz  uV */
  75                                 696000  1275000
  76                                 528000  1175000
  77                                 396000  1175000
  78                                 198000  1175000
  79                         >;
  80                         clocks = <&clks IMX6UL_CLK_ARM>,
  81                                  <&clks IMX6UL_CLK_PLL2_BUS>,
  82                                  <&clks IMX6UL_CLK_PLL2_PFD2>,
  83                                  <&clks IMX6UL_CA7_SECONDARY_SEL>,
  84                                  <&clks IMX6UL_CLK_STEP>,
  85                                  <&clks IMX6UL_CLK_PLL1_SW>,
  86                                  <&clks IMX6UL_CLK_PLL1_SYS>;
  87                         clock-names = "arm", "pll2_bus",  "pll2_pfd2_396m",
  88                                       "secondary_sel", "step", "pll1_sw",
  89                                       "pll1_sys";
  90                         arm-supply = <&reg_arm>;
  91                         soc-supply = <&reg_soc>;
  92                 };
  93         };
  94
  95         intc: interrupt-controller@a01000 {
  96                 compatible = "arm,gic-400", "arm,cortex-a7-gic";
  97                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  98                 #interrupt-cells = <3>;
  99                 interrupt-controller;
 100                 interrupt-parent = <&intc>;
 101                 reg = <0x00a01000 0x1000>,
 102                       <0x00a02000 0x2000>,
 103                       <0x00a04000 0x2000>,
 104                       <0x00a06000 0x2000>;
 105         };
 106
 107         timer {
 108                 compatible = "arm,armv7-timer";
 109                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 110                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 111                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 112                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 113                 interrupt-parent = <&intc>;
 114                 status = "disabled";
 115         };
 116
 117         ckil: clock-cli {
 118                 compatible = "fixed-clock";
 119                 #clock-cells = <0>;
 120                 clock-frequency = <32768>;
 121                 clock-output-names = "ckil";
 122         };
 123
 124         osc: clock-osc {
 125                 compatible = "fixed-clock";
 126                 #clock-cells = <0>;
 127                 clock-frequency = <24000000>;
 128                 clock-output-names = "osc";
 129         };
 130
 131         ipp_di0: clock-di0 {
 132                 compatible = "fixed-clock";
 133                 #clock-cells = <0>;
 134                 clock-frequency = <0>;
 135                 clock-output-names = "ipp_di0";
 136         };
 137
 138         ipp_di1: clock-di1 {
 139                 compatible = "fixed-clock";
 140                 #clock-cells = <0>;
 141                 clock-frequency = <0>;
 142                 clock-output-names = "ipp_di1";
 143         };
 144
 145         tempmon: tempmon {
 146                 compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon";
 147                 interrupt-parent = <&gpc>;
 148                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 149                 fsl,tempmon = <&anatop>;
 150                 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
 151                 nvmem-cell-names = "calib", "temp_grade";
 152                 clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;
 153         };
 154
 155         pmu {
 156                 compatible = "arm,cortex-a7-pmu";
 157                 interrupt-parent = <&gpc>;
 158                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 159                 status = "disabled";
 160         };
 161
 162         soc {
 163                 #address-cells = <1>;
 164                 #size-cells = <1>;
 165                 compatible = "simple-bus";
 166                 interrupt-parent = <&gpc>;
 167                 ranges;
 168
 169                 ocram: sram@900000 {
 170                         compatible = "mmio-sram";
 171                         reg = <0x00900000 0x20000>;
 172                 };
 173
 174                 dma_apbh: dma-apbh@1804000 {
 175                         compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
 176                         reg = <0x01804000 0x2000>;
 177                         interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
 178                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
 179                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
 180                                      <0 13 IRQ_TYPE_LEVEL_HIGH>;
 181                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
 182                         #dma-cells = <1>;
 183                         dma-channels = <4>;
 184                         clocks = <&clks IMX6UL_CLK_APBHDMA>;
 185                 };
 186
 187                 gpmi: gpmi-nand@1806000         {
 188                         compatible = "fsl,imx6q-gpmi-nand";
 189                         #address-cells = <1>;
 190                         #size-cells = <1>;
 191                         reg = <0x01806000 0x2000>, <0x01808000 0x2000>;
 192                         reg-names = "gpmi-nand", "bch";
 193                         interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
 194                         interrupt-names = "bch";
 195                         clocks = <&clks IMX6UL_CLK_GPMI_IO>,
 196                                  <&clks IMX6UL_CLK_GPMI_APB>,
 197                                  <&clks IMX6UL_CLK_GPMI_BCH>,
 198                                  <&clks IMX6UL_CLK_GPMI_BCH_APB>,
 199                                  <&clks IMX6UL_CLK_PER_BCH>;
 200                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
 201                                       "gpmi_bch_apb", "per1_bch";
 202                         dmas = <&dma_apbh 0>;
 203                         dma-names = "rx-tx";
 204                         status = "disabled";
 205                 };
 206
 207                 aips1: aips-bus@2000000 {
 208                         compatible = "fsl,aips-bus", "simple-bus";
 209                         #address-cells = <1>;
 210                         #size-cells = <1>;
 211                         reg = <0x02000000 0x100000>;
 212                         ranges;
 213
 214                         spba-bus@2000000 {
 215                                 compatible = "fsl,spba-bus", "simple-bus";
 216                                 #address-cells = <1>;
 217                                 #size-cells = <1>;
 218                                 reg = <0x02000000 0x40000>;
 219                                 ranges;
 220
 221                                 ecspi1: ecspi@2008000 {
 222                                         #address-cells = <1>;
 223                                         #size-cells = <0>;
 224                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 225                                         reg = <0x02008000 0x4000>;
 226                                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 227                                         clocks = <&clks IMX6UL_CLK_ECSPI1>,
 228                                                  <&clks IMX6UL_CLK_ECSPI1>;
 229                                         clock-names = "ipg", "per";
 230                                         status = "disabled";
 231                                 };
 232
 233                                 ecspi2: ecspi@200c000 {
 234                                         #address-cells = <1>;
 235                                         #size-cells = <0>;
 236                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 237                                         reg = <0x0200c000 0x4000>;
 238                                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 239                                         clocks = <&clks IMX6UL_CLK_ECSPI2>,
 240                                                  <&clks IMX6UL_CLK_ECSPI2>;
 241                                         clock-names = "ipg", "per";
 242                                         status = "disabled";
 243                                 };
 244
 245                                 ecspi3: ecspi@2010000 {
 246                                         #address-cells = <1>;
 247                                         #size-cells = <0>;
 248                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 249                                         reg = <0x02010000 0x4000>;
 250                                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 251                                         clocks = <&clks IMX6UL_CLK_ECSPI3>,
 252                                                  <&clks IMX6UL_CLK_ECSPI3>;
 253                                         clock-names = "ipg", "per";
 254                                         status = "disabled";
 255                                 };
 256
 257                                 ecspi4: ecspi@2014000 {
 258                                         #address-cells = <1>;
 259                                         #size-cells = <0>;
 260                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 261                                         reg = <0x02014000 0x4000>;
 262                                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 263                                         clocks = <&clks IMX6UL_CLK_ECSPI4>,
 264                                                  <&clks IMX6UL_CLK_ECSPI4>;
 265                                         clock-names = "ipg", "per";
 266                                         status = "disabled";
 267                                 };
 268
 269                                 uart7: serial@2018000 {
 270                                         compatible = "fsl,imx6ul-uart",
 271                                                      "fsl,imx6q-uart";
 272                                         reg = <0x02018000 0x4000>;
 273                                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 274                                         clocks = <&clks IMX6UL_CLK_UART7_IPG>,
 275                                                  <&clks IMX6UL_CLK_UART7_SERIAL>;
 276                                         clock-names = "ipg", "per";
 277                                         status = "disabled";
 278                                 };
 279
 280                                 uart1: serial@2020000 {
 281                                         compatible = "fsl,imx6ul-uart",
 282                                                      "fsl,imx6q-uart";
 283                                         reg = <0x02020000 0x4000>;
 284                                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 285                                         clocks = <&clks IMX6UL_CLK_UART1_IPG>,
 286                                                  <&clks IMX6UL_CLK_UART1_SERIAL>;
 287                                         clock-names = "ipg", "per";
 288                                         status = "disabled";
 289                                 };
 290
 291                                 uart8: serial@2024000 {
 292                                         compatible = "fsl,imx6ul-uart",
 293                                                      "fsl,imx6q-uart";
 294                                         reg = <0x02024000 0x4000>;
 295                                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 296                                         clocks = <&clks IMX6UL_CLK_UART8_IPG>,
 297                                                  <&clks IMX6UL_CLK_UART8_SERIAL>;
 298                                         clock-names = "ipg", "per";
 299                                         status = "disabled";
 300                                 };
 301
 302                                 sai1: sai@2028000 {
 303                                         #sound-dai-cells = <0>;
 304                                         compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
 305                                         reg = <0x02028000 0x4000>;
 306                                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 307                                         clocks = <&clks IMX6UL_CLK_SAI1_IPG>,
 308                                                  <&clks IMX6UL_CLK_SAI1>,
 309                                                  <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
 310                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 311                                         dmas = <&sdma 35 24 0>,
 312                                                <&sdma 36 24 0>;
 313                                         dma-names = "rx", "tx";
 314                                         status = "disabled";
 315                                 };
 316
 317                                 sai2: sai@202c000 {
 318                                         #sound-dai-cells = <0>;
 319                                         compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
 320                                         reg = <0x0202c000 0x4000>;
 321                                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 322                                         clocks = <&clks IMX6UL_CLK_SAI2_IPG>,
 323                                                  <&clks IMX6UL_CLK_SAI2>,
 324                                                  <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
 325                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 326                                         dmas = <&sdma 37 24 0>,
 327                                                <&sdma 38 24 0>;
 328                                         dma-names = "rx", "tx";
 329                                         status = "disabled";
 330                                 };
 331
 332                                 sai3: sai@2030000 {
 333                                         #sound-dai-cells = <0>;
 334                                         compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
 335                                         reg = <0x02030000 0x4000>;
 336                                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 337                                         clocks = <&clks IMX6UL_CLK_SAI3_IPG>,
 338                                                  <&clks IMX6UL_CLK_SAI3>,
 339                                                  <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
 340                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 341                                         dmas = <&sdma 39 24 0>,
 342                                                <&sdma 40 24 0>;
 343                                         dma-names = "rx", "tx";
 344                                         status = "disabled";
 345                                 };
 346                         };
 347
 348                         tsc: tsc@2040000 {
 349                                 compatible = "fsl,imx6ul-tsc";
 350                                 reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
 351                                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 352                                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 353                                 clocks = <&clks IMX6UL_CLK_IPG>,
 354                                          <&clks IMX6UL_CLK_ADC2>;
 355                                 clock-names = "tsc", "adc";
 356                                 status = "disabled";
 357                         };
 358
 359                         pwm1: pwm@2080000 {
 360                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 361                                 reg = <0x02080000 0x4000>;
 362                                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 363                                 clocks = <&clks IMX6UL_CLK_PWM1>,
 364                                          <&clks IMX6UL_CLK_PWM1>;
 365                                 clock-names = "ipg", "per";
 366                                 #pwm-cells = <2>;
 367                                 status = "disabled";
 368                         };
 369
 370                         pwm2: pwm@2084000 {
 371                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 372                                 reg = <0x02084000 0x4000>;
 373                                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 374                                 clocks = <&clks IMX6UL_CLK_PWM2>,
 375                                          <&clks IMX6UL_CLK_PWM2>;
 376                                 clock-names = "ipg", "per";
 377                                 #pwm-cells = <2>;
 378                                 status = "disabled";
 379                         };
 380
 381                         pwm3: pwm@2088000 {
 382                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 383                                 reg = <0x02088000 0x4000>;
 384                                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 385                                 clocks = <&clks IMX6UL_CLK_PWM3>,
 386                                          <&clks IMX6UL_CLK_PWM3>;
 387                                 clock-names = "ipg", "per";
 388                                 #pwm-cells = <2>;
 389                                 status = "disabled";
 390                         };
 391
 392                         pwm4: pwm@208c000 {
 393                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 394                                 reg = <0x0208c000 0x4000>;
 395                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 396                                 clocks = <&clks IMX6UL_CLK_PWM4>,
 397                                          <&clks IMX6UL_CLK_PWM4>;
 398                                 clock-names = "ipg", "per";
 399                                 #pwm-cells = <2>;
 400                                 status = "disabled";
 401                         };
 402
 403                         can1: flexcan@2090000 {
 404                                 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
 405                                 reg = <0x02090000 0x4000>;
 406                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 407                                 clocks = <&clks IMX6UL_CLK_CAN1_IPG>,
 408                                          <&clks IMX6UL_CLK_CAN1_SERIAL>;
 409                                 clock-names = "ipg", "per";
 410                                 status = "disabled";
 411                         };
 412
 413                         can2: flexcan@2094000 {
 414                                 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
 415                                 reg = <0x02094000 0x4000>;
 416                                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 417                                 clocks = <&clks IMX6UL_CLK_CAN2_IPG>,
 418                                          <&clks IMX6UL_CLK_CAN2_SERIAL>;
 419                                 clock-names = "ipg", "per";
 420                                 status = "disabled";
 421                         };
 422
 423                         gpt1: gpt@2098000 {
 424                                 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
 425                                 reg = <0x02098000 0x4000>;
 426                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 427                                 clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
 428                                          <&clks IMX6UL_CLK_GPT1_SERIAL>;
 429                                 clock-names = "ipg", "per";
 430                         };
 431
 432                         gpio1: gpio@209c000 {
 433                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 434                                 reg = <0x0209c000 0x4000>;
 435                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 436                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 437                                 clocks = <&clks IMX6UL_CLK_GPIO1>;
 438                                 gpio-controller;
 439                                 #gpio-cells = <2>;
 440                                 interrupt-controller;
 441                                 #interrupt-cells = <2>;
 442                                 gpio-ranges = <&iomuxc  0 23 10>, <&iomuxc 10 17 6>,
 443                                               <&iomuxc 16 33 16>;
 444                         };
 445
 446                         gpio2: gpio@20a0000 {
 447                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 448                                 reg = <0x020a0000 0x4000>;
 449                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 450                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 451                                 clocks = <&clks IMX6UL_CLK_GPIO2>;
 452                                 gpio-controller;
 453                                 #gpio-cells = <2>;
 454                                 interrupt-controller;
 455                                 #interrupt-cells = <2>;
 456                                 gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>;
 457                         };
 458
 459                         gpio3: gpio@20a4000 {
 460                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 461                                 reg = <0x020a4000 0x4000>;
 462                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 463                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 464                                 clocks = <&clks IMX6UL_CLK_GPIO3>;
 465                                 gpio-controller;
 466                                 #gpio-cells = <2>;
 467                                 interrupt-controller;
 468                                 #interrupt-cells = <2>;
 469                                 gpio-ranges = <&iomuxc 0 65 29>;
 470                         };
 471
 472                         gpio4: gpio@20a8000 {
 473                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 474                                 reg = <0x020a8000 0x4000>;
 475                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 476                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 477                                 clocks = <&clks IMX6UL_CLK_GPIO4>;
 478                                 gpio-controller;
 479                                 #gpio-cells = <2>;
 480                                 interrupt-controller;
 481                                 #interrupt-cells = <2>;
 482                                 gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>;
 483                         };
 484
 485                         gpio5: gpio@20ac000 {
 486                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 487                                 reg = <0x020ac000 0x4000>;
 488                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
 489                                              <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 490                                 clocks = <&clks IMX6UL_CLK_GPIO5>;
 491                                 gpio-controller;
 492                                 #gpio-cells = <2>;
 493                                 interrupt-controller;
 494                                 #interrupt-cells = <2>;
 495                                 gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>;
 496                         };
 497
 498                         fec2: ethernet@20b4000 {
 499                                 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
 500                                 reg = <0x020b4000 0x4000>;
 501                                 interrupt-names = "int0", "pps";
 502                                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 503                                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 504                                 clocks = <&clks IMX6UL_CLK_ENET>,
 505                                          <&clks IMX6UL_CLK_ENET_AHB>,
 506                                          <&clks IMX6UL_CLK_ENET_PTP>,
 507                                          <&clks IMX6UL_CLK_ENET2_REF_125M>,
 508                                          <&clks IMX6UL_CLK_ENET2_REF_125M>;
 509                                 clock-names = "ipg", "ahb", "ptp",
 510                                               "enet_clk_ref", "enet_out";
 511                                 fsl,num-tx-queues=<1>;
 512                                 fsl,num-rx-queues=<1>;
 513                                 status = "disabled";
 514                         };
 515
 516                         kpp: kpp@20b8000 {
 517                                 compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp", "fsl,imx21-kpp";
 518                                 reg = <0x020b8000 0x4000>;
 519                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 520                                 clocks = <&clks IMX6UL_CLK_KPP>;
 521                                 status = "disabled";
 522                         };
 523
 524                         wdog1: wdog@20bc000 {
 525                                 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
 526                                 reg = <0x020bc000 0x4000>;
 527                                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 528                                 clocks = <&clks IMX6UL_CLK_WDOG1>;
 529                         };
 530
 531                         wdog2: wdog@20c0000 {
 532                                 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
 533                                 reg = <0x020c0000 0x4000>;
 534                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 535                                 clocks = <&clks IMX6UL_CLK_WDOG2>;
 536                                 status = "disabled";
 537                         };
 538
 539                         clks: ccm@20c4000 {
 540                                 compatible = "fsl,imx6ul-ccm";
 541                                 reg = <0x020c4000 0x4000>;
 542                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 543                                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 544                                 #clock-cells = <1>;
 545                                 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
 546                                 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
 547                         };
 548
 549                         anatop: anatop@20c8000 {
 550                                 compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
 551                                              "syscon", "simple-bus";
 552                                 reg = <0x020c8000 0x1000>;
 553                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 554                                              <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 555                                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 556
 557                                 reg_3p0: regulator-3p0 {
 558                                         compatible = "fsl,anatop-regulator";
 559                                         regulator-name = "vdd3p0";
 560                                         regulator-min-microvolt = <2625000>;
 561                                         regulator-max-microvolt = <3400000>;
 562                                         anatop-reg-offset = <0x120>;
 563                                         anatop-vol-bit-shift = <8>;
 564                                         anatop-vol-bit-width = <5>;
 565                                         anatop-min-bit-val = <0>;
 566                                         anatop-min-voltage = <2625000>;
 567                                         anatop-max-voltage = <3400000>;
 568                                         anatop-enable-bit = <0>;
 569                                 };
 570
 571                                 reg_arm: regulator-vddcore {
 572                                         compatible = "fsl,anatop-regulator";
 573                                         regulator-name = "cpu";
 574                                         regulator-min-microvolt = <725000>;
 575                                         regulator-max-microvolt = <1450000>;
 576                                         regulator-always-on;
 577                                         anatop-reg-offset = <0x140>;
 578                                         anatop-vol-bit-shift = <0>;
 579                                         anatop-vol-bit-width = <5>;
 580                                         anatop-delay-reg-offset = <0x170>;
 581                                         anatop-delay-bit-shift = <24>;
 582                                         anatop-delay-bit-width = <2>;
 583                                         anatop-min-bit-val = <1>;
 584                                         anatop-min-voltage = <725000>;
 585                                         anatop-max-voltage = <1450000>;
 586                                 };
 587
 588                                 reg_soc: regulator-vddsoc {
 589                                         compatible = "fsl,anatop-regulator";
 590                                         regulator-name = "vddsoc";
 591                                         regulator-min-microvolt = <725000>;
 592                                         regulator-max-microvolt = <1450000>;
 593                                         regulator-always-on;
 594                                         anatop-reg-offset = <0x140>;
 595                                         anatop-vol-bit-shift = <18>;
 596                                         anatop-vol-bit-width = <5>;
 597                                         anatop-delay-reg-offset = <0x170>;
 598                                         anatop-delay-bit-shift = <28>;
 599                                         anatop-delay-bit-width = <2>;
 600                                         anatop-min-bit-val = <1>;
 601                                         anatop-min-voltage = <725000>;
 602                                         anatop-max-voltage = <1450000>;
 603                                 };
 604                         };
 605
 606                         usbphy1: usbphy@20c9000 {
 607                                 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
 608                                 reg = <0x020c9000 0x1000>;
 609                                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 610                                 clocks = <&clks IMX6UL_CLK_USBPHY1>;
 611                                 phy-3p0-supply = <&reg_3p0>;
 612                                 fsl,anatop = <&anatop>;
 613                         };
 614
 615                         usbphy2: usbphy@20ca000 {
 616                                 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
 617                                 reg = <0x020ca000 0x1000>;
 618                                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 619                                 clocks = <&clks IMX6UL_CLK_USBPHY2>;
 620                                 phy-3p0-supply = <&reg_3p0>;
 621                                 fsl,anatop = <&anatop>;
 622                         };
 623
 624                         snvs: snvs@20cc000 {
 625                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 626                                 reg = <0x020cc000 0x4000>;
 627
 628                                 snvs_rtc: snvs-rtc-lp {
 629                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 630                                         regmap = <&snvs>;
 631                                         offset = <0x34>;
 632                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 633                                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 634                                 };
 635
 636                                 snvs_poweroff: snvs-poweroff {
 637                                         compatible = "syscon-poweroff";
 638                                         regmap = <&snvs>;
 639                                         offset = <0x38>;
 640                                         value = <0x60>;
 641                                         mask = <0x60>;
 642                                         status = "disabled";
 643                                 };
 644
 645                                 snvs_pwrkey: snvs-powerkey {
 646                                         compatible = "fsl,sec-v4.0-pwrkey";
 647                                         regmap = <&snvs>;
 648                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 649                                         linux,keycode = <KEY_POWER>;
 650                                         wakeup-source;
 651                                 };
 652
 653                                 snvs_lpgpr: snvs-lpgpr {
 654                                         compatible = "fsl,imx6ul-snvs-lpgpr";
 655                                 };
 656                         };
 657
 658                         epit1: epit@20d0000 {
 659                                 reg = <0x020d0000 0x4000>;
 660                                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 661                         };
 662
 663                         epit2: epit@20d4000 {
 664                                 reg = <0x020d4000 0x4000>;
 665                                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 666                         };
 667
 668                         src: src@20d8000 {
 669                                 compatible = "fsl,imx6ul-src", "fsl,imx51-src";
 670                                 reg = <0x020d8000 0x4000>;
 671                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
 672                                              <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 673                                 #reset-cells = <1>;
 674                         };
 675
 676                         gpc: gpc@20dc000 {
 677                                 compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
 678                                 reg = <0x020dc000 0x4000>;
 679                                 interrupt-controller;
 680                                 #interrupt-cells = <3>;
 681                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 682                                 interrupt-parent = <&intc>;
 683                         };
 684
 685                         iomuxc: iomuxc@20e0000 {
 686                                 compatible = "fsl,imx6ul-iomuxc";
 687                                 reg = <0x020e0000 0x4000>;
 688                         };
 689
 690                         gpr: iomuxc-gpr@20e4000 {
 691                                 compatible = "fsl,imx6ul-iomuxc-gpr",
 692                                              "fsl,imx6q-iomuxc-gpr", "syscon";
 693                                 reg = <0x020e4000 0x4000>;
 694                         };
 695
 696                         gpt2: gpt@20e8000 {
 697                                 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
 698                                 reg = <0x020e8000 0x4000>;
 699                                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 700                                 clocks = <&clks IMX6UL_CLK_GPT2_BUS>,
 701                                          <&clks IMX6UL_CLK_GPT2_SERIAL>;
 702                                 clock-names = "ipg", "per";
 703                         };
 704
 705                         sdma: sdma@20ec000 {
 706                                 compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma",
 707                                              "fsl,imx35-sdma";
 708                                 reg = <0x020ec000 0x4000>;
 709                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 710                                 clocks = <&clks IMX6UL_CLK_SDMA>,
 711                                          <&clks IMX6UL_CLK_SDMA>;
 712                                 clock-names = "ipg", "ahb";
 713                                 #dma-cells = <3>;
 714                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 715                         };
 716
 717                         pwm5: pwm@20f0000 {
 718                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 719                                 reg = <0x020f0000 0x4000>;
 720                                 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 721                                 clocks = <&clks IMX6UL_CLK_PWM5>,
 722                                          <&clks IMX6UL_CLK_PWM5>;
 723                                 clock-names = "ipg", "per";
 724                                 #pwm-cells = <2>;
 725                                 status = "disabled";
 726                         };
 727
 728                         pwm6: pwm@20f4000 {
 729                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 730                                 reg = <0x020f4000 0x4000>;
 731                                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 732                                 clocks = <&clks IMX6UL_CLK_PWM6>,
 733                                          <&clks IMX6UL_CLK_PWM6>;
 734                                 clock-names = "ipg", "per";
 735                                 #pwm-cells = <2>;
 736                                 status = "disabled";
 737                         };
 738
 739                         pwm7: pwm@20f8000 {
 740                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 741                                 reg = <0x020f8000 0x4000>;
 742                                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 743                                 clocks = <&clks IMX6UL_CLK_PWM7>,
 744                                          <&clks IMX6UL_CLK_PWM7>;
 745                                 clock-names = "ipg", "per";
 746                                 #pwm-cells = <2>;
 747                                 status = "disabled";
 748                         };
 749
 750                         pwm8: pwm@20fc000 {
 751                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 752                                 reg = <0x020fc000 0x4000>;
 753                                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 754                                 clocks = <&clks IMX6UL_CLK_PWM8>,
 755                                          <&clks IMX6UL_CLK_PWM8>;
 756                                 clock-names = "ipg", "per";
 757                                 #pwm-cells = <2>;
 758                                 status = "disabled";
 759                         };
 760                 };
 761
 762                 aips2: aips-bus@2100000 {
 763                         compatible = "fsl,aips-bus", "simple-bus";
 764                         #address-cells = <1>;
 765                         #size-cells = <1>;
 766                         reg = <0x02100000 0x100000>;
 767                         ranges;
 768
 769                         crypto: caam@2140000 {
 770                                 compatible = "fsl,imx6ul-caam", "fsl,sec-v4.0";
 771                                 #address-cells = <1>;
 772                                 #size-cells = <1>;
 773                                 reg = <0x2140000 0x3c000>;
 774                                 ranges = <0 0x2140000 0x3c000>;
 775                                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 776                                 clocks = <&clks IMX6UL_CLK_CAAM_IPG>, <&clks IMX6UL_CLK_CAAM_ACLK>,
 777                                          <&clks IMX6UL_CLK_CAAM_MEM>;
 778                                 clock-names = "ipg", "aclk", "mem";
 779
 780                                 sec_jr0: jr0@1000 {
 781                                         compatible = "fsl,sec-v4.0-job-ring";
 782                                         reg = <0x1000 0x1000>;
 783                                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 784                                 };
 785
 786                                 sec_jr1: jr1@2000 {
 787                                         compatible = "fsl,sec-v4.0-job-ring";
 788                                         reg = <0x2000 0x1000>;
 789                                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 790                                 };
 791
 792                                 sec_jr2: jr2@3000 {
 793                                         compatible = "fsl,sec-v4.0-job-ring";
 794                                         reg = <0x3000 0x1000>;
 795                                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 796                                 };
 797                         };
 798
 799                         usbotg1: usb@2184000 {
 800                                 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
 801                                 reg = <0x02184000 0x200>;
 802                                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 803                                 clocks = <&clks IMX6UL_CLK_USBOH3>;
 804                                 fsl,usbphy = <&usbphy1>;
 805                                 fsl,usbmisc = <&usbmisc 0>;
 806                                 fsl,anatop = <&anatop>;
 807                                 ahb-burst-config = <0x0>;
 808                                 tx-burst-size-dword = <0x10>;
 809                                 rx-burst-size-dword = <0x10>;
 810                                 status = "disabled";
 811                         };
 812
 813                         usbotg2: usb@2184200 {
 814                                 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
 815                                 reg = <0x02184200 0x200>;
 816                                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 817                                 clocks = <&clks IMX6UL_CLK_USBOH3>;
 818                                 fsl,usbphy = <&usbphy2>;
 819                                 fsl,usbmisc = <&usbmisc 1>;
 820                                 ahb-burst-config = <0x0>;
 821                                 tx-burst-size-dword = <0x10>;
 822                                 rx-burst-size-dword = <0x10>;
 823                                 status = "disabled";
 824                         };
 825
 826                         usbmisc: usbmisc@2184800 {
 827                                 #index-cells = <1>;
 828                                 compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
 829                                 reg = <0x02184800 0x200>;
 830                         };
 831
 832                         fec1: ethernet@2188000 {
 833                                 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
 834                                 reg = <0x02188000 0x4000>;
 835                                 interrupt-names = "int0", "pps";
 836                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 837                                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 838                                 clocks = <&clks IMX6UL_CLK_ENET>,
 839                                          <&clks IMX6UL_CLK_ENET_AHB>,
 840                                          <&clks IMX6UL_CLK_ENET_PTP>,
 841                                          <&clks IMX6UL_CLK_ENET_REF>,
 842                                          <&clks IMX6UL_CLK_ENET_REF>;
 843                                 clock-names = "ipg", "ahb", "ptp",
 844                                               "enet_clk_ref", "enet_out";
 845                                 fsl,num-tx-queues=<1>;
 846                                 fsl,num-rx-queues=<1>;
 847                                 status = "disabled";
 848                         };
 849
 850                         usdhc1: usdhc@2190000 {
 851                                 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
 852                                 reg = <0x02190000 0x4000>;
 853                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 854                                 clocks = <&clks IMX6UL_CLK_USDHC1>,
 855                                          <&clks IMX6UL_CLK_USDHC1>,
 856                                          <&clks IMX6UL_CLK_USDHC1>;
 857                                 clock-names = "ipg", "ahb", "per";
 858                                 bus-width = <4>;
 859                                 status = "disabled";
 860                         };
 861
 862                         usdhc2: usdhc@2194000 {
 863                                 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
 864                                 reg = <0x02194000 0x4000>;
 865                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 866                                 clocks = <&clks IMX6UL_CLK_USDHC2>,
 867                                          <&clks IMX6UL_CLK_USDHC2>,
 868                                          <&clks IMX6UL_CLK_USDHC2>;
 869                                 clock-names = "ipg", "ahb", "per";
 870                                 bus-width = <4>;
 871                                 status = "disabled";
 872                         };
 873
 874                         adc1: adc@2198000 {
 875                                 compatible = "fsl,imx6ul-adc", "fsl,vf610-adc";
 876                                 reg = <0x02198000 0x4000>;
 877                                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 878                                 clocks = <&clks IMX6UL_CLK_ADC1>;
 879                                 num-channels = <2>;
 880                                 clock-names = "adc";
 881                                 fsl,adck-max-frequency = <30000000>, <40000000>,
 882                                                          <20000000>;
 883                                 status = "disabled";
 884                         };
 885
 886                         i2c1: i2c@21a0000 {
 887                                 #address-cells = <1>;
 888                                 #size-cells = <0>;
 889                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 890                                 reg = <0x021a0000 0x4000>;
 891                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 892                                 clocks = <&clks IMX6UL_CLK_I2C1>;
 893                                 status = "disabled";
 894                         };
 895
 896                         i2c2: i2c@21a4000 {
 897                                 #address-cells = <1>;
 898                                 #size-cells = <0>;
 899                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 900                                 reg = <0x021a4000 0x4000>;
 901                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 902                                 clocks = <&clks IMX6UL_CLK_I2C2>;
 903                                 status = "disabled";
 904                         };
 905
 906                         i2c3: i2c@21a8000 {
 907                                 #address-cells = <1>;
 908                                 #size-cells = <0>;
 909                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 910                                 reg = <0x021a8000 0x4000>;
 911                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 912                                 clocks = <&clks IMX6UL_CLK_I2C3>;
 913                                 status = "disabled";
 914                         };
 915
 916                         mmdc: mmdc@21b0000 {
 917                                 compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
 918                                 reg = <0x021b0000 0x4000>;
 919                         };
 920
 921                         ocotp: ocotp-ctrl@21bc000 {
 922                                 #address-cells = <1>;
 923                                 #size-cells = <1>;
 924                                 compatible = "fsl,imx6ul-ocotp", "syscon";
 925                                 reg = <0x021bc000 0x4000>;
 926                                 clocks = <&clks IMX6UL_CLK_OCOTP>;
 927
 928                                 tempmon_calib: calib@38 {
 929                                         reg = <0x38 4>;
 930                                 };
 931
 932                                 tempmon_temp_grade: temp-grade@20 {
 933                                         reg = <0x20 4>;
 934                                 };
 935                         };
 936
 937                         lcdif: lcdif@21c8000 {
 938                                 compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";
 939                                 reg = <0x021c8000 0x4000>;
 940                                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 941                                 clocks = <&clks IMX6UL_CLK_LCDIF_PIX>,
 942                                          <&clks IMX6UL_CLK_LCDIF_APB>,
 943                                          <&clks IMX6UL_CLK_DUMMY>;
 944                                 clock-names = "pix", "axi", "disp_axi";
 945                                 status = "disabled";
 946                         };
 947
 948                         qspi: qspi@21e0000 {
 949                                 #address-cells = <1>;
 950                                 #size-cells = <0>;
 951                                 compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";
 952                                 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
 953                                 reg-names = "QuadSPI", "QuadSPI-memory";
 954                                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 955                                 clocks = <&clks IMX6UL_CLK_QSPI>,
 956                                          <&clks IMX6UL_CLK_QSPI>;
 957                                 clock-names = "qspi_en", "qspi";
 958                                 status = "disabled";
 959                         };
 960
 961                         wdog3: wdog@21e4000 {
 962                                 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
 963                                 reg = <0x021e4000 0x4000>;
 964                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 965                                 clocks = <&clks IMX6UL_CLK_WDOG3>;
 966                                 status = "disabled";
 967                         };
 968
 969                         uart2: serial@21e8000 {
 970                                 compatible = "fsl,imx6ul-uart",
 971                                              "fsl,imx6q-uart";
 972                                 reg = <0x021e8000 0x4000>;
 973                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 974                                 clocks = <&clks IMX6UL_CLK_UART2_IPG>,
 975                                          <&clks IMX6UL_CLK_UART2_SERIAL>;
 976                                 clock-names = "ipg", "per";
 977                                 status = "disabled";
 978                         };
 979
 980                         uart3: serial@21ec000 {
 981                                 compatible = "fsl,imx6ul-uart",
 982                                              "fsl,imx6q-uart";
 983                                 reg = <0x021ec000 0x4000>;
 984                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 985                                 clocks = <&clks IMX6UL_CLK_UART3_IPG>,
 986                                          <&clks IMX6UL_CLK_UART3_SERIAL>;
 987                                 clock-names = "ipg", "per";
 988                                 status = "disabled";
 989                         };
 990
 991                         uart4: serial@21f0000 {
 992                                 compatible = "fsl,imx6ul-uart",
 993                                              "fsl,imx6q-uart";
 994                                 reg = <0x021f0000 0x4000>;
 995                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 996                                 clocks = <&clks IMX6UL_CLK_UART4_IPG>,
 997                                          <&clks IMX6UL_CLK_UART4_SERIAL>;
 998                                 clock-names = "ipg", "per";
 999                                 status = "disabled";
1000                         };
1001
1002                         uart5: serial@21f4000 {
1003                                 compatible = "fsl,imx6ul-uart",
1004                                              "fsl,imx6q-uart";
1005                                 reg = <0x021f4000 0x4000>;
1006                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1007                                 clocks = <&clks IMX6UL_CLK_UART5_IPG>,
1008                                          <&clks IMX6UL_CLK_UART5_SERIAL>;
1009                                 clock-names = "ipg", "per";
1010                                 status = "disabled";
1011                         };
1012
1013                         i2c4: i2c@21f8000 {
1014                                 #address-cells = <1>;
1015                                 #size-cells = <0>;
1016                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
1017                                 reg = <0x021f8000 0x4000>;
1018                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1019                                 clocks = <&clks IMX6UL_CLK_I2C4>;
1020                                 status = "disabled";
1021                         };
1022
1023                         uart6: serial@21fc000 {
1024                                 compatible = "fsl,imx6ul-uart",
1025                                              "fsl,imx6q-uart";
1026                                 reg = <0x021fc000 0x4000>;
1027                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1028                                 clocks = <&clks IMX6UL_CLK_UART6_IPG>,
1029                                          <&clks IMX6UL_CLK_UART6_SERIAL>;
1030                                 clock-names = "ipg", "per";
1031                                 status = "disabled";
1032                         };
1033                 };
1034         };
1035 };