arch/arm/boot/dts/imx6ul-tx6ul.dtsi

   1 /*
   2  * Copyright 2015 Lothar Waßmann <LW@KARO-electronics.de>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License
  11  *     version 2 as published by the Free Software Foundation.
  12  *
  13  *     This file is distributed in the hope that it will be useful,
  14  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *     GNU General Public License for more details.
  17  *
  18  * Or, alternatively,
  19  *
  20  *  b) Permission is hereby granted, free of charge, to any person
  21  *     obtaining a copy of this software and associated documentation
  22  *     files (the "Software"), to deal in the Software without
  23  *     restriction, including without limitation the rights to use,
  24  *     copy, modify, merge, publish, distribute, sublicense, and/or
  25  *     sell copies of the Software, and to permit persons to whom the
  26  *     Software is furnished to do so, subject to the following
  27  *     conditions:
  28  *
  29  *     The above copyright notice and this permission notice shall be
  30  *     included in all copies or substantial portions of the Software.
  31  *
  32  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  33  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  34  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  35  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  36  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  37  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  38  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  39  *     OTHER DEALINGS IN THE SOFTWARE.
  40  */
  41
  42 #include <dt-bindings/gpio/gpio.h>
  43 #include <dt-bindings/interrupt-controller/irq.h>
  44 #include <dt-bindings/pwm/pwm.h>
  45
  46 / {
  47         aliases {
  48                 can0 = &can2;
  49                 can1 = &can1;
  50                 display = &display;
  51                 i2c0 = &i2c2;
  52                 i2c1 = &i2c_gpio;
  53                 i2c2 = &i2c1;
  54                 i2c3 = &i2c3;
  55                 i2c4 = &i2c4;
  56                 lcdif-23bit-pins-a = &pinctrl_disp0_1;
  57                 lcdif-24bit-pins-a = &pinctrl_disp0_2;
  58                 pwm0 = &pwm5;
  59                 reg-can-xcvr = &reg_can_xcvr;
  60                 serial2 = &uart5;
  61                 serial4 = &uart3;
  62                 spi0 = &ecspi2;
  63                 spi1 = &spi_gpio;
  64                 stk5led = &user_led;
  65                 usbh1 = &usbotg2;
  66                 usbotg = &usbotg1;
  67         };
  68
  69         chosen {
  70                 stdout-path = &uart1;
  71         };
  72
  73         memory@80000000 {
  74                 device_type = "memory";
  75                 reg = <0x80000000 0>; /* will be filled by U-Boot */
  76         };
  77
  78         clocks {
  79                 mclk: mclk {
  80                         compatible = "fixed-clock";
  81                         #clock-cells = <0>;
  82                         clock-frequency = <26000000>;
  83                 };
  84         };
  85
  86         backlight: backlight {
  87                 compatible = "pwm-backlight";
  88                 pinctrl-names = "default";
  89                 pinctrl-0 = <&pinctrl_lcd_rst>;
  90                 enable-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
  91                 pwms = <&pwm5 0 500000 PWM_POLARITY_INVERTED>;
  92                 power-supply = <&reg_lcd_pwr>;
  93                 /*
  94                  * a poor man's way to create a 1:1 relationship between
  95                  * the PWM value and the actual duty cycle
  96                  */
  97                 brightness-levels = < 0  1  2  3  4  5  6  7  8  9
  98                                      10 11 12 13 14 15 16 17 18 19
  99                                      20 21 22 23 24 25 26 27 28 29
 100                                      30 31 32 33 34 35 36 37 38 39
 101                                      40 41 42 43 44 45 46 47 48 49
 102                                      50 51 52 53 54 55 56 57 58 59
 103                                      60 61 62 63 64 65 66 67 68 69
 104                                      70 71 72 73 74 75 76 77 78 79
 105                                      80 81 82 83 84 85 86 87 88 89
 106                                      90 91 92 93 94 95 96 97 98 99
 107                                     100>;
 108                 default-brightness-level = <50>;
 109         };
 110
 111         i2c_gpio: i2c-gpio {
 112                 compatible = "i2c-gpio";
 113                 #address-cells = <1>;
 114                 #size-cells = <0>;
 115                 pinctrl-names = "default";
 116                 pinctrl-0 = <&pinctrl_i2c_gpio>;
 117                 gpios = <
 118                         &gpio5 1 GPIO_ACTIVE_HIGH /* SDA */
 119                         &gpio5 0 GPIO_ACTIVE_HIGH /* SCL */
 120                 >;
 121                 clock-frequency = <400000>;
 122                 status = "okay";
 123
 124                 ds1339: rtc@68 {
 125                         compatible = "dallas,ds1339";
 126                         reg = <0x68>;
 127                         status = "disabled";
 128                 };
 129         };
 130
 131         leds {
 132                 compatible = "gpio-leds";
 133
 134                 user_led: user {
 135                         label = "Heartbeat";
 136                         pinctrl-names = "default";
 137                         pinctrl-0 = <&pinctrl_led>;
 138                         gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
 139                         linux,default-trigger = "heartbeat";
 140                 };
 141         };
 142
 143         reg_3v3_etn: regulator-3v3etn {
 144                 compatible = "regulator-fixed";
 145                 regulator-name = "3V3_ETN";
 146                 regulator-min-microvolt = <3300000>;
 147                 regulator-max-microvolt = <3300000>;
 148                 pinctrl-names = "default";
 149                 pinctrl-0 = <&pinctrl_etnphy_power>;
 150                 gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
 151                 enable-active-high;
 152         };
 153
 154         reg_2v5: regulator-2v5 {
 155                 compatible = "regulator-fixed";
 156                 regulator-name = "2V5";
 157                 regulator-min-microvolt = <2500000>;
 158                 regulator-max-microvolt = <2500000>;
 159                 regulator-always-on;
 160         };
 161
 162         reg_3v3: regulator-3v3 {
 163                 compatible = "regulator-fixed";
 164                 regulator-name = "3V3";
 165                 regulator-min-microvolt = <3300000>;
 166                 regulator-max-microvolt = <3300000>;
 167                 regulator-always-on;
 168         };
 169
 170         reg_can_xcvr: regulator-canxcvr {
 171                 compatible = "regulator-fixed";
 172                 regulator-name = "CAN XCVR";
 173                 regulator-min-microvolt = <3300000>;
 174                 regulator-max-microvolt = <3300000>;
 175                 pinctrl-names = "default";
 176                 pinctrl-0 = <&pinctrl_flexcan_xcvr>;
 177                 gpio = <&gpio3 5 GPIO_ACTIVE_LOW>;
 178         };
 179
 180         reg_lcd_pwr: regulator-lcdpwr {
 181                 compatible = "regulator-fixed";
 182                 regulator-name = "LCD POWER";
 183                 regulator-min-microvolt = <3300000>;
 184                 regulator-max-microvolt = <3300000>;
 185                 pinctrl-names = "default";
 186                 pinctrl-0 = <&pinctrl_lcd_pwr>;
 187                 gpio = <&gpio5 4 GPIO_ACTIVE_HIGH>;
 188                 enable-active-high;
 189                 regulator-boot-on;
 190                 regulator-always-on;
 191         };
 192
 193         reg_usbh1_vbus: regulator-usbh1vbus {
 194                 compatible = "regulator-fixed";
 195                 regulator-name = "usbh1_vbus";
 196                 regulator-min-microvolt = <5000000>;
 197                 regulator-max-microvolt = <5000000>;
 198                 pinctrl-names = "default";
 199                 pinctrl-0 = <&pinctrl_usbh1_vbus &pinctrl_usbh1_oc>;
 200                 gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
 201                 enable-active-high;
 202         };
 203
 204         reg_usbotg_vbus: regulator-usbotgvbus {
 205                 compatible = "regulator-fixed";
 206                 regulator-name = "usbotg_vbus";
 207                 regulator-min-microvolt = <5000000>;
 208                 regulator-max-microvolt = <5000000>;
 209                 pinctrl-names = "default";
 210                 pinctrl-0 = <&pinctrl_usbotg_vbus &pinctrl_usbotg_oc>;
 211                 gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
 212                 enable-active-high;
 213         };
 214
 215         spi_gpio: spi-gpio {
 216                 #address-cells = <1>;
 217                 #size-cells = <0>;
 218                 compatible = "spi-gpio";
 219                 pinctrl-names = "default";
 220                 pinctrl-0 = <&pinctrl_spi_gpio>;
 221                 gpio-mosi = <&gpio1 30 GPIO_ACTIVE_HIGH>;
 222                 gpio-miso = <&gpio1 31 GPIO_ACTIVE_HIGH>;
 223                 gpio-sck = <&gpio1 28 GPIO_ACTIVE_HIGH>;
 224                 num-chipselects = <2>;
 225                 cs-gpios = <
 226                         &gpio1 29 GPIO_ACTIVE_HIGH
 227                         &gpio1 10 GPIO_ACTIVE_HIGH
 228                 >;
 229                 status = "disabled";
 230
 231                 spi@0 {
 232                         compatible = "spidev";
 233                         reg = <0>;
 234                         spi-max-frequency = <660000>;
 235                 };
 236
 237                 spi@1 {
 238                         compatible = "spidev";
 239                         reg = <1>;
 240                         spi-max-frequency = <660000>;
 241                 };
 242         };
 243
 244         sound {
 245                 compatible = "karo,imx6ul-tx6ul-sgtl5000",
 246                              "simple-audio-card";
 247                 simple-audio-card,name = "imx6ul-tx6ul-sgtl5000-audio";
 248                 simple-audio-card,format = "i2s";
 249                 simple-audio-card,bitclock-master = <&codec_dai>;
 250                 simple-audio-card,frame-master = <&codec_dai>;
 251                 simple-audio-card,widgets =
 252                         "Microphone", "Mic Jack",
 253                         "Line", "Line In",
 254                         "Line", "Line Out",
 255                         "Headphone", "Headphone Jack";
 256                 simple-audio-card,routing =
 257                         "MIC_IN", "Mic Jack",
 258                         "Mic Jack", "Mic Bias",
 259                         "Headphone Jack", "HP_OUT";
 260
 261                 cpu_dai: simple-audio-card,cpu {
 262                         sound-dai = <&sai2>;
 263                 };
 264
 265                 codec_dai: simple-audio-card,codec {
 266                         sound-dai = <&sgtl5000>;
 267                 };
 268         };
 269 };
 270
 271 &can1 {
 272         pinctrl-names = "default";
 273         pinctrl-0 = <&pinctrl_flexcan1>;
 274         xceiver-supply = <&reg_can_xcvr>;
 275         status = "okay";
 276 };
 277
 278 &can2 {
 279         pinctrl-names = "default";
 280         pinctrl-0 = <&pinctrl_flexcan2>;
 281         xceiver-supply = <&reg_can_xcvr>;
 282         status = "okay";
 283 };
 284
 285 &ecspi2 {
 286         pinctrl-names = "default";
 287         pinctrl-0 = <&pinctrl_ecspi2>;
 288         cs-gpios = <
 289                 &gpio1 29 GPIO_ACTIVE_HIGH
 290                 &gpio1 10 GPIO_ACTIVE_HIGH
 291         >;
 292         status = "disabled";
 293
 294         spidev0: spi@0 {
 295                 compatible = "spidev";
 296                 reg = <0>;
 297                 spi-max-frequency = <60000000>;
 298         };
 299
 300         spidev1: spi@1 {
 301                 compatible = "spidev";
 302                 reg = <1>;
 303                 spi-max-frequency = <60000000>;
 304         };
 305 };
 306
 307 &fec1 {
 308         pinctrl-names = "default";
 309         pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio &pinctrl_etnphy0_rst>;
 310         phy-mode = "rmii";
 311         phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
 312         phy-supply = <&reg_3v3_etn>;
 313         phy-handle = <&etnphy0>;
 314         status = "okay";
 315
 316         mdio {
 317                 #address-cells = <1>;
 318                 #size-cells = <0>;
 319
 320                 etnphy0: ethernet-phy@0 {
 321                         compatible = "ethernet-phy-ieee802.3-c22";
 322                         reg = <0>;
 323                         pinctrl-names = "default";
 324                         pinctrl-0 = <&pinctrl_etnphy0_int>;
 325                         interrupt-parent = <&gpio5>;
 326                         interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
 327                         status = "okay";
 328                 };
 329
 330                 etnphy1: ethernet-phy@2 {
 331                         compatible = "ethernet-phy-ieee802.3-c22";
 332                         reg = <2>;
 333                         pinctrl-names = "default";
 334                         pinctrl-0 = <&pinctrl_etnphy1_int>;
 335                         interrupt-parent = <&gpio4>;
 336                         interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
 337                         status = "okay";
 338                 };
 339         };
 340 };
 341
 342 &fec2 {
 343         pinctrl-names = "default";
 344         pinctrl-0 = <&pinctrl_enet2 &pinctrl_etnphy1_rst>;
 345         phy-mode = "rmii";
 346         phy-reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
 347         phy-supply = <&reg_3v3_etn>;
 348         phy-handle = <&etnphy1>;
 349         status = "disabled";
 350 };
 351
 352 &gpmi {
 353         pinctrl-names = "default";
 354         pinctrl-0 = <&pinctrl_gpmi_nand>;
 355         nand-on-flash-bbt;
 356         fsl,no-blockmark-swap;
 357         status = "okay";
 358 };
 359
 360 &i2c2 {
 361         pinctrl-names = "default";
 362         pinctrl-0 = <&pinctrl_i2c2>;
 363         clock-frequency = <400000>;
 364         status = "okay";
 365
 366         sgtl5000: codec@a {
 367                 compatible = "fsl,sgtl5000";
 368                 reg = <0x0a>;
 369                 #sound-dai-cells = <0>;
 370                 VDDA-supply = <&reg_2v5>;
 371                 VDDIO-supply = <&reg_3v3>;
 372                 clocks = <&mclk>;
 373         };
 374
 375         polytouch: polytouch@38 {
 376                 compatible = "edt,edt-ft5x06";
 377                 reg = <0x38>;
 378                 pinctrl-names = "default";
 379                 pinctrl-0 = <&pinctrl_edt_ft5x06>;
 380                 interrupt-parent = <&gpio5>;
 381                 interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
 382                 reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
 383                 wake-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
 384                 wakeup-source;
 385         };
 386
 387         touchscreen: touchscreen@48 {
 388                 compatible = "ti,tsc2007";
 389                 reg = <0x48>;
 390                 pinctrl-names = "default";
 391                 pinctrl-0 = <&pinctrl_tsc2007>;
 392                 interrupt-parent = <&gpio3>;
 393                 interrupts = <26 IRQ_TYPE_NONE>;
 394                 gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
 395                 ti,x-plate-ohms = <660>;
 396                 wakeup-source;
 397         };
 398 };
 399
 400 &kpp {
 401         pinctrl-names = "default";
 402         pinctrl-0 = <&pinctrl_kpp>;
 403         /* sample keymap */
 404         /* row/col 0..3 are mapped to KPP row/col 4..7 */
 405         linux,keymap = <
 406                 MATRIX_KEY(4, 4, KEY_POWER)
 407                 MATRIX_KEY(4, 5, KEY_KP0)
 408                 MATRIX_KEY(4, 6, KEY_KP1)
 409                 MATRIX_KEY(4, 7, KEY_KP2)
 410                 MATRIX_KEY(5, 4, KEY_KP3)
 411                 MATRIX_KEY(5, 5, KEY_KP4)
 412                 MATRIX_KEY(5, 6, KEY_KP5)
 413                 MATRIX_KEY(5, 7, KEY_KP6)
 414                 MATRIX_KEY(6, 4, KEY_KP7)
 415                 MATRIX_KEY(6, 5, KEY_KP8)
 416                 MATRIX_KEY(6, 6, KEY_KP9)
 417         >;
 418         status = "okay";
 419 };
 420
 421 &lcdif {
 422         pinctrl-names = "default";
 423         pinctrl-0 = <&pinctrl_disp0_1>;
 424         lcd-supply = <&reg_lcd_pwr>;
 425         display = <&display>;
 426         status = "okay";
 427
 428         display: disp0 {
 429                 bits-per-pixel = <32>;
 430                 bus-width = <24>;
 431                 status = "okay";
 432
 433                 display-timings {
 434                         VGA {
 435                                 clock-frequency = <25200000>;
 436                                 hactive = <640>;
 437                                 vactive = <480>;
 438                                 hback-porch = <48>;
 439                                 hsync-len = <96>;
 440                                 hfront-porch = <16>;
 441                                 vback-porch = <31>;
 442                                 vsync-len = <2>;
 443                                 vfront-porch = <12>;
 444                                 hsync-active = <0>;
 445                                 vsync-active = <0>;
 446                                 de-active = <1>;
 447                                 pixelclk-active = <1>;
 448                         };
 449
 450                         ETV570 {
 451                                 clock-frequency = <25200000>;
 452                                 hactive = <640>;
 453                                 vactive = <480>;
 454                                 hback-porch = <114>;
 455                                 hsync-len = <30>;
 456                                 hfront-porch = <16>;
 457                                 vback-porch = <32>;
 458                                 vsync-len = <3>;
 459                                 vfront-porch = <10>;
 460                                 hsync-active = <0>;
 461                                 vsync-active = <0>;
 462                                 de-active = <1>;
 463                                 pixelclk-active = <1>;
 464                         };
 465
 466                         ET0350 {
 467                                 clock-frequency = <6413760>;
 468                                 hactive = <320>;
 469                                 vactive = <240>;
 470                                 hback-porch = <34>;
 471                                 hsync-len = <34>;
 472                                 hfront-porch = <20>;
 473                                 vback-porch = <15>;
 474                                 vsync-len = <3>;
 475                                 vfront-porch = <4>;
 476                                 hsync-active = <0>;
 477                                 vsync-active = <0>;
 478                                 de-active = <1>;
 479                                 pixelclk-active = <1>;
 480                         };
 481
 482                         ET0430 {
 483                                 clock-frequency = <9009000>;
 484                                 hactive = <480>;
 485                                 vactive = <272>;
 486                                 hback-porch = <2>;
 487                                 hsync-len = <41>;
 488                                 hfront-porch = <2>;
 489                                 vback-porch = <2>;
 490                                 vsync-len = <10>;
 491                                 vfront-porch = <2>;
 492                                 hsync-active = <0>;
 493                                 vsync-active = <0>;
 494                                 de-active = <1>;
 495                                 pixelclk-active = <0>;
 496                         };
 497
 498                         ET0500 {
 499                                 clock-frequency = <33264000>;
 500                                 hactive = <800>;
 501                                 vactive = <480>;
 502                                 hback-porch = <88>;
 503                                 hsync-len = <128>;
 504                                 hfront-porch = <40>;
 505                                 vback-porch = <33>;
 506                                 vsync-len = <2>;
 507                                 vfront-porch = <10>;
 508                                 hsync-active = <0>;
 509                                 vsync-active = <0>;
 510                                 de-active = <1>;
 511                                 pixelclk-active = <1>;
 512                         };
 513
 514                         ET0700 { /* same as ET0500 */
 515                                 clock-frequency = <33264000>;
 516                                 hactive = <800>;
 517                                 vactive = <480>;
 518                                 hback-porch = <88>;
 519                                 hsync-len = <128>;
 520                                 hfront-porch = <40>;
 521                                 vback-porch = <33>;
 522                                 vsync-len = <2>;
 523                                 vfront-porch = <10>;
 524                                 hsync-active = <0>;
 525                                 vsync-active = <0>;
 526                                 de-active = <1>;
 527                                 pixelclk-active = <1>;
 528                         };
 529
 530                         ETQ570 {
 531                                 clock-frequency = <6596040>;
 532                                 hactive = <320>;
 533                                 vactive = <240>;
 534                                 hback-porch = <38>;
 535                                 hsync-len = <30>;
 536                                 hfront-porch = <30>;
 537                                 vback-porch = <16>;
 538                                 vsync-len = <3>;
 539                                 vfront-porch = <4>;
 540                                 hsync-active = <0>;
 541                                 vsync-active = <0>;
 542                                 de-active = <1>;
 543                                 pixelclk-active = <1>;
 544                         };
 545                 };
 546         };
 547 };
 548
 549 &pwm5 {
 550         pinctrl-names = "default";
 551         pinctrl-0 = <&pinctrl_pwm5>;
 552         #pwm-cells = <3>;
 553         status = "okay";
 554 };
 555
 556 &sai2 {
 557         pinctrl-names = "default";
 558         pinctrl-0 = <&pinctrl_sai2>;
 559         status = "okay";
 560 };
 561
 562 &uart1 {
 563         pinctrl-names = "default";
 564         pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>;
 565         uart-has-rtscts;
 566         status = "okay";
 567 };
 568
 569 &uart2 {
 570         pinctrl-names = "default";
 571         pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>;
 572         uart-has-rtscts;
 573         status = "okay";
 574 };
 575
 576 &uart5 {
 577         pinctrl-names = "default";
 578         pinctrl-0 = <&pinctrl_uart5 &pinctrl_uart5_rtscts>;
 579         uart-has-rtscts;
 580         status = "okay";
 581 };
 582
 583 &usbotg1 {
 584         vbus-supply = <&reg_usbotg_vbus>;
 585         dr_mode = "peripheral";
 586         disable-over-current;
 587         status = "okay";
 588 };
 589
 590 &usbotg2 {
 591         vbus-supply = <&reg_usbh1_vbus>;
 592         dr_mode = "host";
 593         disable-over-current;
 594         status = "okay";
 595 };
 596
 597 &usdhc1 {
 598         pinctrl-names = "default";
 599         pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_usdhc1_cd>;
 600         bus-width = <4>;
 601         no-1-8-v;
 602         cd-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
 603         fsl,wp-controller;
 604         status = "okay";
 605 };
 606
 607 &iomuxc {
 608         pinctrl-names = "default";
 609         pinctrl-0 = <&pinctrl_hog>;
 610
 611         pinctrl_hog: hoggrp {
 612         };
 613
 614         pinctrl_led: ledgrp {
 615                 fsl,pins = <
 616                         MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09      0x0b0b0 /* LED */
 617                 >;
 618         };
 619
 620         pinctrl_disp0_1: disp0grp-1 {
 621                 fsl,pins = <
 622                         MX6UL_PAD_LCD_CLK__LCDIF_CLK            0x10 /* LSCLK */
 623                         MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE      0x10 /* OE_ACD */
 624                         MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC        0x10 /* HSYNC */
 625                         MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC        0x10 /* VSYNC */
 626                         /* PAD DISP0_DAT0 is used for the Flexcan transceiver control on STK5-v5 */
 627                         MX6UL_PAD_LCD_DATA01__LCDIF_DATA01      0x10
 628                         MX6UL_PAD_LCD_DATA02__LCDIF_DATA02      0x10
 629                         MX6UL_PAD_LCD_DATA03__LCDIF_DATA03      0x10
 630                         MX6UL_PAD_LCD_DATA04__LCDIF_DATA04      0x10
 631                         MX6UL_PAD_LCD_DATA05__LCDIF_DATA05      0x10
 632                         MX6UL_PAD_LCD_DATA06__LCDIF_DATA06      0x10
 633                         MX6UL_PAD_LCD_DATA07__LCDIF_DATA07      0x10
 634                         MX6UL_PAD_LCD_DATA08__LCDIF_DATA08      0x10
 635                         MX6UL_PAD_LCD_DATA09__LCDIF_DATA09      0x10
 636                         MX6UL_PAD_LCD_DATA10__LCDIF_DATA10      0x10
 637                         MX6UL_PAD_LCD_DATA11__LCDIF_DATA11      0x10
 638                         MX6UL_PAD_LCD_DATA12__LCDIF_DATA12      0x10
 639                         MX6UL_PAD_LCD_DATA13__LCDIF_DATA13      0x10
 640                         MX6UL_PAD_LCD_DATA14__LCDIF_DATA14      0x10
 641                         MX6UL_PAD_LCD_DATA15__LCDIF_DATA15      0x10
 642                         MX6UL_PAD_LCD_DATA16__LCDIF_DATA16      0x10
 643                         MX6UL_PAD_LCD_DATA17__LCDIF_DATA17      0x10
 644                         MX6UL_PAD_LCD_DATA18__LCDIF_DATA18      0x10
 645                         MX6UL_PAD_LCD_DATA19__LCDIF_DATA19      0x10
 646                         MX6UL_PAD_LCD_DATA20__LCDIF_DATA20      0x10
 647                         MX6UL_PAD_LCD_DATA21__LCDIF_DATA21      0x10
 648                         MX6UL_PAD_LCD_DATA22__LCDIF_DATA22      0x10
 649                         MX6UL_PAD_LCD_DATA23__LCDIF_DATA23      0x10
 650                 >;
 651         };
 652
 653         pinctrl_disp0_2: disp0grp-2 {
 654                 fsl,pins = <
 655                         MX6UL_PAD_LCD_CLK__LCDIF_CLK            0x10 /* LSCLK */
 656                         MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE      0x10 /* OE_ACD */
 657                         MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC        0x10 /* HSYNC */
 658                         MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC        0x10 /* VSYNC */
 659                         MX6UL_PAD_LCD_DATA00__LCDIF_DATA00      0x10
 660                         MX6UL_PAD_LCD_DATA01__LCDIF_DATA01      0x10
 661                         MX6UL_PAD_LCD_DATA02__LCDIF_DATA02      0x10
 662                         MX6UL_PAD_LCD_DATA03__LCDIF_DATA03      0x10
 663                         MX6UL_PAD_LCD_DATA04__LCDIF_DATA04      0x10
 664                         MX6UL_PAD_LCD_DATA05__LCDIF_DATA05      0x10
 665                         MX6UL_PAD_LCD_DATA06__LCDIF_DATA06      0x10
 666                         MX6UL_PAD_LCD_DATA07__LCDIF_DATA07      0x10
 667                         MX6UL_PAD_LCD_DATA08__LCDIF_DATA08      0x10
 668                         MX6UL_PAD_LCD_DATA09__LCDIF_DATA09      0x10
 669                         MX6UL_PAD_LCD_DATA10__LCDIF_DATA10      0x10
 670                         MX6UL_PAD_LCD_DATA11__LCDIF_DATA11      0x10
 671                         MX6UL_PAD_LCD_DATA12__LCDIF_DATA12      0x10
 672                         MX6UL_PAD_LCD_DATA13__LCDIF_DATA13      0x10
 673                         MX6UL_PAD_LCD_DATA14__LCDIF_DATA14      0x10
 674                         MX6UL_PAD_LCD_DATA15__LCDIF_DATA15      0x10
 675                         MX6UL_PAD_LCD_DATA16__LCDIF_DATA16      0x10
 676                         MX6UL_PAD_LCD_DATA17__LCDIF_DATA17      0x10
 677                         MX6UL_PAD_LCD_DATA18__LCDIF_DATA18      0x10
 678                         MX6UL_PAD_LCD_DATA19__LCDIF_DATA19      0x10
 679                         MX6UL_PAD_LCD_DATA20__LCDIF_DATA20      0x10
 680                         MX6UL_PAD_LCD_DATA21__LCDIF_DATA21      0x10
 681                         MX6UL_PAD_LCD_DATA22__LCDIF_DATA22      0x10
 682                         MX6UL_PAD_LCD_DATA23__LCDIF_DATA23      0x10
 683                 >;
 684         };
 685
 686         pinctrl_ecspi2: ecspi2grp {
 687                 fsl,pins = <
 688                         MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29     0x0b0b0 /* CSPI_SS */
 689                         MX6UL_PAD_JTAG_MOD__GPIO1_IO10          0x0b0b0 /* CSPI_SS */
 690                         MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI    0x0b0b0 /* CSPI_MOSI */
 691                         MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO    0x0b0b0 /* CSPI_MISO */
 692                         MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK    0x0b0b0 /* CSPI_SCLK */
 693                 >;
 694         };
 695
 696         pinctrl_edt_ft5x06: edt-ft5x06grp {
 697                 fsl,pins = <
 698                         MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02      0x1b0b0 /* Interrupt */
 699                         MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03      0x1b0b0 /* Reset */
 700                         MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08      0x1b0b0 /* Wake */
 701                 >;
 702         };
 703
 704         pinctrl_enet1: enet1grp {
 705                 fsl,pins = <
 706                         MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x000b0
 707                         MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x000b0
 708                         MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x000b0
 709                         MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER      0x000b0
 710                         MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x000b0
 711                         MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x000b0
 712                         MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x000b0
 713                         MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x400000b1
 714                 >;
 715         };
 716
 717         pinctrl_enet2: enet2grp {
 718                 fsl,pins = <
 719                         MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x000b0
 720                         MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x000b0
 721                         MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN      0x000b0
 722                         MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER      0x000b0
 723                         MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN      0x000b0
 724                         MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x000b0
 725                         MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x000b0
 726                         MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2  0x400000b1
 727                 >;
 728         };
 729
 730         pinctrl_enet1_mdio: enet1-mdiogrp {
 731                 fsl,pins = <
 732                         MX6UL_PAD_GPIO1_IO07__ENET1_MDC         0x0b0b0
 733                         MX6UL_PAD_GPIO1_IO06__ENET1_MDIO        0x1b0b0
 734                 >;
 735         };
 736
 737         pinctrl_etnphy_power: etnphy-pwrgrp {
 738                 fsl,pins = <
 739                         MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07      0x0b0b0 /* ETN PHY POWER */
 740                 >;
 741         };
 742
 743         pinctrl_etnphy0_int: etnphy-intgrp-0 {
 744                 fsl,pins = <
 745                         MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05      0x0b0b0 /* ETN PHY INT */
 746                 >;
 747         };
 748
 749         pinctrl_etnphy0_rst: etnphy-rstgrp-0 {
 750                 fsl,pins = <
 751                         MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06      0x0b0b0 /* ETN PHY RESET */
 752                 >;
 753         };
 754
 755         pinctrl_etnphy1_int: etnphy-intgrp-1 {
 756                 fsl,pins = <
 757                         MX6UL_PAD_CSI_DATA06__GPIO4_IO27        0x0b0b0 /* ETN PHY INT */
 758                 >;
 759         };
 760
 761         pinctrl_etnphy1_rst: etnphy-rstgrp-1 {
 762                 fsl,pins = <
 763                         MX6UL_PAD_CSI_DATA07__GPIO4_IO28        0x0b0b0 /* ETN PHY RESET */
 764                 >;
 765         };
 766
 767         pinctrl_flexcan1: flexcan1grp {
 768                 fsl,pins = <
 769                         MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX      0x0b0b0
 770                         MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX      0x0b0b0
 771                 >;
 772         };
 773
 774         pinctrl_flexcan2: flexcan2grp {
 775                 fsl,pins = <
 776                         MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX      0x0b0b0
 777                         MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX      0x0b0b0
 778                 >;
 779         };
 780
 781         pinctrl_flexcan_xcvr: flexcan-xcvrgrp {
 782                 fsl,pins = <
 783                         MX6UL_PAD_LCD_DATA00__GPIO3_IO05        0x0b0b0 /* Flexcan XCVR enable */
 784                 >;
 785         };
 786
 787         pinctrl_gpmi_nand: gpminandgrp {
 788                 fsl,pins = <
 789                         MX6UL_PAD_NAND_CLE__RAWNAND_CLE         0x0b0b1
 790                         MX6UL_PAD_NAND_ALE__RAWNAND_ALE         0x0b0b1
 791                         MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B       0x0b0b1
 792                         MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
 793                         MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B     0x0b0b1
 794                         MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B       0x0b0b1
 795                         MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B       0x0b0b1
 796                         MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00   0x0b0b1
 797                         MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01   0x0b0b1
 798                         MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02   0x0b0b1
 799                         MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03   0x0b0b1
 800                         MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04   0x0b0b1
 801                         MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05   0x0b0b1
 802                         MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06   0x0b0b1
 803                         MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07   0x0b0b1
 804                 >;
 805         };
 806
 807         pinctrl_i2c_gpio: i2c-gpiogrp {
 808                 fsl,pins = <
 809                         MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00      0x4001b8b1 /* I2C SCL */
 810                         MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01      0x4001b8b1 /* I2C SDA */
 811                 >;
 812         };
 813
 814         pinctrl_i2c2: i2c2grp {
 815                 fsl,pins = <
 816                         MX6UL_PAD_GPIO1_IO00__I2C2_SCL          0x4001b8b1
 817                         MX6UL_PAD_GPIO1_IO01__I2C2_SDA          0x4001b8b1
 818                 >;
 819         };
 820
 821         pinctrl_kpp: kppgrp {
 822                 fsl,pins = <
 823                         MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04     0x1b0b0
 824                         MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05     0x1b0b0
 825                         MX6UL_PAD_ENET2_TX_EN__KPP_COL06        0x1b0b0
 826                         MX6UL_PAD_ENET2_RX_ER__KPP_COL07        0x1b0b0
 827                         MX6UL_PAD_ENET2_RX_DATA0__KPP_ROW04     0x1b0b0
 828                         MX6UL_PAD_ENET2_RX_EN__KPP_ROW05        0x1b0b0
 829                         MX6UL_PAD_ENET2_TX_DATA1__KPP_ROW06     0x1b0b0
 830                         MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07       0x1b0b0
 831                 >;
 832         };
 833
 834         pinctrl_lcd_pwr: lcd-pwrgrp {
 835                 fsl,pins = <
 836                         MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04      0x0b0b0 /* LCD Power Enable */
 837                 >;
 838         };
 839
 840         pinctrl_lcd_rst: lcd-rstgrp {
 841                 fsl,pins = <
 842                         MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x0b0b0 /* LCD Reset */
 843                 >;
 844         };
 845
 846         pinctrl_pwm5: pwm5grp {
 847                 fsl,pins = <
 848                         MX6UL_PAD_NAND_DQS__PWM5_OUT            0x0b0b0
 849                 >;
 850         };
 851
 852         pinctrl_sai2: sai2grp {
 853                 fsl,pins = <
 854                         MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA        0x0b0b0 /* SSI1_RXD */
 855                         MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA     0x0b0b0 /* SSI1_TXD */
 856                         MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK        0x0b0b0 /* SSI1_CLK */
 857                         MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC        0x0b0b0 /* SSI1_FS */
 858                 >;
 859         };
 860
 861         pinctrl_spi_gpio: spi-gpiogrp {
 862                 fsl,pins = <
 863                         MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29     0x0b0b0 /* CSPI_SS */
 864                         MX6UL_PAD_JTAG_MOD__GPIO1_IO10          0x0b0b0 /* CSPI_SS */
 865                         MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30     0x0b0b0 /* CSPI_MOSI */
 866                         MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31     0x0b0b0 /* CSPI_MISO */
 867                         MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28     0x0b0b0 /* CSPI_SCLK */
 868                 >;
 869         };
 870
 871         pinctrl_tsc2007: tsc2007grp {
 872                 fsl,pins = <
 873                         MX6UL_PAD_JTAG_TMS__GPIO1_IO11          0x1b0b0 /* Interrupt */
 874                 >;
 875         };
 876
 877         pinctrl_uart1: uart1grp {
 878                 fsl,pins = <
 879                         MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX   0x0b0b0
 880                         MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX   0x0b0b0
 881                 >;
 882         };
 883
 884         pinctrl_uart1_rtscts: uart1-rtsctsgrp {
 885                 fsl,pins = <
 886                         MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS    0x0b0b0
 887                         MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS    0x0b0b0
 888                 >;
 889         };
 890
 891         pinctrl_uart2: uart2grp {
 892                 fsl,pins = <
 893                         MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX   0x0b0b0
 894                         MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX   0x0b0b0
 895                 >;
 896         };
 897
 898         pinctrl_uart2_rtscts: uart2-rtsctsgrp {
 899                 fsl,pins = <
 900                         MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS  0x0b0b0
 901                         MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS  0x0b0b0
 902                 >;
 903         };
 904
 905         pinctrl_uart5: uart5grp {
 906                 fsl,pins = <
 907                         MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX      0x0b0b0
 908                         MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX      0x0b0b0
 909                 >;
 910         };
 911
 912         pinctrl_uart5_rtscts: uart5-rtsctsgrp {
 913                 fsl,pins = <
 914                         MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS     0x0b0b0
 915                         MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS     0x0b0b0
 916                 >;
 917         };
 918
 919         pinctrl_usbh1_oc: usbh1-ocgrp {
 920                 fsl,pins = <
 921                         MX6UL_PAD_GPIO1_IO03__GPIO1_IO03        0x17059 /* USBH1_OC */
 922                 >;
 923         };
 924
 925         pinctrl_usbh1_vbus: usbh1-vbusgrp {
 926                 fsl,pins = <
 927                         MX6UL_PAD_GPIO1_IO02__GPIO1_IO02        0x0b0b0 /* USBH1_VBUSEN */
 928                 >;
 929         };
 930
 931         pinctrl_usbotg_oc: usbotg-ocgrp {
 932                 fsl,pins = <
 933                         MX6UL_PAD_UART3_RTS_B__GPIO1_IO27       0x17059 /* USBOTG_OC */
 934                 >;
 935         };
 936
 937         pinctrl_usbotg_vbus: usbotg-vbusgrp {
 938                 fsl,pins = <
 939                         MX6UL_PAD_UART3_CTS_B__GPIO1_IO26       0x1b0b0 /* USBOTG_VBUSEN */
 940                 >;
 941         };
 942
 943         pinctrl_usdhc1: usdhc1grp {
 944                 fsl,pins = <
 945                         MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x070b1
 946                         MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x07099
 947                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x070b1
 948                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x070b1
 949                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x070b1
 950                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x070b1
 951                 >;
 952         };
 953
 954         pinctrl_usdhc1_cd: usdhc1cdgrp {
 955                 fsl,pins = <
 956                         MX6UL_PAD_NAND_CE1_B__GPIO4_IO14        0x170b0 /* SD1 CD */
 957                 >;
 958         };
 959
 960         pinctrl_usdhc2: usdhc2grp {
 961                 fsl,pins = <
 962                         MX6UL_PAD_NAND_WE_B__USDHC2_CMD         0x070b1
 963                         MX6UL_PAD_NAND_RE_B__USDHC2_CLK         0x070b1
 964                         MX6UL_PAD_NAND_DATA00__USDHC2_DATA0     0x070b1
 965                         MX6UL_PAD_NAND_DATA01__USDHC2_DATA1     0x070b1
 966                         MX6UL_PAD_NAND_DATA02__USDHC2_DATA2     0x070b1
 967                         MX6UL_PAD_NAND_DATA03__USDHC2_DATA3     0x070b1
 968                         /* eMMC RESET */
 969                         MX6UL_PAD_NAND_ALE__USDHC2_RESET_B      0x170b0
 970                 >;
 971         };
 972 };