arch/arm/boot/dts/imx6ul-opos6ul.dtsi

   1 /*
   2  * Copyright 2017 Armadeus Systems <support@armadeus.com>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of
  12  *     the License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  *     You should have received a copy of the GNU General Public
  20  *     License along with this file; if not, write to the Free
  21  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  22  *     MA 02110-1301 USA
  23  *
  24  * Or, alternatively,
  25  *
  26  *  b) Permission is hereby granted, free of charge, to any person
  27  *     obtaining a copy of this software and associated documentation
  28  *     files (the "Software"), to deal in the Software without
  29  *     restriction, including without limitation the rights to use,
  30  *     copy, modify, merge, publish, distribute, sublicense, and/or
  31  *     sell copies of the Software, and to permit persons to whom the
  32  *     Software is furnished to do so, subject to the following
  33  *     conditions:
  34  *
  35  *     The above copyright notice and this permission notice shall be
  36  *     included in all copies or substantial portions of the Software.
  37  *
  38  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  39  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  40  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  41  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  42  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  43  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  44  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  45  *     OTHER DEALINGS IN THE SOFTWARE.
  46  */
  47
  48 #include "imx6ul.dtsi"
  49
  50 / {
  51         memory@80000000 {
  52                 device_type = "memory";
  53                 reg = <0x80000000 0>; /* will be filled by U-Boot */
  54         };
  55
  56         reg_3v3: regulator-3v3 {
  57                 compatible = "regulator-fixed";
  58                 regulator-name = "3V3";
  59                 regulator-min-microvolt = <3300000>;
  60                 regulator-max-microvolt = <3300000>;
  61         };
  62
  63         usdhc3_pwrseq: usdhc3-pwrseq {
  64                 compatible = "mmc-pwrseq-simple";
  65                 reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
  66         };
  67 };
  68
  69 &fec1 {
  70         pinctrl-names = "default";
  71         pinctrl-0 = <&pinctrl_enet1>;
  72         phy-mode = "rmii";
  73         phy-reset-duration = <1>;
  74         phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
  75         phy-handle = <&ethphy1>;
  76         phy-supply = <&reg_3v3>;
  77         status = "okay";
  78
  79         mdio: mdio {
  80                 #address-cells = <1>;
  81                 #size-cells = <0>;
  82
  83                 ethphy1: ethernet-phy@1 {
  84                         compatible = "ethernet-phy-ieee802.3-c22";
  85                         reg = <1>;
  86                         interrupt-parent = <&gpio4>;
  87                         interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
  88                         status = "okay";
  89                 };
  90         };
  91 };
  92
  93 /* Bluetooth */
  94 &uart8 {
  95         pinctrl-names = "default";
  96         pinctrl-0 = <&pinctrl_uart8>;
  97         uart-has-rtscts;
  98         status = "okay";
  99 };
 100
 101 /* eMMC */
 102 &usdhc1 {
 103         pinctrl-names = "default";
 104         pinctrl-0 = <&pinctrl_usdhc1>;
 105         bus-width = <8>;
 106         no-1-8-v;
 107         non-removable;
 108         status = "okay";
 109 };
 110
 111 /* WiFi */
 112 &usdhc2 {
 113         pinctrl-names = "default";
 114         pinctrl-0 = <&pinctrl_usdhc2>;
 115         bus-width = <4>;
 116         no-1-8-v;
 117         non-removable;
 118         mmc-pwrseq = <&usdhc3_pwrseq>;
 119         status = "okay";
 120
 121         #address-cells = <1>;
 122         #size-cells = <0>;
 123
 124         brcmf: wifi@1 {
 125                 compatible = "brcm,bcm4329-fmac";
 126                 reg = <1>;
 127                 interrupt-parent = <&gpio2>;
 128                 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
 129                 interrupt-names = "host-wake";
 130         };
 131 };
 132
 133 &iomuxc {
 134         pinctrl_enet1: enet1grp {
 135                 fsl,pins = <
 136                         MX6UL_PAD_GPIO1_IO06__ENET1_MDIO        0x1b0b0
 137                         MX6UL_PAD_GPIO1_IO07__ENET1_MDC         0x1b0b0
 138                         MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER      0x130b0
 139                         MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x130b0
 140                         MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x130b0
 141                         MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x130b0
 142                         MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
 143                         MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
 144                         MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x1b0b0
 145                         /* INT# */
 146                         MX6UL_PAD_NAND_DQS__GPIO4_IO16          0x1b0b0
 147                         /* RST# */
 148                         MX6UL_PAD_NAND_DATA00__GPIO4_IO02       0x130b0
 149                         MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x4001b031
 150                 >;
 151         };
 152
 153         pinctrl_uart8: uart8grp {
 154                 fsl,pins = <
 155                         MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX     0x1b0b0
 156                         MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX  0x1b0b0
 157                         MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS    0x1b0b0
 158                         MX6UL_PAD_ENET2_TX_CLK__UART8_DCE_CTS   0x1b0b0
 159                         /* BT_REG_ON */
 160                         MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10       0x130b0
 161                 >;
 162         };
 163
 164         pinctrl_usdhc1: usdhc1grp {
 165                 fsl,pins = <
 166                         MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x17059
 167                         MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x10059
 168                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x17059
 169                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x17059
 170                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x17059
 171                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x17059
 172                         MX6UL_PAD_NAND_READY_B__USDHC1_DATA4    0x17059
 173                         MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5      0x17059
 174                         MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6      0x17059
 175                         MX6UL_PAD_NAND_CLE__USDHC1_DATA7        0x17059
 176                 >;
 177         };
 178
 179         pinctrl_usdhc2: usdhc2grp {
 180                 fsl,pins = <
 181                         MX6UL_PAD_LCD_DATA18__USDHC2_CMD        0x1b0b0
 182                         MX6UL_PAD_LCD_DATA19__USDHC2_CLK        0x100b0
 183                         MX6UL_PAD_LCD_DATA20__USDHC2_DATA0      0x1b0b0
 184                         MX6UL_PAD_LCD_DATA21__USDHC2_DATA1      0x1b0b0
 185                         MX6UL_PAD_LCD_DATA22__USDHC2_DATA2      0x1b0b0
 186                         MX6UL_PAD_LCD_DATA23__USDHC2_DATA3      0x1b0b0
 187                         /* WL_REG_ON */
 188                         MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09    0x130b0
 189                         /* WL_IRQ */
 190                         MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08    0x1b0b0
 191                 >;
 192         };
 193 };