arch/arm/boot/dts/imx6ul-isiot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0 OR X11
   2 /*
   3  * Copyright (C) 2016 Amarula Solutions B.V.
   4  * Copyright (C) 2016 Engicam S.r.l.
   5  */
   6
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/input/input.h>
   9 #include "imx6ul.dtsi"
  10
  11 / {
  12         memory@80000000 {
  13                 reg = <0x80000000 0x20000000>;
  14         };
  15
  16         chosen {
  17                 stdout-path = &uart1;
  18         };
  19
  20         backlight {
  21                 compatible = "pwm-backlight";
  22                 pwms = <&pwm8 0 100000>;
  23                 brightness-levels = < 0  1  2  3  4  5  6  7  8  9
  24                                      10 11 12 13 14 15 16 17 18 19
  25                                      20 21 22 23 24 25 26 27 28 29
  26                                      30 31 32 33 34 35 36 37 38 39
  27                                      40 41 42 43 44 45 46 47 48 49
  28                                      50 51 52 53 54 55 56 57 58 59
  29                                      60 61 62 63 64 65 66 67 68 69
  30                                      70 71 72 73 74 75 76 77 78 79
  31                                      80 81 82 83 84 85 86 87 88 89
  32                                      90 91 92 93 94 95 96 97 98 99
  33                                     100>;
  34                 default-brightness-level = <100>;
  35         };
  36
  37         reg_1p8v: regulator-1p8v {
  38                 compatible = "regulator-fixed";
  39                 regulator-name = "1P8V";
  40                 regulator-min-microvolt = <1800000>;
  41                 regulator-max-microvolt = <1800000>;
  42                 regulator-always-on;
  43                 regulator-boot-on;
  44         };
  45
  46         reg_3p3v: regulator-3p3v {
  47                 compatible = "regulator-fixed";
  48                 regulator-name = "3P3V";
  49                 regulator-min-microvolt = <3300000>;
  50                 regulator-max-microvolt = <3300000>;
  51                 regulator-always-on;
  52                 regulator-boot-on;
  53         };
  54
  55         sound {
  56                 compatible = "simple-audio-card";
  57                 simple-audio-card,name = "imx6ul-isiot-sgtl5000";
  58                 simple-audio-card,format = "i2s";
  59                 simple-audio-card,bitclock-master = <&dailink_master>;
  60                 simple-audio-card,frame-master = <&dailink_master>;
  61                 simple-audio-card,widgets =
  62                         "Microphone", "Mic Jack",
  63                         "Line", "Line In",
  64                         "Line", "Line Out",
  65                         "Headphone", "Headphone Jack";
  66                 simple-audio-card,routing =
  67                         "MIC_IN", "Mic Jack",
  68                         "Mic Jack", "Mic Bias",
  69                         "Headphone Jack", "HP_OUT";
  70
  71                 simple-audio-card,cpu {
  72                         sound-dai = <&sai2>;
  73                 };
  74
  75                 dailink_master: simple-audio-card,codec {
  76                         sound-dai = <&sgtl5000>;
  77                         clocks = <&clks IMX6UL_CLK_SAI2>;
  78                 };
  79         };
  80 };
  81
  82 &fec1 {
  83         pinctrl-names = "default";
  84         pinctrl-0 = <&pinctrl_enet1>;
  85         phy-mode = "rmii";
  86         phy-handle = <&ethphy0>;
  87         status = "okay";
  88
  89         mdio {
  90                 #address-cells = <1>;
  91                 #size-cells = <0>;
  92
  93                 ethphy0: ethernet-phy@0 {
  94                         compatible = "ethernet-phy-ieee802.3-c22";
  95                         reg = <0>;
  96                 };
  97         };
  98 };
  99
 100 &gpmi {
 101         pinctrl-names = "default";
 102         pinctrl-0 = <&pinctrl_gpmi_nand>;
 103         nand-on-flash-bbt;
 104         status = "disabled";
 105 };
 106
 107 &i2c1 {
 108         clock-frequency = <100000>;
 109         pinctrl-names = "default";
 110         pinctrl-0 = <&pinctrl_i2c1>;
 111         status = "okay";
 112
 113         sgtl5000: codec@a {
 114                 compatible = "fsl,sgtl5000";
 115                 reg = <0x0a>;
 116                 #sound-dai-cells = <0>;
 117                 clocks = <&clks IMX6UL_CLK_OSC>;
 118                 clock-names = "mclk";
 119                 VDDA-supply = <&reg_3p3v>;
 120                 VDDIO-supply = <&reg_3p3v>;
 121                 VDDD-supply = <&reg_1p8v>;
 122         };
 123
 124         stmpe811: gpio-expander@44 {
 125                 compatible = "st,stmpe811";
 126                 reg = <0x44>;
 127                 pinctrl-names = "default";
 128                 pinctrl-0 = <&pinctrl_stmpe>;
 129                 interrupt-parent = <&gpio1>;
 130                 interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
 131                 interrupt-controller;
 132                 #interrupt-cells = <2>;
 133
 134                 stmpe: touchscreen {
 135                         compatible = "st,stmpe-ts";
 136                         st,sample-time = <4>;
 137                         st,mod-12b = <1>;
 138                         st,ref-sel = <0>;
 139                         st,adc-freq = <1>;
 140                         st,ave-ctrl = <1>;
 141                         st,touch-det-delay = <2>;
 142                         st,settling = <2>;
 143                         st,fraction-z = <7>;
 144                         st,i-drive = <1>;
 145                 };
 146         };
 147 };
 148
 149 &i2c2 {
 150         clock_frequency = <100000>;
 151         pinctrl-names = "default";
 152         pinctrl-0 = <&pinctrl_i2c2>;
 153         status = "okay";
 154 };
 155
 156 &lcdif {
 157         pinctrl-names = "default";
 158         pinctrl-0 = <&pinctrl_lcdif_dat
 159                      &pinctrl_lcdif_ctrl>;
 160         display = <&display0>;
 161         status = "okay";
 162
 163         display0: display {
 164                 bits-per-pixel = <16>;
 165                 bus-width = <18>;
 166
 167                 display-timings {
 168                         native-mode = <&timing0>;
 169                         timing0: timing0 {
 170                                 clock-frequency = <28000000>;
 171                                 hactive = <800>;
 172                                 vactive = <480>;
 173                                 hfront-porch = <30>;
 174                                 hback-porch = <30>;
 175                                 hsync-len = <64>;
 176                                 vback-porch = <5>;
 177                                 vfront-porch = <5>;
 178                                 vsync-len = <20>;
 179                                 hsync-active = <0>;
 180                                 vsync-active = <0>;
 181                                 de-active = <1>;
 182                                 pixelclk-active = <0>;
 183                         };
 184                 };
 185         };
 186 };
 187
 188 &pwm8 {
 189         pinctrl-names = "default";
 190         pinctrl-0 = <&pinctrl_pwm8>;
 191         status = "okay";
 192 };
 193
 194 &sai2 {
 195         pinctrl-names = "default";
 196         pinctrl-0 = <&pinctrl_sai2>;
 197         status = "okay";
 198 };
 199
 200 &uart1 {
 201         pinctrl-names = "default";
 202         pinctrl-0 = <&pinctrl_uart1>;
 203         status = "okay";
 204 };
 205
 206 &usdhc1 {
 207         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 208         pinctrl-0 = <&pinctrl_usdhc1>;
 209         pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
 210         pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
 211         cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
 212         bus-width = <4>;
 213         no-1-8-v;
 214         status = "okay";
 215 };
 216
 217 &usdhc2 {
 218         pinctrl-names = "default";
 219         pinctrl-0 = <&pinctrl_usdhc2>;
 220         cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
 221         bus-width = <8>;
 222         no-1-8-v;
 223         status = "disabled";
 224 };
 225
 226 &iomuxc {
 227         pinctrl_enet1: enet1grp {
 228                 fsl,pins = <
 229                         MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO    0x1b0b0
 230                         MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC     0x1b0b0
 231                         MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x1b0b0
 232                         MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
 233                         MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
 234                         MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x1b0b0
 235                         MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
 236                         MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
 237                         MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x4001b031
 238                         MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10       0x1b0b0
 239                 >;
 240         };
 241
 242         pinctrl_gpmi_nand: gpminandgrp {
 243                 fsl,pins = <
 244                         MX6UL_PAD_NAND_CLE__RAWNAND_CLE         0xb0b1
 245                         MX6UL_PAD_NAND_ALE__RAWNAND_ALE         0xb0b1
 246                         MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B       0xb0b1
 247                         MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
 248                         MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B     0xb0b1
 249                         MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B       0xb0b1
 250                         MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B       0xb0b1
 251                         MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00   0xb0b1
 252                         MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01   0xb0b1
 253                         MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02   0xb0b1
 254                         MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03   0xb0b1
 255                         MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04   0xb0b1
 256                         MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05   0xb0b1
 257                         MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06   0xb0b1
 258                         MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07   0xb0b1
 259                 >;
 260         };
 261
 262         pinctrl_i2c1: i2c1grp {
 263                 fsl,pins = <
 264                         MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
 265                         MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
 266                 >;
 267         };
 268
 269         pinctrl_i2c2: i2c2grp {
 270                 fsl,pins = <
 271                         MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x4001b8b0
 272                         MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x4001b8b0
 273                 >;
 274         };
 275
 276         pinctrl_lcdif_ctrl: lcdifctrlgrp {
 277                 fsl,pins = <
 278                         MX6UL_PAD_LCD_CLK__LCDIF_CLK        0x79
 279                         MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE  0x79
 280                         MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x79
 281                         MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x79
 282                 >;
 283         };
 284
 285         pinctrl_lcdif_dat: lcdifdatgrp {
 286                 fsl,pins = <
 287                         MX6UL_PAD_LCD_DATA00__LCDIF_DATA00  0x79
 288                         MX6UL_PAD_LCD_DATA01__LCDIF_DATA01  0x79
 289                         MX6UL_PAD_LCD_DATA02__LCDIF_DATA02  0x79
 290                         MX6UL_PAD_LCD_DATA03__LCDIF_DATA03  0x79
 291                         MX6UL_PAD_LCD_DATA04__LCDIF_DATA04  0x79
 292                         MX6UL_PAD_LCD_DATA05__LCDIF_DATA05  0x79
 293                         MX6UL_PAD_LCD_DATA06__LCDIF_DATA06  0x79
 294                         MX6UL_PAD_LCD_DATA07__LCDIF_DATA07  0x79
 295                         MX6UL_PAD_LCD_DATA08__LCDIF_DATA08  0x79
 296                         MX6UL_PAD_LCD_DATA09__LCDIF_DATA09  0x79
 297                         MX6UL_PAD_LCD_DATA10__LCDIF_DATA10  0x79
 298                         MX6UL_PAD_LCD_DATA11__LCDIF_DATA11  0x79
 299                         MX6UL_PAD_LCD_DATA12__LCDIF_DATA12  0x79
 300                         MX6UL_PAD_LCD_DATA13__LCDIF_DATA13  0x79
 301                         MX6UL_PAD_LCD_DATA14__LCDIF_DATA14  0x79
 302                         MX6UL_PAD_LCD_DATA15__LCDIF_DATA15  0x79
 303                         MX6UL_PAD_LCD_DATA16__LCDIF_DATA16  0x79
 304                         MX6UL_PAD_LCD_DATA17__LCDIF_DATA17  0x79
 305                 >;
 306         };
 307
 308         pinctrl_pwm8: pwm8grp {
 309                 fsl,pins = <
 310                         MX6UL_PAD_ENET1_RX_ER__PWM8_OUT   0x110b0
 311                 >;
 312         };
 313
 314         pinctrl_sai2: sai2grp {
 315                 fsl,pins = <
 316                         MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA        0x130b0
 317                         MX6UL_PAD_JTAG_TMS__CCM_CLKO1           0x4001b031
 318                         MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK        0x17088
 319                         MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC        0x17088
 320                         MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA     0x120b0
 321                 >;
 322         };
 323
 324         pinctrl_stmpe: stmpegrp  {
 325                 fsl,pins = <
 326                         MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x1b0b0
 327                 >;
 328         };
 329
 330         pinctrl_uart1: uart1grp {
 331                 fsl,pins = <
 332                         MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
 333                         MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
 334                 >;
 335         };
 336
 337         pinctrl_usdhc1: usdhc1grp {
 338                 fsl,pins = <
 339                         MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x17059
 340                         MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x10059
 341                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
 342                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
 343                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
 344                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
 345                 >;
 346         };
 347
 348         pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
 349                 fsl,pins = <
 350                         MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170b9
 351                         MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100b9
 352                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
 353                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
 354                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
 355                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
 356                 >;
 357         };
 358
 359         pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
 360                 fsl,pins = <
 361                         MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170f9
 362                         MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100f9
 363                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
 364                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
 365                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
 366                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
 367                 >;
 368         };
 369
 370         pinctrl_usdhc2: usdhc2grp {
 371                 fsl,pins = <
 372                         MX6UL_PAD_NAND_RE_B__USDHC2_CLK      0x17070
 373                         MX6UL_PAD_NAND_WE_B__USDHC2_CMD      0x10070
 374                         MX6UL_PAD_NAND_DATA00__USDHC2_DATA0  0x17070
 375                         MX6UL_PAD_NAND_DATA01__USDHC2_DATA1  0x17070
 376                         MX6UL_PAD_NAND_DATA02__USDHC2_DATA2  0x17070
 377                         MX6UL_PAD_NAND_DATA03__USDHC2_DATA3  0x17070
 378                         MX6UL_PAD_NAND_DATA04__USDHC2_DATA4  0x17070
 379                         MX6UL_PAD_NAND_DATA05__USDHC2_DATA5  0x17070
 380                         MX6UL_PAD_NAND_DATA06__USDHC2_DATA6  0x17070
 381                         MX6UL_PAD_NAND_DATA07__USDHC2_DATA7  0x17070
 382                         MX6UL_PAD_NAND_ALE__USDHC2_RESET_B   0x17070
 383                 >;
 384         };
 385 };