arch/arm/boot/dts/imx6sl.dtsi

   1 /*
   2  * Copyright 2013 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  */
   9
  10 #include <dt-bindings/interrupt-controller/irq.h>
  11 #include "imx6sl-pinfunc.h"
  12 #include <dt-bindings/clock/imx6sl-clock.h>
  13
  14 / {
  15         #address-cells = <1>;
  16         #size-cells = <1>;
  17
  18         aliases {
  19                 ethernet0 = &fec;
  20                 gpio0 = &gpio1;
  21                 gpio1 = &gpio2;
  22                 gpio2 = &gpio3;
  23                 gpio3 = &gpio4;
  24                 gpio4 = &gpio5;
  25                 serial0 = &uart1;
  26                 serial1 = &uart2;
  27                 serial2 = &uart3;
  28                 serial3 = &uart4;
  29                 serial4 = &uart5;
  30                 spi0 = &ecspi1;
  31                 spi1 = &ecspi2;
  32                 spi2 = &ecspi3;
  33                 spi3 = &ecspi4;
  34                 usbphy0 = &usbphy1;
  35                 usbphy1 = &usbphy2;
  36         };
  37
  38         cpus {
  39                 #address-cells = <1>;
  40                 #size-cells = <0>;
  41
  42                 cpu@0 {
  43                         compatible = "arm,cortex-a9";
  44                         device_type = "cpu";
  45                         reg = <0x0>;
  46                         next-level-cache = <&L2>;
  47                         operating-points = <
  48                                 /* kHz    uV */
  49                                 996000  1275000
  50                                 792000  1175000
  51                                 396000  975000
  52                         >;
  53                         fsl,soc-operating-points = <
  54                                 /* ARM kHz      SOC-PU uV */
  55                                 996000          1225000
  56                                 792000          1175000
  57                                 396000          1175000
  58                         >;
  59                         clock-latency = <61036>; /* two CLK32 periods */
  60                         clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
  61                                         <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
  62                                         <&clks IMX6SL_CLK_PLL1_SYS>;
  63                         clock-names = "arm", "pll2_pfd2_396m", "step",
  64                                       "pll1_sw", "pll1_sys";
  65                         arm-supply = <&reg_arm>;
  66                         pu-supply = <&reg_pu>;
  67                         soc-supply = <&reg_soc>;
  68                 };
  69         };
  70
  71         intc: interrupt-controller@00a01000 {
  72                 compatible = "arm,cortex-a9-gic";
  73                 #interrupt-cells = <3>;
  74                 interrupt-controller;
  75                 reg = <0x00a01000 0x1000>,
  76                       <0x00a00100 0x100>;
  77                 interrupt-parent = <&intc>;
  78         };
  79
  80         clocks {
  81                 #address-cells = <1>;
  82                 #size-cells = <0>;
  83
  84                 ckil {
  85                         compatible = "fixed-clock";
  86                         #clock-cells = <0>;
  87                         clock-frequency = <32768>;
  88                 };
  89
  90                 osc {
  91                         compatible = "fixed-clock";
  92                         #clock-cells = <0>;
  93                         clock-frequency = <24000000>;
  94                 };
  95         };
  96
  97         soc {
  98                 #address-cells = <1>;
  99                 #size-cells = <1>;
 100                 compatible = "simple-bus";
 101                 interrupt-parent = <&gpc>;
 102                 ranges;
 103
 104                 ocram: sram@00900000 {
 105                         compatible = "mmio-sram";
 106                         reg = <0x00900000 0x20000>;
 107                         clocks = <&clks IMX6SL_CLK_OCRAM>;
 108                 };
 109
 110                 L2: l2-cache@00a02000 {
 111                         compatible = "arm,pl310-cache";
 112                         reg = <0x00a02000 0x1000>;
 113                         interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
 114                         cache-unified;
 115                         cache-level = <2>;
 116                         arm,tag-latency = <4 2 3>;
 117                         arm,data-latency = <4 2 3>;
 118                 };
 119
 120                 pmu {
 121                         compatible = "arm,cortex-a9-pmu";
 122                         interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
 123                 };
 124
 125                 aips1: aips-bus@02000000 {
 126                         compatible = "fsl,aips-bus", "simple-bus";
 127                         #address-cells = <1>;
 128                         #size-cells = <1>;
 129                         reg = <0x02000000 0x100000>;
 130                         ranges;
 131
 132                         spba: spba-bus@02000000 {
 133                                 compatible = "fsl,spba-bus", "simple-bus";
 134                                 #address-cells = <1>;
 135                                 #size-cells = <1>;
 136                                 reg = <0x02000000 0x40000>;
 137                                 ranges;
 138
 139                                 spdif: spdif@02004000 {
 140                                         compatible = "fsl,imx6sl-spdif",
 141                                                 "fsl,imx35-spdif";
 142                                         reg = <0x02004000 0x4000>;
 143                                         interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
 144                                         dmas = <&sdma 14 18 0>,
 145                                                 <&sdma 15 18 0>;
 146                                         dma-names = "rx", "tx";
 147                                         clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>,
 148                                                  <&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>,
 149                                                  <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_DUMMY>,
 150                                                  <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_DUMMY>,
 151                                                  <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_SPBA>;
 152                                         clock-names = "core", "rxtx0",
 153                                                 "rxtx1", "rxtx2",
 154                                                 "rxtx3", "rxtx4",
 155                                                 "rxtx5", "rxtx6",
 156                                                 "rxtx7", "spba";
 157                                         status = "disabled";
 158                                 };
 159
 160                                 ecspi1: ecspi@02008000 {
 161                                         #address-cells = <1>;
 162                                         #size-cells = <0>;
 163                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 164                                         reg = <0x02008000 0x4000>;
 165                                         interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 166                                         clocks = <&clks IMX6SL_CLK_ECSPI1>,
 167                                                  <&clks IMX6SL_CLK_ECSPI1>;
 168                                         clock-names = "ipg", "per";
 169                                         status = "disabled";
 170                                 };
 171
 172                                 ecspi2: ecspi@0200c000 {
 173                                         #address-cells = <1>;
 174                                         #size-cells = <0>;
 175                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 176                                         reg = <0x0200c000 0x4000>;
 177                                         interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
 178                                         clocks = <&clks IMX6SL_CLK_ECSPI2>,
 179                                                  <&clks IMX6SL_CLK_ECSPI2>;
 180                                         clock-names = "ipg", "per";
 181                                         status = "disabled";
 182                                 };
 183
 184                                 ecspi3: ecspi@02010000 {
 185                                         #address-cells = <1>;
 186                                         #size-cells = <0>;
 187                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 188                                         reg = <0x02010000 0x4000>;
 189                                         interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
 190                                         clocks = <&clks IMX6SL_CLK_ECSPI3>,
 191                                                  <&clks IMX6SL_CLK_ECSPI3>;
 192                                         clock-names = "ipg", "per";
 193                                         status = "disabled";
 194                                 };
 195
 196                                 ecspi4: ecspi@02014000 {
 197                                         #address-cells = <1>;
 198                                         #size-cells = <0>;
 199                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 200                                         reg = <0x02014000 0x4000>;
 201                                         interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
 202                                         clocks = <&clks IMX6SL_CLK_ECSPI4>,
 203                                                  <&clks IMX6SL_CLK_ECSPI4>;
 204                                         clock-names = "ipg", "per";
 205                                         status = "disabled";
 206                                 };
 207
 208                                 uart5: serial@02018000 {
 209                                         compatible = "fsl,imx6sl-uart",
 210                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 211                                         reg = <0x02018000 0x4000>;
 212                                         interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
 213                                         clocks = <&clks IMX6SL_CLK_UART>,
 214                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 215                                         clock-names = "ipg", "per";
 216                                         dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
 217                                         dma-names = "rx", "tx";
 218                                         status = "disabled";
 219                                 };
 220
 221                                 uart1: serial@02020000 {
 222                                         compatible = "fsl,imx6sl-uart",
 223                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 224                                         reg = <0x02020000 0x4000>;
 225                                         interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
 226                                         clocks = <&clks IMX6SL_CLK_UART>,
 227                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 228                                         clock-names = "ipg", "per";
 229                                         dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
 230                                         dma-names = "rx", "tx";
 231                                         status = "disabled";
 232                                 };
 233
 234                                 uart2: serial@02024000 {
 235                                         compatible = "fsl,imx6sl-uart",
 236                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 237                                         reg = <0x02024000 0x4000>;
 238                                         interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
 239                                         clocks = <&clks IMX6SL_CLK_UART>,
 240                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 241                                         clock-names = "ipg", "per";
 242                                         dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
 243                                         dma-names = "rx", "tx";
 244                                         status = "disabled";
 245                                 };
 246
 247                                 ssi1: ssi@02028000 {
 248                                         #sound-dai-cells = <0>;
 249                                         compatible = "fsl,imx6sl-ssi",
 250                                                         "fsl,imx51-ssi";
 251                                         reg = <0x02028000 0x4000>;
 252                                         interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
 253                                         clocks = <&clks IMX6SL_CLK_SSI1_IPG>,
 254                                                  <&clks IMX6SL_CLK_SSI1>;
 255                                         clock-names = "ipg", "baud";
 256                                         dmas = <&sdma 37 1 0>,
 257                                                <&sdma 38 1 0>;
 258                                         dma-names = "rx", "tx";
 259                                         fsl,fifo-depth = <15>;
 260                                         status = "disabled";
 261                                 };
 262
 263                                 ssi2: ssi@0202c000 {
 264                                         #sound-dai-cells = <0>;
 265                                         compatible = "fsl,imx6sl-ssi",
 266                                                         "fsl,imx51-ssi";
 267                                         reg = <0x0202c000 0x4000>;
 268                                         interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
 269                                         clocks = <&clks IMX6SL_CLK_SSI2_IPG>,
 270                                                  <&clks IMX6SL_CLK_SSI2>;
 271                                         clock-names = "ipg", "baud";
 272                                         dmas = <&sdma 41 1 0>,
 273                                                <&sdma 42 1 0>;
 274                                         dma-names = "rx", "tx";
 275                                         fsl,fifo-depth = <15>;
 276                                         status = "disabled";
 277                                 };
 278
 279                                 ssi3: ssi@02030000 {
 280                                         #sound-dai-cells = <0>;
 281                                         compatible = "fsl,imx6sl-ssi",
 282                                                         "fsl,imx51-ssi";
 283                                         reg = <0x02030000 0x4000>;
 284                                         interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
 285                                         clocks = <&clks IMX6SL_CLK_SSI3_IPG>,
 286                                                  <&clks IMX6SL_CLK_SSI3>;
 287                                         clock-names = "ipg", "baud";
 288                                         dmas = <&sdma 45 1 0>,
 289                                                <&sdma 46 1 0>;
 290                                         dma-names = "rx", "tx";
 291                                         fsl,fifo-depth = <15>;
 292                                         status = "disabled";
 293                                 };
 294
 295                                 uart3: serial@02034000 {
 296                                         compatible = "fsl,imx6sl-uart",
 297                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 298                                         reg = <0x02034000 0x4000>;
 299                                         interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
 300                                         clocks = <&clks IMX6SL_CLK_UART>,
 301                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 302                                         clock-names = "ipg", "per";
 303                                         dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
 304                                         dma-names = "rx", "tx";
 305                                         status = "disabled";
 306                                 };
 307
 308                                 uart4: serial@02038000 {
 309                                         compatible = "fsl,imx6sl-uart",
 310                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 311                                         reg = <0x02038000 0x4000>;
 312                                         interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
 313                                         clocks = <&clks IMX6SL_CLK_UART>,
 314                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 315                                         clock-names = "ipg", "per";
 316                                         dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
 317                                         dma-names = "rx", "tx";
 318                                         status = "disabled";
 319                                 };
 320                         };
 321
 322                         pwm1: pwm@02080000 {
 323                                 #pwm-cells = <2>;
 324                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 325                                 reg = <0x02080000 0x4000>;
 326                                 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
 327                                 clocks = <&clks IMX6SL_CLK_PWM1>,
 328                                          <&clks IMX6SL_CLK_PWM1>;
 329                                 clock-names = "ipg", "per";
 330                         };
 331
 332                         pwm2: pwm@02084000 {
 333                                 #pwm-cells = <2>;
 334                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 335                                 reg = <0x02084000 0x4000>;
 336                                 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
 337                                 clocks = <&clks IMX6SL_CLK_PWM2>,
 338                                          <&clks IMX6SL_CLK_PWM2>;
 339                                 clock-names = "ipg", "per";
 340                         };
 341
 342                         pwm3: pwm@02088000 {
 343                                 #pwm-cells = <2>;
 344                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 345                                 reg = <0x02088000 0x4000>;
 346                                 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
 347                                 clocks = <&clks IMX6SL_CLK_PWM3>,
 348                                          <&clks IMX6SL_CLK_PWM3>;
 349                                 clock-names = "ipg", "per";
 350                         };
 351
 352                         pwm4: pwm@0208c000 {
 353                                 #pwm-cells = <2>;
 354                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 355                                 reg = <0x0208c000 0x4000>;
 356                                 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
 357                                 clocks = <&clks IMX6SL_CLK_PWM4>,
 358                                          <&clks IMX6SL_CLK_PWM4>;
 359                                 clock-names = "ipg", "per";
 360                         };
 361
 362                         gpt: gpt@02098000 {
 363                                 compatible = "fsl,imx6sl-gpt";
 364                                 reg = <0x02098000 0x4000>;
 365                                 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
 366                                 clocks = <&clks IMX6SL_CLK_GPT>,
 367                                          <&clks IMX6SL_CLK_GPT_SERIAL>;
 368                                 clock-names = "ipg", "per";
 369                         };
 370
 371                         gpio1: gpio@0209c000 {
 372                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 373                                 reg = <0x0209c000 0x4000>;
 374                                 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
 375                                              <0 67 IRQ_TYPE_LEVEL_HIGH>;
 376                                 gpio-controller;
 377                                 #gpio-cells = <2>;
 378                                 interrupt-controller;
 379                                 #interrupt-cells = <2>;
 380                                 gpio-ranges = <&iomuxc  0 22 1>, <&iomuxc  1 20 2>,
 381                                               <&iomuxc  3 23 1>, <&iomuxc  4 25 1>,
 382                                               <&iomuxc  5 24 1>, <&iomuxc  6 19 1>,
 383                                               <&iomuxc  7 36 2>, <&iomuxc  9 44 8>,
 384                                               <&iomuxc 17 38 6>, <&iomuxc 23 68 4>,
 385                                               <&iomuxc 27 64 4>, <&iomuxc 31 52 1>;
 386                         };
 387
 388                         gpio2: gpio@020a0000 {
 389                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 390                                 reg = <0x020a0000 0x4000>;
 391                                 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
 392                                              <0 69 IRQ_TYPE_LEVEL_HIGH>;
 393                                 gpio-controller;
 394                                 #gpio-cells = <2>;
 395                                 interrupt-controller;
 396                                 #interrupt-cells = <2>;
 397                                 gpio-ranges = <&iomuxc  0  53 3>, <&iomuxc  3  72 2>,
 398                                               <&iomuxc  5  34 2>, <&iomuxc  7  57 4>,
 399                                               <&iomuxc 11  56 1>, <&iomuxc 12  61 3>,
 400                                               <&iomuxc 15 107 1>, <&iomuxc 16 132 2>,
 401                                               <&iomuxc 18 135 1>, <&iomuxc 19 134 1>,
 402                                               <&iomuxc 20 108 2>, <&iomuxc 22 120 1>,
 403                                               <&iomuxc 23 125 7>, <&iomuxc 30 110 2>;
 404                         };
 405
 406                         gpio3: gpio@020a4000 {
 407                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 408                                 reg = <0x020a4000 0x4000>;
 409                                 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
 410                                              <0 71 IRQ_TYPE_LEVEL_HIGH>;
 411                                 gpio-controller;
 412                                 #gpio-cells = <2>;
 413                                 interrupt-controller;
 414                                 #interrupt-cells = <2>;
 415                                 gpio-ranges = <&iomuxc  0 112 8>, <&iomuxc  8 121 4>,
 416                                               <&iomuxc 12  97 4>, <&iomuxc 16 166 3>,
 417                                               <&iomuxc 19  85 2>, <&iomuxc 21 137 2>,
 418                                               <&iomuxc 23 136 1>, <&iomuxc 24  91 1>,
 419                                               <&iomuxc 25  99 1>, <&iomuxc 26  92 1>,
 420                                               <&iomuxc 27 100 1>, <&iomuxc 28  93 1>,
 421                                               <&iomuxc 29 101 1>, <&iomuxc 30  94 1>,
 422                                               <&iomuxc 31 102 1>;
 423                         };
 424
 425                         gpio4: gpio@020a8000 {
 426                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 427                                 reg = <0x020a8000 0x4000>;
 428                                 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
 429                                              <0 73 IRQ_TYPE_LEVEL_HIGH>;
 430                                 gpio-controller;
 431                                 #gpio-cells = <2>;
 432                                 interrupt-controller;
 433                                 #interrupt-cells = <2>;
 434                                 gpio-ranges = <&iomuxc  0  95 1>, <&iomuxc  1 103 1>,
 435                                               <&iomuxc  2  96 1>, <&iomuxc  3 104 1>,
 436                                               <&iomuxc  4  97 1>, <&iomuxc  5 105 1>,
 437                                               <&iomuxc  6  98 1>, <&iomuxc  7 106 1>,
 438                                               <&iomuxc  8  28 1>, <&iomuxc  9  27 1>,
 439                                               <&iomuxc 10  26 1>, <&iomuxc 11  29 1>,
 440                                               <&iomuxc 12  32 1>, <&iomuxc 13  31 1>,
 441                                               <&iomuxc 14  30 1>, <&iomuxc 15  33 1>,
 442                                               <&iomuxc 16  84 1>, <&iomuxc 17  79 2>,
 443                                               <&iomuxc 19  78 1>, <&iomuxc 20  76 1>,
 444                                               <&iomuxc 21  81 2>, <&iomuxc 23  75 1>,
 445                                               <&iomuxc 24  83 1>, <&iomuxc 25  74 1>,
 446                                               <&iomuxc 26  77 1>, <&iomuxc 27 159 1>,
 447                                               <&iomuxc 28 154 1>, <&iomuxc 29 157 1>,
 448                                               <&iomuxc 30 152 1>, <&iomuxc 31 156 1>;
 449                         };
 450
 451                         gpio5: gpio@020ac000 {
 452                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 453                                 reg = <0x020ac000 0x4000>;
 454                                 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
 455                                              <0 75 IRQ_TYPE_LEVEL_HIGH>;
 456                                 gpio-controller;
 457                                 #gpio-cells = <2>;
 458                                 interrupt-controller;
 459                                 #interrupt-cells = <2>;
 460                                 gpio-ranges = <&iomuxc  0 158 1>, <&iomuxc  1 151 1>,
 461                                               <&iomuxc  2 155 1>, <&iomuxc  3 153 1>,
 462                                               <&iomuxc  4 150 1>, <&iomuxc  5 149 1>,
 463                                               <&iomuxc  6 144 1>, <&iomuxc  7 147 1>,
 464                                               <&iomuxc  8 142 1>, <&iomuxc  9 146 1>,
 465                                               <&iomuxc 10 148 1>, <&iomuxc 11 141 1>,
 466                                               <&iomuxc 12 145 1>, <&iomuxc 13 143 1>,
 467                                               <&iomuxc 14 140 1>, <&iomuxc 15 139 1>,
 468                                               <&iomuxc 16 164 2>, <&iomuxc 18 160 1>,
 469                                               <&iomuxc 19 162 1>, <&iomuxc 20 163 1>,
 470                                               <&iomuxc 21 161 1>;
 471                         };
 472
 473                         kpp: kpp@020b8000 {
 474                                 compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp";
 475                                 reg = <0x020b8000 0x4000>;
 476                                 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
 477                                 clocks = <&clks IMX6SL_CLK_DUMMY>;
 478                                 status = "disabled";
 479                         };
 480
 481                         wdog1: wdog@020bc000 {
 482                                 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
 483                                 reg = <0x020bc000 0x4000>;
 484                                 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
 485                                 clocks = <&clks IMX6SL_CLK_DUMMY>;
 486                         };
 487
 488                         wdog2: wdog@020c0000 {
 489                                 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
 490                                 reg = <0x020c0000 0x4000>;
 491                                 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
 492                                 clocks = <&clks IMX6SL_CLK_DUMMY>;
 493                                 status = "disabled";
 494                         };
 495
 496                         clks: ccm@020c4000 {
 497                                 compatible = "fsl,imx6sl-ccm";
 498                                 reg = <0x020c4000 0x4000>;
 499                                 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
 500                                              <0 88 IRQ_TYPE_LEVEL_HIGH>;
 501                                 #clock-cells = <1>;
 502                         };
 503
 504                         anatop: anatop@020c8000 {
 505                                 compatible = "fsl,imx6sl-anatop",
 506                                              "fsl,imx6q-anatop",
 507                                              "syscon", "simple-bus";
 508                                 reg = <0x020c8000 0x1000>;
 509                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
 510                                              <0 54 IRQ_TYPE_LEVEL_HIGH>,
 511                                              <0 127 IRQ_TYPE_LEVEL_HIGH>;
 512
 513                                 regulator-1p1 {
 514                                         compatible = "fsl,anatop-regulator";
 515                                         regulator-name = "vdd1p1";
 516                                         regulator-min-microvolt = <800000>;
 517                                         regulator-max-microvolt = <1375000>;
 518                                         regulator-always-on;
 519                                         anatop-reg-offset = <0x110>;
 520                                         anatop-vol-bit-shift = <8>;
 521                                         anatop-vol-bit-width = <5>;
 522                                         anatop-min-bit-val = <4>;
 523                                         anatop-min-voltage = <800000>;
 524                                         anatop-max-voltage = <1375000>;
 525                                 };
 526
 527                                 regulator-3p0 {
 528                                         compatible = "fsl,anatop-regulator";
 529                                         regulator-name = "vdd3p0";
 530                                         regulator-min-microvolt = <2800000>;
 531                                         regulator-max-microvolt = <3150000>;
 532                                         regulator-always-on;
 533                                         anatop-reg-offset = <0x120>;
 534                                         anatop-vol-bit-shift = <8>;
 535                                         anatop-vol-bit-width = <5>;
 536                                         anatop-min-bit-val = <0>;
 537                                         anatop-min-voltage = <2625000>;
 538                                         anatop-max-voltage = <3400000>;
 539                                 };
 540
 541                                 regulator-2p5 {
 542                                         compatible = "fsl,anatop-regulator";
 543                                         regulator-name = "vdd2p5";
 544                                         regulator-min-microvolt = <2100000>;
 545                                         regulator-max-microvolt = <2850000>;
 546                                         regulator-always-on;
 547                                         anatop-reg-offset = <0x130>;
 548                                         anatop-vol-bit-shift = <8>;
 549                                         anatop-vol-bit-width = <5>;
 550                                         anatop-min-bit-val = <0>;
 551                                         anatop-min-voltage = <2100000>;
 552                                         anatop-max-voltage = <2850000>;
 553                                 };
 554
 555                                 reg_arm: regulator-vddcore {
 556                                         compatible = "fsl,anatop-regulator";
 557                                         regulator-name = "vddarm";
 558                                         regulator-min-microvolt = <725000>;
 559                                         regulator-max-microvolt = <1450000>;
 560                                         regulator-always-on;
 561                                         anatop-reg-offset = <0x140>;
 562                                         anatop-vol-bit-shift = <0>;
 563                                         anatop-vol-bit-width = <5>;
 564                                         anatop-delay-reg-offset = <0x170>;
 565                                         anatop-delay-bit-shift = <24>;
 566                                         anatop-delay-bit-width = <2>;
 567                                         anatop-min-bit-val = <1>;
 568                                         anatop-min-voltage = <725000>;
 569                                         anatop-max-voltage = <1450000>;
 570                                 };
 571
 572                                 reg_pu: regulator-vddpu {
 573                                         compatible = "fsl,anatop-regulator";
 574                                         regulator-name = "vddpu";
 575                                         regulator-min-microvolt = <725000>;
 576                                         regulator-max-microvolt = <1450000>;
 577                                         regulator-always-on;
 578                                         anatop-reg-offset = <0x140>;
 579                                         anatop-vol-bit-shift = <9>;
 580                                         anatop-vol-bit-width = <5>;
 581                                         anatop-delay-reg-offset = <0x170>;
 582                                         anatop-delay-bit-shift = <26>;
 583                                         anatop-delay-bit-width = <2>;
 584                                         anatop-min-bit-val = <1>;
 585                                         anatop-min-voltage = <725000>;
 586                                         anatop-max-voltage = <1450000>;
 587                                 };
 588
 589                                 reg_soc: regulator-vddsoc {
 590                                         compatible = "fsl,anatop-regulator";
 591                                         regulator-name = "vddsoc";
 592                                         regulator-min-microvolt = <725000>;
 593                                         regulator-max-microvolt = <1450000>;
 594                                         regulator-always-on;
 595                                         anatop-reg-offset = <0x140>;
 596                                         anatop-vol-bit-shift = <18>;
 597                                         anatop-vol-bit-width = <5>;
 598                                         anatop-delay-reg-offset = <0x170>;
 599                                         anatop-delay-bit-shift = <28>;
 600                                         anatop-delay-bit-width = <2>;
 601                                         anatop-min-bit-val = <1>;
 602                                         anatop-min-voltage = <725000>;
 603                                         anatop-max-voltage = <1450000>;
 604                                 };
 605                         };
 606
 607                         tempmon: tempmon {
 608                                 compatible = "fsl,imx6q-tempmon";
 609                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
 610                                 fsl,tempmon = <&anatop>;
 611                                 fsl,tempmon-data = <&ocotp>;
 612                                 clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>;
 613                         };
 614
 615                         usbphy1: usbphy@020c9000 {
 616                                 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
 617                                 reg = <0x020c9000 0x1000>;
 618                                 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
 619                                 clocks = <&clks IMX6SL_CLK_USBPHY1>;
 620                                 fsl,anatop = <&anatop>;
 621                         };
 622
 623                         usbphy2: usbphy@020ca000 {
 624                                 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
 625                                 reg = <0x020ca000 0x1000>;
 626                                 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
 627                                 clocks = <&clks IMX6SL_CLK_USBPHY2>;
 628                                 fsl,anatop = <&anatop>;
 629                         };
 630
 631                         snvs: snvs@020cc000 {
 632                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 633                                 reg = <0x020cc000 0x4000>;
 634
 635                                 snvs_rtc: snvs-rtc-lp {
 636                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 637                                         regmap = <&snvs>;
 638                                         offset = <0x34>;
 639                                         interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
 640                                                      <0 20 IRQ_TYPE_LEVEL_HIGH>;
 641                                 };
 642
 643                                 snvs_poweroff: snvs-poweroff {
 644                                         compatible = "syscon-poweroff";
 645                                         regmap = <&snvs>;
 646                                         offset = <0x38>;
 647                                         mask = <0x60>;
 648                                         status = "disabled";
 649                                 };
 650                         };
 651
 652                         epit1: epit@020d0000 {
 653                                 reg = <0x020d0000 0x4000>;
 654                                 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
 655                         };
 656
 657                         epit2: epit@020d4000 {
 658                                 reg = <0x020d4000 0x4000>;
 659                                 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
 660                         };
 661
 662                         src: src@020d8000 {
 663                                 compatible = "fsl,imx6sl-src", "fsl,imx51-src";
 664                                 reg = <0x020d8000 0x4000>;
 665                                 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
 666                                              <0 96 IRQ_TYPE_LEVEL_HIGH>;
 667                                 #reset-cells = <1>;
 668                         };
 669
 670                         gpc: gpc@020dc000 {
 671                                 compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
 672                                 reg = <0x020dc000 0x4000>;
 673                                 interrupt-controller;
 674                                 #interrupt-cells = <3>;
 675                                 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
 676                                 interrupt-parent = <&intc>;
 677                                 pu-supply = <&reg_pu>;
 678                                 clocks = <&clks IMX6SL_CLK_GPU2D_OVG>,
 679                                          <&clks IMX6SL_CLK_GPU2D_PODF>;
 680                                 #power-domain-cells = <1>;
 681                         };
 682
 683                         gpr: iomuxc-gpr@020e0000 {
 684                                 compatible = "fsl,imx6sl-iomuxc-gpr",
 685                                              "fsl,imx6q-iomuxc-gpr", "syscon";
 686                                 reg = <0x020e0000 0x38>;
 687                         };
 688
 689                         iomuxc: iomuxc@020e0000 {
 690                                 compatible = "fsl,imx6sl-iomuxc";
 691                                 reg = <0x020e0000 0x4000>;
 692                         };
 693
 694                         csi: csi@020e4000 {
 695                                 reg = <0x020e4000 0x4000>;
 696                                 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
 697                         };
 698
 699                         spdc: spdc@020e8000 {
 700                                 reg = <0x020e8000 0x4000>;
 701                                 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
 702                         };
 703
 704                         sdma: sdma@020ec000 {
 705                                 compatible = "fsl,imx6sl-sdma", "fsl,imx6q-sdma";
 706                                 reg = <0x020ec000 0x4000>;
 707                                 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
 708                                 clocks = <&clks IMX6SL_CLK_SDMA>,
 709                                          <&clks IMX6SL_CLK_SDMA>;
 710                                 clock-names = "ipg", "ahb";
 711                                 #dma-cells = <3>;
 712                                 /* imx6sl reuses imx6q sdma firmware */
 713                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 714                         };
 715
 716                         pxp: pxp@020f0000 {
 717                                 reg = <0x020f0000 0x4000>;
 718                                 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
 719                         };
 720
 721                         epdc: epdc@020f4000 {
 722                                 reg = <0x020f4000 0x4000>;
 723                                 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
 724                         };
 725
 726                         lcdif: lcdif@020f8000 {
 727                                 compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif";
 728                                 reg = <0x020f8000 0x4000>;
 729                                 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
 730                                 clocks = <&clks IMX6SL_CLK_LCDIF_PIX>,
 731                                          <&clks IMX6SL_CLK_LCDIF_AXI>,
 732                                          <&clks IMX6SL_CLK_DUMMY>;
 733                                 clock-names = "pix", "axi", "disp_axi";
 734                                 status = "disabled";
 735                         };
 736
 737                         dcp: dcp@020fc000 {
 738                                 compatible = "fsl,imx6sl-dcp", "fsl,imx28-dcp";
 739                                 reg = <0x020fc000 0x4000>;
 740                                 interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>,
 741                                              <0 100 IRQ_TYPE_LEVEL_HIGH>,
 742                                              <0 101 IRQ_TYPE_LEVEL_HIGH>;
 743                         };
 744                 };
 745
 746                 aips2: aips-bus@02100000 {
 747                         compatible = "fsl,aips-bus", "simple-bus";
 748                         #address-cells = <1>;
 749                         #size-cells = <1>;
 750                         reg = <0x02100000 0x100000>;
 751                         ranges;
 752
 753                         usbotg1: usb@02184000 {
 754                                 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
 755                                 reg = <0x02184000 0x200>;
 756                                 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
 757                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 758                                 fsl,usbphy = <&usbphy1>;
 759                                 fsl,usbmisc = <&usbmisc 0>;
 760                                 ahb-burst-config = <0x0>;
 761                                 tx-burst-size-dword = <0x10>;
 762                                 rx-burst-size-dword = <0x10>;
 763                                 status = "disabled";
 764                         };
 765
 766                         usbotg2: usb@02184200 {
 767                                 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
 768                                 reg = <0x02184200 0x200>;
 769                                 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
 770                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 771                                 fsl,usbphy = <&usbphy2>;
 772                                 fsl,usbmisc = <&usbmisc 1>;
 773                                 ahb-burst-config = <0x0>;
 774                                 tx-burst-size-dword = <0x10>;
 775                                 rx-burst-size-dword = <0x10>;
 776                                 status = "disabled";
 777                         };
 778
 779                         usbh: usb@02184400 {
 780                                 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
 781                                 reg = <0x02184400 0x200>;
 782                                 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
 783                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 784                                 fsl,usbmisc = <&usbmisc 2>;
 785                                 dr_mode = "host";
 786                                 ahb-burst-config = <0x0>;
 787                                 tx-burst-size-dword = <0x10>;
 788                                 rx-burst-size-dword = <0x10>;
 789                                 status = "disabled";
 790                         };
 791
 792                         usbmisc: usbmisc@02184800 {
 793                                 #index-cells = <1>;
 794                                 compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
 795                                 reg = <0x02184800 0x200>;
 796                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 797                         };
 798
 799                         fec: ethernet@02188000 {
 800                                 compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
 801                                 reg = <0x02188000 0x4000>;
 802                                 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
 803                                 clocks = <&clks IMX6SL_CLK_ENET>,
 804                                          <&clks IMX6SL_CLK_ENET_REF>;
 805                                 clock-names = "ipg", "ahb";
 806                                 status = "disabled";
 807                         };
 808
 809                         usdhc1: usdhc@02190000 {
 810                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 811                                 reg = <0x02190000 0x4000>;
 812                                 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 813                                 clocks = <&clks IMX6SL_CLK_USDHC1>,
 814                                          <&clks IMX6SL_CLK_USDHC1>,
 815                                          <&clks IMX6SL_CLK_USDHC1>;
 816                                 clock-names = "ipg", "ahb", "per";
 817                                 bus-width = <4>;
 818                                 status = "disabled";
 819                         };
 820
 821                         usdhc2: usdhc@02194000 {
 822                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 823                                 reg = <0x02194000 0x4000>;
 824                                 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 825                                 clocks = <&clks IMX6SL_CLK_USDHC2>,
 826                                          <&clks IMX6SL_CLK_USDHC2>,
 827                                          <&clks IMX6SL_CLK_USDHC2>;
 828                                 clock-names = "ipg", "ahb", "per";
 829                                 bus-width = <4>;
 830                                 status = "disabled";
 831                         };
 832
 833                         usdhc3: usdhc@02198000 {
 834                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 835                                 reg = <0x02198000 0x4000>;
 836                                 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
 837                                 clocks = <&clks IMX6SL_CLK_USDHC3>,
 838                                          <&clks IMX6SL_CLK_USDHC3>,
 839                                          <&clks IMX6SL_CLK_USDHC3>;
 840                                 clock-names = "ipg", "ahb", "per";
 841                                 bus-width = <4>;
 842                                 status = "disabled";
 843                         };
 844
 845                         usdhc4: usdhc@0219c000 {
 846                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 847                                 reg = <0x0219c000 0x4000>;
 848                                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 849                                 clocks = <&clks IMX6SL_CLK_USDHC4>,
 850                                          <&clks IMX6SL_CLK_USDHC4>,
 851                                          <&clks IMX6SL_CLK_USDHC4>;
 852                                 clock-names = "ipg", "ahb", "per";
 853                                 bus-width = <4>;
 854                                 status = "disabled";
 855                         };
 856
 857                         i2c1: i2c@021a0000 {
 858                                 #address-cells = <1>;
 859                                 #size-cells = <0>;
 860                                 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
 861                                 reg = <0x021a0000 0x4000>;
 862                                 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
 863                                 clocks = <&clks IMX6SL_CLK_I2C1>;
 864                                 status = "disabled";
 865                         };
 866
 867                         i2c2: i2c@021a4000 {
 868                                 #address-cells = <1>;
 869                                 #size-cells = <0>;
 870                                 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
 871                                 reg = <0x021a4000 0x4000>;
 872                                 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
 873                                 clocks = <&clks IMX6SL_CLK_I2C2>;
 874                                 status = "disabled";
 875                         };
 876
 877                         i2c3: i2c@021a8000 {
 878                                 #address-cells = <1>;
 879                                 #size-cells = <0>;
 880                                 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
 881                                 reg = <0x021a8000 0x4000>;
 882                                 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
 883                                 clocks = <&clks IMX6SL_CLK_I2C3>;
 884                                 status = "disabled";
 885                         };
 886
 887                         mmdc: mmdc@021b0000 {
 888                                 compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
 889                                 reg = <0x021b0000 0x4000>;
 890                         };
 891
 892                         rngb: rngb@021b4000 {
 893                                 reg = <0x021b4000 0x4000>;
 894                                 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
 895                         };
 896
 897                         weim: weim@021b8000 {
 898                                 #address-cells = <2>;
 899                                 #size-cells = <1>;
 900                                 reg = <0x021b8000 0x4000>;
 901                                 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
 902                                 fsl,weim-cs-gpr = <&gpr>;
 903                         };
 904
 905                         ocotp: ocotp@021bc000 {
 906                                 compatible = "fsl,imx6sl-ocotp", "syscon";
 907                                 reg = <0x021bc000 0x4000>;
 908                                 clocks = <&clks IMX6SL_CLK_OCOTP>;
 909                         };
 910
 911                         audmux: audmux@021d8000 {
 912                                 compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
 913                                 reg = <0x021d8000 0x4000>;
 914                                 status = "disabled";
 915                         };
 916                 };
 917         };
 918 };