arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi

   1 /*
   2  * Copyright (C) 2016-2017 Zodiac Inflight Innovations
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License
  11  *     version 2 as published by the Free Software Foundation.
  12  *
  13  *     This file is distributed in the hope that it will be useful,
  14  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *     GNU General Public License for more details.
  17  *
  18  * Or, alternatively,
  19  *
  20  *  b) Permission is hereby granted, free of charge, to any person
  21  *     obtaining a copy of this software and associated documentation
  22  *     files (the "Software"), to deal in the Software without
  23  *     restriction, including without limitation the rights to use,
  24  *     copy, modify, merge, publish, distribute, sublicense, and/or
  25  *     sell copies of the Software, and to permit persons to whom the
  26  *     Software is furnished to do so, subject to the following
  27  *     conditions:
  28  *
  29  *     The above copyright notice and this permission notice shall be
  30  *     included in all copies or substantial portions of the Software.
  31  *
  32  *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND,
  33  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  34  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  35  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  36  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  37  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  38  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  39  *     OTHER DEALINGS IN THE SOFTWARE.
  40  */
  41
  42 #include <dt-bindings/gpio/gpio.h>
  43 #include <dt-bindings/sound/fsl-imx-audmux.h>
  44
  45 / {
  46         chosen {
  47                 stdout-path = &uart1;
  48         };
  49
  50         aliases {
  51                 mdio-gpio0 = &mdio1;
  52                 rtc0 = &ds1341;
  53         };
  54
  55         mdio1: mdio {
  56                 compatible = "virtual,mdio-gpio";
  57                 #address-cells = <1>;
  58                 #size-cells = <0>;
  59                 pinctrl-names = "default";
  60                 pinctrl-0 = <&pinctrl_mdio1>;
  61                 gpios = <&gpio6 5 GPIO_ACTIVE_HIGH
  62                          &gpio6 4 GPIO_ACTIVE_HIGH>;
  63
  64                 phy: ethernet-phy@0 {
  65                         pinctrl-0 = <&pinctrl_rmii_phy_irq>;
  66                         pinctrl-names = "default";
  67                         reg = <0>;
  68                         interrupt-parent = <&gpio3>;
  69                         interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
  70                 };
  71         };
  72
  73         reg_28p0v: regulator-28p0v {
  74                 compatible = "regulator-fixed";
  75                 regulator-name = "28V_IN";
  76                 regulator-min-microvolt = <28000000>;
  77                 regulator-max-microvolt = <28000000>;
  78                 regulator-always-on;
  79         };
  80
  81         reg_12p0v: regulator-12p0v {
  82                 compatible = "regulator-fixed";
  83                 vin-supply = <&reg_28p0v>;
  84                 regulator-name = "12V_MAIN";
  85                 regulator-min-microvolt = <12000000>;
  86                 regulator-max-microvolt = <12000000>;
  87                 regulator-always-on;
  88         };
  89
  90         reg_5p0v_main: regulator-5p0v-main {
  91                 compatible = "regulator-fixed";
  92                 vin-supply = <&reg_12p0v>;
  93                 regulator-name = "5V_MAIN";
  94                 regulator-min-microvolt = <5000000>;
  95                 regulator-max-microvolt = <5000000>;
  96                 regulator-always-on;
  97         };
  98
  99         reg_5p0v_user_usb: regulator-5p0v-user-usb {
 100                 compatible = "regulator-fixed";
 101                 pinctrl-names = "default";
 102                 pinctrl-0 = <&pinctrl_reg_user_usb>;
 103                 vin-supply = <&reg_5p0v_main>;
 104                 regulator-name = "5V_USER_USB";
 105                 regulator-min-microvolt = <5000000>;
 106                 regulator-max-microvolt = <5000000>;
 107                 gpio = <&gpio3 22 GPIO_ACTIVE_LOW>;
 108                 startup-delay-us = <1000>;
 109         };
 110
 111         reg_3p3v_pmic: regulator-3p3v-pmic {
 112                 compatible = "regulator-fixed";
 113                 vin-supply = <&reg_12p0v>;
 114                 regulator-name = "PMIC_3V3";
 115                 regulator-min-microvolt = <3300000>;
 116                 regulator-max-microvolt = <3300000>;
 117                 regulator-always-on;
 118         };
 119
 120         reg_3p3v: regulator-3p3v {
 121                 compatible = "regulator-fixed";
 122                 vin-supply = <&reg_3p3v_pmic>;
 123                 regulator-name = "GEN_3V3";
 124                 regulator-min-microvolt = <3300000>;
 125                 regulator-max-microvolt = <3300000>;
 126                 regulator-always-on;
 127         };
 128
 129         reg_3p3v_sd: regulator-3p3v-sd {
 130                 compatible = "regulator-fixed";
 131                 pinctrl-names = "default";
 132                 pinctrl-0 = <&pinctrl_reg_3p3v_sd>;
 133                 vin-supply = <&reg_3p3v>;
 134                 regulator-name = "3V3_SD";
 135                 regulator-min-microvolt = <3300000>;
 136                 regulator-max-microvolt = <3300000>;
 137                 gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>;
 138                 startup-delay-us = <1000>;
 139                 enable-active-high;
 140                 regulator-always-on;
 141         };
 142
 143         reg_3p3v_display: regulator-3p3v-display {
 144                 compatible = "regulator-fixed";
 145                 vin-supply = <&reg_12p0v>;
 146                 regulator-name = "3V3_DISPLAY";
 147                 regulator-min-microvolt = <3300000>;
 148                 regulator-max-microvolt = <3300000>;
 149                 regulator-always-on;
 150         };
 151
 152         reg_3p3v_ssd: regulator-3p3v-ssd {
 153                 compatible = "regulator-fixed";
 154                 vin-supply = <&reg_12p0v>;
 155                 regulator-name = "3V3_SSD";
 156                 regulator-min-microvolt = <3300000>;
 157                 regulator-max-microvolt = <3300000>;
 158                 regulator-always-on;
 159         };
 160
 161         sound1 {
 162                 compatible = "simple-audio-card";
 163                 simple-audio-card,name = "Front";
 164                 simple-audio-card,format = "i2s";
 165                 simple-audio-card,bitclock-master = <&sound1_codec>;
 166                 simple-audio-card,frame-master = <&sound1_codec>;
 167                 simple-audio-card,widgets =
 168                         "Headphone", "Headphone Jack";
 169                 simple-audio-card,routing =
 170                         "Headphone Jack", "HPLEFT",
 171                         "Headphone Jack", "HPRIGHT",
 172                         "LEFTIN", "HPL",
 173                         "RIGHTIN", "HPR";
 174                 simple-audio-card,aux-devs = <&hpa1>;
 175
 176                 sound1_cpu: simple-audio-card,cpu {
 177                         sound-dai = <&ssi2>;
 178                 };
 179
 180                 sound1_codec: simple-audio-card,codec {
 181                         sound-dai = <&codec1>;
 182                         clocks = <&cs2000>;
 183                 };
 184         };
 185
 186         sound2 {
 187                 compatible = "simple-audio-card";
 188                 simple-audio-card,name = "Back";
 189                 simple-audio-card,format = "i2s";
 190                 simple-audio-card,bitclock-master = <&sound2_codec>;
 191                 simple-audio-card,frame-master = <&sound2_codec>;
 192                 simple-audio-card,widgets =
 193                         "Headphone", "Headphone Jack";
 194                 simple-audio-card,routing =
 195                         "Headphone Jack", "HPLEFT",
 196                         "Headphone Jack", "HPRIGHT",
 197                         "LEFTIN", "HPL",
 198                         "RIGHTIN", "HPR";
 199                 simple-audio-card,aux-devs = <&hpa2>;
 200
 201                 sound2_cpu: simple-audio-card,cpu {
 202                         sound-dai = <&ssi1>;
 203                 };
 204
 205                 sound2_codec: simple-audio-card,codec {
 206                         sound-dai = <&codec2>;
 207                         clocks = <&cs2000>;
 208                 };
 209         };
 210
 211         panel {
 212                 power-supply = <&reg_3p3v_display>;
 213                 status = "disabled";
 214
 215                 port {
 216                         panel_in: endpoint {
 217                                 remote-endpoint = <&lvds0_out>;
 218                         };
 219                 };
 220         };
 221
 222         disp0: disp0 {
 223                 #address-cells = <1>;
 224                 #size-cells = <0>;
 225                 compatible = "fsl,imx-parallel-display";
 226                 pinctrl-names = "default";
 227                 pinctrl-0 = <&pinctrl_disp0>;
 228                 status = "disabled";
 229
 230                 port@0 {
 231                         reg = <0>;
 232
 233                         disp0_in_0: endpoint {
 234                                 remote-endpoint = <&ipu1_di0_disp0>;
 235                         };
 236                 };
 237
 238                 port@1 {
 239                         reg = <1>;
 240
 241                         disp0_out: endpoint {
 242                                 remote-endpoint = <&tc358767_in>;
 243                         };
 244                 };
 245         };
 246
 247         cs2000_ref: cs2000-ref {
 248                 compatible = "fixed-clock";
 249                 #clock-cells = <0>;
 250                 clock-frequency = <24576000>;
 251         };
 252
 253         cs2000_in_dummy: cs2000-in-dummy {
 254                 compatible = "fixed-clock";
 255                 #clock-cells = <0>;
 256                 clock-frequency = <0>;
 257         };
 258
 259         edp_refclk: edp-refclk {
 260                 compatible = "fixed-clock";
 261                 #clock-cells = <0>;
 262                 clock-frequency = <19200000>;
 263         };
 264 };
 265
 266 &reg_arm {
 267         vin-supply = <&sw1a_reg>;
 268 };
 269
 270 &reg_pu {
 271         vin-supply = <&sw1c_reg>;
 272 };
 273
 274 &reg_soc {
 275         vin-supply = <&sw1c_reg>;
 276 };
 277
 278 &ldb {
 279         lvds-channel@0 {
 280                 port@4 {
 281                         reg = <4>;
 282
 283                         lvds0_out: endpoint {
 284                                 remote-endpoint = <&panel_in>;
 285                         };
 286                 };
 287         };
 288 };
 289
 290 &uart1 {
 291         pinctrl-names = "default";
 292         pinctrl-0 = <&pinctrl_uart1>;
 293         status = "okay";
 294 };
 295
 296 &uart3 {
 297         pinctrl-names = "default";
 298         pinctrl-0 = <&pinctrl_uart3>;
 299         uart-has-rtscts;
 300         linux,rs485-enabled-at-boot-time;
 301         status = "okay";
 302 };
 303
 304 &uart4 {
 305         pinctrl-names = "default";
 306         pinctrl-0 = <&pinctrl_uart4>;
 307         status = "okay";
 308 };
 309
 310 &ecspi1 {
 311         pinctrl-names = "default";
 312         pinctrl-0 = <&pinctrl_ecspi1>;
 313         cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>;
 314         status = "okay";
 315
 316         flash@0 {
 317                 compatible = "st,m25p128", "jedec,spi-nor";
 318                 spi-max-frequency = <20000000>;
 319                 reg = <0>;
 320         };
 321 };
 322
 323 &i2c1 {
 324         pinctrl-names = "default";
 325         pinctrl-0 = <&pinctrl_i2c1>;
 326         clock-frequency = <100000>;
 327         status = "okay";
 328
 329         codec2: codec@18 {
 330                 compatible = "ti,tlv320dac3100";
 331                 pinctrl-names = "default";
 332                 pinctrl-0 = <&pinctrl_codec2>;
 333                 reg = <0x18>;
 334                 #sound-dai-cells = <0>;
 335                 HPVDD-supply = <&reg_3p3v>;
 336                 SPRVDD-supply = <&reg_3p3v>;
 337                 SPLVDD-supply = <&reg_3p3v>;
 338                 AVDD-supply = <&reg_3p3v>;
 339                 IOVDD-supply = <&reg_3p3v>;
 340                 DVDD-supply = <&vgen4_reg>;
 341                 gpio-reset = <&gpio1 2 GPIO_ACTIVE_HIGH>;
 342         };
 343
 344         accel@1c {
 345                 pinctrl-names = "default";
 346                 pinctrl-0 = <&pinctrl_accel>;
 347                 compatible = "fsl,mma8451";
 348                 reg = <0x1c>;
 349                 interrupt-parent = <&gpio1>;
 350                 interrupt-names = "int1", "int2";
 351                 interrupts = <18 IRQ_TYPE_LEVEL_LOW>, <20 IRQ_TYPE_LEVEL_LOW>;
 352         };
 353
 354         hpa2: amp@60 {
 355                 compatible = "ti,tpa6130a2";
 356                 pinctrl-names = "default";
 357                 pinctrl-0 = <&pinctrl_tpa2>;
 358                 reg = <0x60>;
 359                 power-gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
 360                 Vdd-supply = <&reg_5p0v_main>;
 361         };
 362
 363         edp-bridge@68 {
 364                 compatible = "toshiba,tc358767";
 365                 pinctrl-names = "default";
 366                 pinctrl-0 = <&pinctrl_tc358767>;
 367                 reg = <0x68>;
 368                 shutdown-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
 369                 clock-names = "ref";
 370                 clocks = <&edp_refclk>;
 371                 status = "disabled";
 372
 373                 ports {
 374                         #address-cells = <1>;
 375                         #size-cells = <0>;
 376
 377                         port@1 {
 378                                 reg = <1>;
 379
 380                                 tc358767_in: endpoint {
 381                                         remote-endpoint = <&disp0_out>;
 382                                 };
 383                         };
 384                 };
 385         };
 386 };
 387
 388 &i2c2 {
 389         pinctrl-names = "default";
 390         pinctrl-0 = <&pinctrl_i2c2>;
 391         clock-frequency = <100000>;
 392         status = "okay";
 393
 394         pmic@8 {
 395                 compatible = "fsl,pfuze100";
 396                 pinctrl-names = "default";
 397                 pinctrl-0 = <&pinctrl_pfuze100_irq>;
 398                 reg = <0x08>;
 399                 interrupt-parent = <&gpio7>;
 400                 interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
 401
 402                 regulators {
 403                         sw1a_reg: sw1ab {
 404                                 regulator-min-microvolt = <300000>;
 405                                 regulator-max-microvolt = <1875000>;
 406                                 regulator-boot-on;
 407                                 regulator-always-on;
 408                                 regulator-ramp-delay = <6250>;
 409                         };
 410
 411                         sw1c_reg: sw1c {
 412                                 regulator-min-microvolt = <300000>;
 413                                 regulator-max-microvolt = <1875000>;
 414                                 regulator-boot-on;
 415                                 regulator-always-on;
 416                                 regulator-ramp-delay = <6250>;
 417                         };
 418
 419                         sw2_reg: sw2 {
 420                                 regulator-min-microvolt = <800000>;
 421                                 regulator-max-microvolt = <3000000>;
 422                                 regulator-boot-on;
 423                                 regulator-always-on;
 424                         };
 425
 426                         sw3a_reg: sw3a {
 427                                 regulator-min-microvolt = <400000>;
 428                                 regulator-max-microvolt = <1500000>;
 429                                 regulator-boot-on;
 430                                 regulator-always-on;
 431                         };
 432
 433                         sw3b_reg: sw3b {
 434                                 regulator-min-microvolt = <400000>;
 435                                 regulator-max-microvolt = <1500000>;
 436                                 regulator-boot-on;
 437                                 regulator-always-on;
 438                         };
 439
 440                         sw4_reg: sw4 {
 441                                 regulator-min-microvolt = <800000>;
 442                                 regulator-max-microvolt = <1800000>;
 443                                 regulator-boot-on;
 444                                 regulator-always-on;
 445                         };
 446
 447                         snvs_reg: vsnvs {
 448                                 regulator-min-microvolt = <1000000>;
 449                                 regulator-max-microvolt = <3000000>;
 450                                 regulator-boot-on;
 451                                 regulator-always-on;
 452                         };
 453
 454                         vref_reg: vrefddr {
 455                                 regulator-boot-on;
 456                                 regulator-always-on;
 457                         };
 458
 459                         vgen2_reg: vgen2 {
 460                                 regulator-min-microvolt = <1000000>;
 461                                 regulator-max-microvolt = <1500000>;
 462                                 regulator-always-on;
 463                         };
 464
 465                         vgen4_reg: vgen4 {
 466                                 regulator-min-microvolt = <1200000>;
 467                                 regulator-max-microvolt = <1800000>;
 468                                 regulator-always-on;
 469                         };
 470
 471                         vgen5_reg: vgen5 {
 472                                 regulator-min-microvolt = <1800000>;
 473                                 regulator-max-microvolt = <2500000>;
 474                                 regulator-always-on;
 475                         };
 476
 477                         vgen6_reg: vgen6 {
 478                                 regulator-min-microvolt = <1800000>;
 479                                 regulator-max-microvolt = <2800000>;
 480                                 regulator-always-on;
 481                         };
 482                 };
 483         };
 484
 485         temp-sense@48 {
 486                 compatible = "national,lm75";
 487                 reg = <0x48>;
 488         };
 489
 490         cs2000: clkgen@4e {
 491                 compatible = "cirrus,cs2000-cp";
 492                 reg = <0x4e>;
 493                 #clock-cells = <0>;
 494                 clock-names = "clk_in", "ref_clk";
 495                 clocks = <&cs2000_in_dummy>, <&cs2000_ref>;
 496                 assigned-clocks = <&cs2000>;
 497                 assigned-clock-rates = <24000000>;
 498         };
 499
 500         eeprom@54 {
 501                 compatible = "at,24c128";
 502                 reg = <0x54>;
 503         };
 504
 505         ds1341: rtc@68 {
 506                 compatible = "dallas,ds1341";
 507                 reg = <0x68>;
 508         };
 509 };
 510
 511 &i2c3 {
 512         pinctrl-names = "default";
 513         pinctrl-0 = <&pinctrl_i2c3>;
 514         clock-frequency = <400000>;
 515         status = "okay";
 516
 517         codec1: codec@18 {
 518                 compatible = "ti,tlv320dac3100";
 519                 pinctrl-names = "default";
 520                 pinctrl-0 = <&pinctrl_codec1>;
 521                 reg = <0x18>;
 522                 #sound-dai-cells = <0>;
 523                 HPVDD-supply = <&reg_3p3v>;
 524                 SPRVDD-supply = <&reg_3p3v>;
 525                 SPLVDD-supply = <&reg_3p3v>;
 526                 AVDD-supply = <&reg_3p3v>;
 527                 IOVDD-supply = <&reg_3p3v>;
 528                 DVDD-supply = <&vgen4_reg>;
 529                 gpio-reset = <&gpio1 0 GPIO_ACTIVE_HIGH>;
 530         };
 531
 532         touchscreen@20 {
 533                 compatible = "syna,rmi4-i2c";
 534                 pinctrl-names = "default";
 535                 pinctrl-0 = <&pinctrl_ts>;
 536                 reg = <0x20>;
 537                 interrupt-parent = <&gpio1>;
 538                 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
 539                 vdd-supply = <&reg_5p0v_main>;
 540                 vio-supply = <&reg_3p3v>;
 541
 542                 #address-cells = <1>;
 543                 #size-cells = <0>;
 544
 545                 rmi4-f01@1 {
 546                         reg = <0x1>;
 547                         syna,nosleep-mode = <2>;
 548                 };
 549
 550                 rmi4-f11@11 {
 551                         reg = <0x11>;
 552                         touchscreen-inverted-y;
 553                         touchscreen-swapped-x-y;
 554                         syna,sensor-type = <1>;
 555                 };
 556
 557                 rmi4-f12@12 {
 558                         reg = <0x12>;
 559                         touchscreen-inverted-y;
 560                         touchscreen-swapped-x-y;
 561                         syna,sensor-type = <1>;
 562                 };
 563         };
 564
 565         hpa1: amp@60 {
 566                 compatible = "ti,tpa6130a2";
 567                 pinctrl-names = "default";
 568                 pinctrl-0 = <&pinctrl_tpa1>;
 569                 reg = <0x60>;
 570                 power-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
 571                 Vdd-supply = <&reg_5p0v_main>;
 572         };
 573 };
 574
 575 &ipu1_di0_disp0 {
 576         remote-endpoint = <&disp0_in_0>;
 577 };
 578
 579 &pcie {
 580         pinctrl-names = "default";
 581         pinctrl-0 = <&pinctrl_pcie>;
 582         reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
 583         status = "okay";
 584
 585         host@0 {
 586                 reg = <0 0 0 0 0>;
 587
 588                 #address-cells = <3>;
 589                 #size-cells = <2>;
 590
 591                 i210: i210@0 {
 592                         reg = <0 0 0 0 0>;
 593                 };
 594         };
 595 };
 596
 597 &usdhc2 {
 598         pinctrl-names = "default";
 599         pinctrl-0 = <&pinctrl_usdhc2>;
 600         bus-width = <4>;
 601         cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
 602         wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
 603         vmmc-supply = <&reg_3p3v_sd>;
 604         vqmmc-supply = <&reg_3p3v>;
 605         status = "okay";
 606 };
 607
 608 &usdhc3 {
 609         pinctrl-names = "default";
 610         pinctrl-0 = <&pinctrl_usdhc3>;
 611         bus-width = <4>;
 612         cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
 613         wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
 614         vmmc-supply = <&reg_3p3v_sd>;
 615         vqmmc-supply = <&reg_3p3v>;
 616         status = "okay";
 617 };
 618
 619 &usdhc4 {
 620         pinctrl-names = "default";
 621         pinctrl-0 = <&pinctrl_usdhc4>;
 622         bus-width = <8>;
 623         vmmc-supply = <&reg_3p3v>;
 624         vqmmc-supply = <&reg_3p3v>;
 625         non-removable;
 626         status = "okay";
 627 };
 628
 629 &sata {
 630         target-supply = <&reg_3p3v_ssd>;
 631         status = "okay";
 632 };
 633
 634 &fec {
 635         pinctrl-names = "default";
 636         pinctrl-0 = <&pinctrl_enet>;
 637         phy-mode = "rmii";
 638         phy-handle = <&phy>;
 639         phy-reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
 640         phy-reset-duration = <100>;
 641         phy-supply = <&reg_3p3v>;
 642         status = "okay";
 643
 644         mdio {
 645                 #address-cells = <1>;
 646                 #size-cells = <0>;
 647                 status = "okay";
 648
 649                 switch: switch@0 {
 650                         compatible = "marvell,mv88e6085";
 651                         pinctrl-0 = <&pinctrl_switch_irq>;
 652                         pinctrl-names = "default";
 653                         #address-cells = <1>;
 654                         #size-cells = <0>;
 655                         reg = <0>;
 656                         dsa,member = <0 0>;
 657                         eeprom-length = <512>;
 658                         interrupt-parent = <&gpio6>;
 659                         interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
 660                         interrupt-controller;
 661                         #interrupt-cells = <2>;
 662
 663                         ports {
 664                                 #address-cells = <1>;
 665                                 #size-cells = <0>;
 666
 667                                 port@0 {
 668                                         reg = <0>;
 669                                         label = "gigabit_proc";
 670                                         phy-handle = <&switchphy0>;
 671                                 };
 672
 673                                 port@1 {
 674                                         reg = <1>;
 675                                         label = "netaux";
 676                                         phy-handle = <&switchphy1>;
 677                                 };
 678
 679                                 port@2 {
 680                                         reg = <2>;
 681                                         label = "cpu";
 682                                         ethernet = <&fec>;
 683
 684                                         fixed-link {
 685                                                 speed = <100>;
 686                                                 full-duplex;
 687                                         };
 688                                 };
 689
 690                                 port@3 {
 691                                         reg = <3>;
 692                                         label = "netright";
 693                                         phy-handle = <&switchphy3>;
 694                                 };
 695
 696                                 port@4 {
 697                                         reg = <4>;
 698                                         label = "netleft";
 699                                         phy-handle = <&switchphy4>;
 700                                 };
 701                         };
 702
 703                         mdio {
 704                                 #address-cells = <1>;
 705                                 #size-cells = <0>;
 706
 707                                 switchphy0: switchphy@0 {
 708                                         reg = <0>;
 709                                         interrupt-parent = <&switch>;
 710                                         interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
 711                                 };
 712
 713                                 switchphy1: switchphy@1 {
 714                                         reg = <1>;
 715                                         interrupt-parent = <&switch>;
 716                                         interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
 717                                 };
 718
 719                                 switchphy2: switchphy@2 {
 720                                         reg = <2>;
 721                                         interrupt-parent = <&switch>;
 722                                         interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
 723                                 };
 724
 725                                 switchphy3: switchphy@3 {
 726                                         reg = <3>;
 727                                         interrupt-parent = <&switch>;
 728                                         interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
 729                                 };
 730
 731                                 switchphy4: switchphy@4 {
 732                                         reg = <4>;
 733                                         interrupt-parent = <&switch>;
 734                                         interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
 735                                 };
 736                         };
 737                 };
 738         };
 739 };
 740
 741 &usbh1 {
 742         vbus-supply = <&reg_5p0v_main>;
 743         disable-over-current;
 744         status = "okay";
 745 };
 746
 747 &usbotg {
 748         vbus-supply = <&reg_5p0v_user_usb>;
 749         disable-over-current;
 750         dr_mode = "host";
 751         status = "okay";
 752 };
 753
 754 &ssi1 {
 755         status = "okay";
 756 };
 757
 758 &ssi2 {
 759         status = "okay";
 760 };
 761
 762 &audmux {
 763         pinctrl-names = "default";
 764         pinctrl-0 = <&pinctrl_audmux>;
 765         status = "okay";
 766
 767         ssi1 {
 768                 fsl,audmux-port = <0>;
 769                 fsl,port-config = <
 770                         (IMX_AUDMUX_V2_PTCR_SYN |
 771                          IMX_AUDMUX_V2_PTCR_TFSEL(2) |
 772                          IMX_AUDMUX_V2_PTCR_TCSEL(2) |
 773                          IMX_AUDMUX_V2_PTCR_TFSDIR |
 774                          IMX_AUDMUX_V2_PTCR_TCLKDIR)
 775                         IMX_AUDMUX_V2_PDCR_RXDSEL(2)
 776                 >;
 777         };
 778
 779         aud3 {
 780                 fsl,audmux-port = <2>;
 781                 fsl,port-config = <
 782                         IMX_AUDMUX_V2_PTCR_SYN
 783                         IMX_AUDMUX_V2_PDCR_RXDSEL(0)
 784                 >;
 785         };
 786
 787         ssi2 {
 788                 fsl,audmux-port = <1>;
 789                 fsl,port-config = <
 790                         (IMX_AUDMUX_V2_PTCR_SYN |
 791                          IMX_AUDMUX_V2_PTCR_TFSEL(4) |
 792                          IMX_AUDMUX_V2_PTCR_TCSEL(4) |
 793                          IMX_AUDMUX_V2_PTCR_TFSDIR |
 794                          IMX_AUDMUX_V2_PTCR_TCLKDIR)
 795                         IMX_AUDMUX_V2_PDCR_RXDSEL(4)
 796                 >;
 797         };
 798
 799         aud5 {
 800                 fsl,audmux-port = <4>;
 801                 fsl,port-config = <
 802                         IMX_AUDMUX_V2_PTCR_SYN
 803                         IMX_AUDMUX_V2_PDCR_RXDSEL(1)
 804                 >;
 805         };
 806 };
 807
 808 &iomuxc {
 809         pinctrl_accel: accelgrp {
 810                 fsl,pins = <
 811                         MX6QDL_PAD_SD1_CMD__GPIO1_IO18          0x4001b000
 812                         MX6QDL_PAD_SD1_CLK__GPIO1_IO20          0x4001b000
 813                 >;
 814         };
 815
 816         pinctrl_audmux: audmuxgrp {
 817                 fsl,pins = <
 818                         MX6QDL_PAD_KEY_COL0__AUD5_TXC           0x130b0
 819                         MX6QDL_PAD_KEY_ROW0__AUD5_TXD           0x130b0
 820                         MX6QDL_PAD_KEY_COL1__AUD5_TXFS          0x130b0
 821                         MX6QDL_PAD_CSI0_DAT4__AUD3_TXC          0x130b0
 822                         MX6QDL_PAD_CSI0_DAT5__AUD3_TXD          0x130b0
 823                         MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS         0x130b0
 824                 >;
 825         };
 826
 827         pinctrl_codec1: dac1grp {
 828                 fsl,pins = <
 829                         MX6QDL_PAD_GPIO_0__GPIO1_IO00           0x40000038
 830                 >;
 831         };
 832
 833         pinctrl_codec2: dac2grp {
 834                 fsl,pins = <
 835                         MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x40000038
 836                 >;
 837         };
 838
 839         pinctrl_disp0: disp0grp {
 840                 fsl,pins = <
 841                         MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x100f9
 842                         MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x100f9
 843                         MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x100f9
 844                         MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x100f9
 845                         MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x100f9
 846                         MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x100f9
 847                         MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x100f9
 848                         MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x100f9
 849                         MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x100f9
 850                         MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x100f9
 851                         MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x100f9
 852                         MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x100f9
 853                         MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x100f9
 854                         MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x100f9
 855                         MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x100f9
 856                         MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x100f9
 857                         MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x100f9
 858                         MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x100f9
 859                         MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x100f9
 860                         MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x100f9
 861                         MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x100f9
 862                         MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x100f9
 863                         MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x100f9
 864                         MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x100f9
 865                         MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x100f9
 866                         MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x100f9
 867                         MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x100f9
 868                         MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x100f9
 869                 >;
 870         };
 871
 872         pinctrl_ecspi1: ecspi1grp {
 873                 fsl,pins = <
 874                         MX6QDL_PAD_EIM_D17__ECSPI1_MISO         0x100b1
 875                         MX6QDL_PAD_EIM_D18__ECSPI1_MOSI         0x100b1
 876                         MX6QDL_PAD_EIM_D16__ECSPI1_SCLK         0x100b1
 877                         MX6QDL_PAD_EIM_EB2__GPIO2_IO30          0x1b0b1
 878                 >;
 879         };
 880
 881         pinctrl_enet: enetgrp {
 882                 fsl,pins = <
 883                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x000b1
 884                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x100b1
 885                         MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN      0x100f5
 886                         MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN       0x100f5
 887                         MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0     0x100c0
 888                         MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1     0x100c0
 889                         MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0     0x100f5
 890                         MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1     0x100f5
 891                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x40010040
 892                         MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER       0x100b0
 893                         MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23     0x1b0b0
 894                 >;
 895         };
 896
 897         pinctrl_i2c1: i2c1grp {
 898                 fsl,pins = <
 899                         MX6QDL_PAD_CSI0_DAT8__I2C1_SDA          0x4001b8b1
 900                         MX6QDL_PAD_CSI0_DAT9__I2C1_SCL          0x4001b8b1
 901                 >;
 902         };
 903
 904         pinctrl_i2c2: i2c2grp {
 905                 fsl,pins = <
 906                         MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 907                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 908                 >;
 909         };
 910
 911         pinctrl_i2c3: i2c3grp {
 912                 fsl,pins = <
 913                         MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 914                         MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 915                 >;
 916         };
 917
 918         pinctrl_mdio1: bitbangmdiogrp {
 919                 fsl,pins = <
 920                         /* Bitbang MDIO for DEB Switch */
 921                         MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05       0x4001b030
 922                         MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04       0x40018830
 923                 >;
 924         };
 925
 926         pinctrl_pcie: pciegrp {
 927                 fsl,pins = <
 928                         MX6QDL_PAD_GPIO_17__GPIO7_IO12          0x10038
 929                 >;
 930         };
 931
 932         pinctrl_pfuze100_irq: pfuze100grp {
 933                 fsl,pins = <
 934                         MX6QDL_PAD_GPIO_18__GPIO7_IO13          0x40010000
 935                 >;
 936         };
 937
 938         pinctrl_reg_3p3v_sd: mmcsupply1grp {
 939                 fsl,pins = <
 940                         MX6QDL_PAD_SD3_RST__GPIO7_IO08          0x858
 941                 >;
 942         };
 943
 944         pinctrl_reg_user_usb: usbotggrp {
 945                 fsl,pins = <
 946                         MX6QDL_PAD_EIM_D22__GPIO3_IO22          0x40000038
 947                 >;
 948         };
 949
 950         pinctrl_rmii_phy_irq: phygrp {
 951                 fsl,pins = <
 952                         MX6QDL_PAD_EIM_D30__GPIO3_IO30          0x40010000
 953                 >;
 954         };
 955
 956         pinctrl_switch_irq: switchgrp {
 957                 fsl,pins = <
 958                         MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03       0x4001b000
 959                 >;
 960         };
 961
 962         pinctrl_tc358767: tc358767grp {
 963                 fsl,pins = <
 964                         MX6QDL_PAD_GPIO_9__GPIO1_IO09           0x10
 965                 >;
 966         };
 967
 968         pinctrl_tpa1: tpa6130-1grp {
 969                 fsl,pins = <
 970                         MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x40000038
 971                 >;
 972         };
 973
 974         pinctrl_tpa2: tpa6130-2grp {
 975                 fsl,pins = <
 976                         MX6QDL_PAD_GPIO_5__GPIO1_IO05           0x40000038
 977                 >;
 978         };
 979
 980         pinctrl_ts: tsgrp {
 981                 fsl,pins = <
 982                         MX6QDL_PAD_GPIO_8__GPIO1_IO08           0x1b0b0
 983                         MX6QDL_PAD_GPIO_7__GPIO1_IO07           0x1b0b0
 984                 >;
 985         };
 986
 987         pinctrl_uart1: uart1grp {
 988                 fsl,pins = <
 989                         MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA    0x1b0b1
 990                         MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA    0x1b0b1
 991                 >;
 992         };
 993
 994         pinctrl_uart3: uart3grp {
 995                 fsl,pins = <
 996                         MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
 997                         MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
 998                         MX6QDL_PAD_EIM_D31__UART3_RTS_B         0x1b0b1
 999                 >;
1000         };
1001
1002         pinctrl_uart4: uart4grp {
1003                 fsl,pins = <
1004                         MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA    0x1b0b1
1005                         MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA    0x1b0b1
1006                 >;
1007         };
1008
1009         pinctrl_usdhc2: usdhc2grp {
1010                 fsl,pins = <
1011                         MX6QDL_PAD_SD2_CMD__SD2_CMD             0x10059
1012                         MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10069
1013                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17059
1014                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17059
1015                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17059
1016                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17059
1017                         MX6QDL_PAD_NANDF_D3__GPIO2_IO03         0x40010040
1018                         MX6QDL_PAD_NANDF_D2__GPIO2_IO02         0x40010040
1019                 >;
1020         };
1021
1022         pinctrl_usdhc3: usdhc3grp {
1023                 fsl,pins = <
1024                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x10059
1025                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10069
1026                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
1027                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
1028                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
1029                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
1030                         MX6QDL_PAD_NANDF_D1__GPIO2_IO01         0x40010040
1031                         MX6QDL_PAD_NANDF_D0__GPIO2_IO00         0x40010040
1032
1033                 >;
1034         };
1035
1036         pinctrl_usdhc4: usdhc4grp {
1037                 fsl,pins = <
1038                         MX6QDL_PAD_SD4_CMD__SD4_CMD             0x17059
1039                         MX6QDL_PAD_SD4_CLK__SD4_CLK             0x10059
1040                         MX6QDL_PAD_SD4_DAT0__SD4_DATA0          0x17059
1041                         MX6QDL_PAD_SD4_DAT1__SD4_DATA1          0x17059
1042                         MX6QDL_PAD_SD4_DAT2__SD4_DATA2          0x17059
1043                         MX6QDL_PAD_SD4_DAT3__SD4_DATA3          0x17059
1044                         MX6QDL_PAD_SD4_DAT4__SD4_DATA4          0x17059
1045                         MX6QDL_PAD_SD4_DAT5__SD4_DATA5          0x17059
1046                         MX6QDL_PAD_SD4_DAT6__SD4_DATA6          0x17059
1047                         MX6QDL_PAD_SD4_DAT7__SD4_DATA7          0x17059
1048                         MX6QDL_PAD_NANDF_ALE__SD4_RESET         0x1b0b1
1049                 >;
1050         };
1051 };