arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi

   1 /*
   2  * Copyright (C) 2016-2017 Zodiac Inflight Innovations
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License
  11  *     version 2 as published by the Free Software Foundation.
  12  *
  13  *     This file is distributed in the hope that it will be useful,
  14  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *     GNU General Public License for more details.
  17  *
  18  * Or, alternatively,
  19  *
  20  *  b) Permission is hereby granted, free of charge, to any person
  21  *     obtaining a copy of this software and associated documentation
  22  *     files (the "Software"), to deal in the Software without
  23  *     restriction, including without limitation the rights to use,
  24  *     copy, modify, merge, publish, distribute, sublicense, and/or
  25  *     sell copies of the Software, and to permit persons to whom the
  26  *     Software is furnished to do so, subject to the following
  27  *     conditions:
  28  *
  29  *     The above copyright notice and this permission notice shall be
  30  *     included in all copies or substantial portions of the Software.
  31  *
  32  *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND,
  33  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  34  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  35  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  36  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  37  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  38  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  39  *     OTHER DEALINGS IN THE SOFTWARE.
  40  */
  41
  42 #include <dt-bindings/gpio/gpio.h>
  43 #include <dt-bindings/sound/fsl-imx-audmux.h>
  44
  45 / {
  46         chosen {
  47                 stdout-path = &uart1;
  48         };
  49
  50         aliases {
  51                 mdio-gpio0 = &mdio1;
  52                 rtc0 = &ds1341;
  53         };
  54
  55         mdio1: mdio {
  56                 compatible = "virtual,mdio-gpio";
  57                 #address-cells = <1>;
  58                 #size-cells = <0>;
  59                 pinctrl-names = "default";
  60                 pinctrl-0 = <&pinctrl_mdio1>;
  61                 gpios = <&gpio6 5 GPIO_ACTIVE_HIGH
  62                          &gpio6 4 GPIO_ACTIVE_HIGH>;
  63
  64                 phy: ethernet-phy@0 {
  65                         pinctrl-0 = <&pinctrl_rmii_phy_irq>;
  66                         pinctrl-names = "default";
  67                         reg = <0>;
  68                         interrupt-parent = <&gpio3>;
  69                         interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
  70                 };
  71         };
  72
  73         reg_28p0v: regulator-28p0v {
  74                 compatible = "regulator-fixed";
  75                 regulator-name = "28V_IN";
  76                 regulator-min-microvolt = <28000000>;
  77                 regulator-max-microvolt = <28000000>;
  78                 regulator-always-on;
  79         };
  80
  81         reg_12p0v: regulator-12p0v {
  82                 compatible = "regulator-fixed";
  83                 vin-supply = <&reg_28p0v>;
  84                 regulator-name = "12V_MAIN";
  85                 regulator-min-microvolt = <12000000>;
  86                 regulator-max-microvolt = <12000000>;
  87                 regulator-always-on;
  88         };
  89
  90         reg_5p0v_main: regulator-5p0v-main {
  91                 compatible = "regulator-fixed";
  92                 vin-supply = <&reg_12p0v>;
  93                 regulator-name = "5V_MAIN";
  94                 regulator-min-microvolt = <5000000>;
  95                 regulator-max-microvolt = <5000000>;
  96                 regulator-always-on;
  97         };
  98
  99         reg_5p0v_user_usb: regulator-5p0v-user-usb {
 100                 compatible = "regulator-fixed";
 101                 pinctrl-names = "default";
 102                 pinctrl-0 = <&pinctrl_reg_user_usb>;
 103                 vin-supply = <&reg_5p0v_main>;
 104                 regulator-name = "5V_USER_USB";
 105                 regulator-min-microvolt = <5000000>;
 106                 regulator-max-microvolt = <5000000>;
 107                 gpio = <&gpio3 22 GPIO_ACTIVE_LOW>;
 108                 startup-delay-us = <1000>;
 109         };
 110
 111         reg_3p3v_pmic: regulator-3p3v-pmic {
 112                 compatible = "regulator-fixed";
 113                 vin-supply = <&reg_12p0v>;
 114                 regulator-name = "PMIC_3V3";
 115                 regulator-min-microvolt = <3300000>;
 116                 regulator-max-microvolt = <3300000>;
 117                 regulator-always-on;
 118         };
 119
 120         reg_3p3v: regulator-3p3v {
 121                 compatible = "regulator-fixed";
 122                 vin-supply = <&reg_3p3v_pmic>;
 123                 regulator-name = "GEN_3V3";
 124                 regulator-min-microvolt = <3300000>;
 125                 regulator-max-microvolt = <3300000>;
 126                 regulator-always-on;
 127         };
 128
 129         reg_3p3v_sd: regulator-3p3v-sd {
 130                 compatible = "regulator-fixed";
 131                 pinctrl-names = "default";
 132                 pinctrl-0 = <&pinctrl_reg_3p3v_sd>;
 133                 vin-supply = <&reg_3p3v>;
 134                 regulator-name = "3V3_SD";
 135                 regulator-min-microvolt = <3300000>;
 136                 regulator-max-microvolt = <3300000>;
 137                 gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>;
 138                 startup-delay-us = <1000>;
 139                 enable-active-high;
 140                 regulator-always-on;
 141         };
 142
 143         reg_3p3v_display: regulator-3p3v-display {
 144                 compatible = "regulator-fixed";
 145                 vin-supply = <&reg_12p0v>;
 146                 regulator-name = "3V3_DISPLAY";
 147                 regulator-min-microvolt = <3300000>;
 148                 regulator-max-microvolt = <3300000>;
 149                 regulator-always-on;
 150         };
 151
 152         reg_3p3v_ssd: regulator-3p3v-ssd {
 153                 compatible = "regulator-fixed";
 154                 vin-supply = <&reg_12p0v>;
 155                 regulator-name = "3V3_SSD";
 156                 regulator-min-microvolt = <3300000>;
 157                 regulator-max-microvolt = <3300000>;
 158                 regulator-always-on;
 159         };
 160
 161         sound1 {
 162                 compatible = "simple-audio-card";
 163                 simple-audio-card,name = "Front";
 164                 simple-audio-card,format = "i2s";
 165                 simple-audio-card,bitclock-master = <&sound1_codec>;
 166                 simple-audio-card,frame-master = <&sound1_codec>;
 167                 simple-audio-card,widgets =
 168                         "Headphone", "Headphone Jack";
 169                 simple-audio-card,routing =
 170                         "Headphone Jack", "HPLEFT",
 171                         "Headphone Jack", "HPRIGHT",
 172                         "LEFTIN", "HPL",
 173                         "RIGHTIN", "HPR";
 174                 simple-audio-card,aux-devs = <&hpa1>;
 175
 176                 sound1_cpu: simple-audio-card,cpu {
 177                         sound-dai = <&ssi2>;
 178                 };
 179
 180                 sound1_codec: simple-audio-card,codec {
 181                         sound-dai = <&codec1>;
 182                         clocks = <&cs2000>;
 183                 };
 184         };
 185
 186         sound2 {
 187                 compatible = "simple-audio-card";
 188                 simple-audio-card,name = "Back";
 189                 simple-audio-card,format = "i2s";
 190                 simple-audio-card,bitclock-master = <&sound2_codec>;
 191                 simple-audio-card,frame-master = <&sound2_codec>;
 192                 simple-audio-card,widgets =
 193                         "Headphone", "Headphone Jack";
 194                 simple-audio-card,routing =
 195                         "Headphone Jack", "HPLEFT",
 196                         "Headphone Jack", "HPRIGHT",
 197                         "LEFTIN", "HPL",
 198                         "RIGHTIN", "HPR";
 199                 simple-audio-card,aux-devs = <&hpa2>;
 200
 201                 sound2_cpu: simple-audio-card,cpu {
 202                         sound-dai = <&ssi1>;
 203                 };
 204
 205                 sound2_codec: simple-audio-card,codec {
 206                         sound-dai = <&codec2>;
 207                         clocks = <&cs2000>;
 208                 };
 209         };
 210
 211         panel {
 212                 power-supply = <&reg_3p3v_display>;
 213                 status = "disabled";
 214
 215                 port {
 216                         panel_in: endpoint {
 217                                 remote-endpoint = <&lvds0_out>;
 218                         };
 219                 };
 220         };
 221
 222         disp0: disp0 {
 223                 #address-cells = <1>;
 224                 #size-cells = <0>;
 225                 compatible = "fsl,imx-parallel-display";
 226                 pinctrl-names = "default";
 227                 pinctrl-0 = <&pinctrl_disp0>;
 228                 status = "disabled";
 229
 230                 port@0 {
 231                         reg = <0>;
 232
 233                         disp0_in_0: endpoint {
 234                                 remote-endpoint = <&ipu1_di0_disp0>;
 235                         };
 236                 };
 237
 238                 port@1 {
 239                         reg = <1>;
 240
 241                         disp0_out: endpoint {
 242                                 remote-endpoint = <&tc358767_in>;
 243                         };
 244                 };
 245         };
 246
 247         cs2000_ref: cs2000-ref {
 248                 compatible = "fixed-clock";
 249                 #clock-cells = <0>;
 250                 clock-frequency = <24576000>;
 251         };
 252
 253         cs2000_in_dummy: cs2000-in-dummy {
 254                 compatible = "fixed-clock";
 255                 #clock-cells = <0>;
 256                 clock-frequency = <0>;
 257         };
 258
 259         edp_refclk: edp-refclk {
 260                 compatible = "fixed-clock";
 261                 #clock-cells = <0>;
 262                 clock-frequency = <19200000>;
 263         };
 264 };
 265
 266 &reg_arm {
 267         vin-supply = <&sw1a_reg>;
 268 };
 269
 270 &reg_pu {
 271         vin-supply = <&sw1c_reg>;
 272 };
 273
 274 &reg_soc {
 275         vin-supply = <&sw1c_reg>;
 276 };
 277
 278 &ldb {
 279         lvds-channel@0 {
 280                 port@4 {
 281                         reg = <4>;
 282
 283                         lvds0_out: endpoint {
 284                                 remote-endpoint = <&panel_in>;
 285                         };
 286                 };
 287         };
 288 };
 289
 290 &uart1 {
 291         pinctrl-names = "default";
 292         pinctrl-0 = <&pinctrl_uart1>;
 293         status = "okay";
 294 };
 295
 296 &uart3 {
 297         pinctrl-names = "default";
 298         pinctrl-0 = <&pinctrl_uart3>;
 299         uart-has-rtscts;
 300         linux,rs485-enabled-at-boot-time;
 301         status = "okay";
 302 };
 303
 304 &uart4 {
 305         pinctrl-names = "default";
 306         pinctrl-0 = <&pinctrl_uart4>;
 307         status = "okay";
 308
 309         rave-sp {
 310                 compatible = "zii,rave-sp-rdu2";
 311                 current-speed = <1000000>;
 312
 313                 watchdog {
 314                         compatible = "zii,rave-sp-watchdog";
 315                 };
 316         };
 317 };
 318
 319 &ecspi1 {
 320         pinctrl-names = "default";
 321         pinctrl-0 = <&pinctrl_ecspi1>;
 322         cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>;
 323         status = "okay";
 324
 325         flash@0 {
 326                 compatible = "st,m25p128", "jedec,spi-nor";
 327                 spi-max-frequency = <20000000>;
 328                 reg = <0>;
 329         };
 330 };
 331
 332 &i2c1 {
 333         pinctrl-names = "default";
 334         pinctrl-0 = <&pinctrl_i2c1>;
 335         clock-frequency = <100000>;
 336         status = "okay";
 337
 338         codec2: codec@18 {
 339                 compatible = "ti,tlv320dac3100";
 340                 pinctrl-names = "default";
 341                 pinctrl-0 = <&pinctrl_codec2>;
 342                 reg = <0x18>;
 343                 #sound-dai-cells = <0>;
 344                 HPVDD-supply = <&reg_3p3v>;
 345                 SPRVDD-supply = <&reg_3p3v>;
 346                 SPLVDD-supply = <&reg_3p3v>;
 347                 AVDD-supply = <&reg_3p3v>;
 348                 IOVDD-supply = <&reg_3p3v>;
 349                 DVDD-supply = <&vgen4_reg>;
 350                 gpio-reset = <&gpio1 2 GPIO_ACTIVE_HIGH>;
 351         };
 352
 353         accel@1c {
 354                 pinctrl-names = "default";
 355                 pinctrl-0 = <&pinctrl_accel>;
 356                 compatible = "fsl,mma8451";
 357                 reg = <0x1c>;
 358                 interrupt-parent = <&gpio1>;
 359                 interrupt-names = "int1", "int2";
 360                 interrupts = <18 IRQ_TYPE_LEVEL_LOW>, <20 IRQ_TYPE_LEVEL_LOW>;
 361         };
 362
 363         hpa2: amp@60 {
 364                 compatible = "ti,tpa6130a2";
 365                 pinctrl-names = "default";
 366                 pinctrl-0 = <&pinctrl_tpa2>;
 367                 reg = <0x60>;
 368                 power-gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
 369                 Vdd-supply = <&reg_5p0v_main>;
 370         };
 371
 372         edp-bridge@68 {
 373                 compatible = "toshiba,tc358767";
 374                 pinctrl-names = "default";
 375                 pinctrl-0 = <&pinctrl_tc358767>;
 376                 reg = <0x68>;
 377                 shutdown-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
 378                 clock-names = "ref";
 379                 clocks = <&edp_refclk>;
 380                 status = "disabled";
 381
 382                 ports {
 383                         #address-cells = <1>;
 384                         #size-cells = <0>;
 385
 386                         port@1 {
 387                                 reg = <1>;
 388
 389                                 tc358767_in: endpoint {
 390                                         remote-endpoint = <&disp0_out>;
 391                                 };
 392                         };
 393                 };
 394         };
 395 };
 396
 397 &i2c2 {
 398         pinctrl-names = "default";
 399         pinctrl-0 = <&pinctrl_i2c2>;
 400         clock-frequency = <100000>;
 401         status = "okay";
 402
 403         pmic@8 {
 404                 compatible = "fsl,pfuze100";
 405                 pinctrl-names = "default";
 406                 pinctrl-0 = <&pinctrl_pfuze100_irq>;
 407                 reg = <0x08>;
 408                 interrupt-parent = <&gpio7>;
 409                 interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
 410
 411                 regulators {
 412                         sw1a_reg: sw1ab {
 413                                 regulator-min-microvolt = <300000>;
 414                                 regulator-max-microvolt = <1875000>;
 415                                 regulator-boot-on;
 416                                 regulator-always-on;
 417                                 regulator-ramp-delay = <6250>;
 418                         };
 419
 420                         sw1c_reg: sw1c {
 421                                 regulator-min-microvolt = <300000>;
 422                                 regulator-max-microvolt = <1875000>;
 423                                 regulator-boot-on;
 424                                 regulator-always-on;
 425                                 regulator-ramp-delay = <6250>;
 426                         };
 427
 428                         sw2_reg: sw2 {
 429                                 regulator-min-microvolt = <800000>;
 430                                 regulator-max-microvolt = <3000000>;
 431                                 regulator-boot-on;
 432                                 regulator-always-on;
 433                         };
 434
 435                         sw3a_reg: sw3a {
 436                                 regulator-min-microvolt = <400000>;
 437                                 regulator-max-microvolt = <1500000>;
 438                                 regulator-boot-on;
 439                                 regulator-always-on;
 440                         };
 441
 442                         sw3b_reg: sw3b {
 443                                 regulator-min-microvolt = <400000>;
 444                                 regulator-max-microvolt = <1500000>;
 445                                 regulator-boot-on;
 446                                 regulator-always-on;
 447                         };
 448
 449                         sw4_reg: sw4 {
 450                                 regulator-min-microvolt = <800000>;
 451                                 regulator-max-microvolt = <1800000>;
 452                                 regulator-boot-on;
 453                                 regulator-always-on;
 454                         };
 455
 456                         snvs_reg: vsnvs {
 457                                 regulator-min-microvolt = <1000000>;
 458                                 regulator-max-microvolt = <3000000>;
 459                                 regulator-boot-on;
 460                                 regulator-always-on;
 461                         };
 462
 463                         vref_reg: vrefddr {
 464                                 regulator-boot-on;
 465                                 regulator-always-on;
 466                         };
 467
 468                         vgen2_reg: vgen2 {
 469                                 regulator-min-microvolt = <1000000>;
 470                                 regulator-max-microvolt = <1500000>;
 471                                 regulator-always-on;
 472                         };
 473
 474                         vgen4_reg: vgen4 {
 475                                 regulator-min-microvolt = <1200000>;
 476                                 regulator-max-microvolt = <1800000>;
 477                                 regulator-always-on;
 478                         };
 479
 480                         vgen5_reg: vgen5 {
 481                                 regulator-min-microvolt = <1800000>;
 482                                 regulator-max-microvolt = <2500000>;
 483                                 regulator-always-on;
 484                         };
 485
 486                         vgen6_reg: vgen6 {
 487                                 regulator-min-microvolt = <1800000>;
 488                                 regulator-max-microvolt = <2800000>;
 489                                 regulator-always-on;
 490                         };
 491                 };
 492         };
 493
 494         temp-sense@48 {
 495                 compatible = "national,lm75";
 496                 reg = <0x48>;
 497         };
 498
 499         cs2000: clkgen@4e {
 500                 compatible = "cirrus,cs2000-cp";
 501                 reg = <0x4e>;
 502                 #clock-cells = <0>;
 503                 clock-names = "clk_in", "ref_clk";
 504                 clocks = <&cs2000_in_dummy>, <&cs2000_ref>;
 505                 assigned-clocks = <&cs2000>;
 506                 assigned-clock-rates = <24000000>;
 507         };
 508
 509         eeprom@54 {
 510                 compatible = "atmel,24c128";
 511                 reg = <0x54>;
 512         };
 513
 514         ds1341: rtc@68 {
 515                 compatible = "dallas,ds1341";
 516                 reg = <0x68>;
 517         };
 518 };
 519
 520 &i2c3 {
 521         pinctrl-names = "default";
 522         pinctrl-0 = <&pinctrl_i2c3>;
 523         clock-frequency = <400000>;
 524         status = "okay";
 525
 526         codec1: codec@18 {
 527                 compatible = "ti,tlv320dac3100";
 528                 pinctrl-names = "default";
 529                 pinctrl-0 = <&pinctrl_codec1>;
 530                 reg = <0x18>;
 531                 #sound-dai-cells = <0>;
 532                 HPVDD-supply = <&reg_3p3v>;
 533                 SPRVDD-supply = <&reg_3p3v>;
 534                 SPLVDD-supply = <&reg_3p3v>;
 535                 AVDD-supply = <&reg_3p3v>;
 536                 IOVDD-supply = <&reg_3p3v>;
 537                 DVDD-supply = <&vgen4_reg>;
 538                 gpio-reset = <&gpio1 0 GPIO_ACTIVE_HIGH>;
 539         };
 540
 541         touchscreen@20 {
 542                 compatible = "syna,rmi4-i2c";
 543                 pinctrl-names = "default";
 544                 pinctrl-0 = <&pinctrl_ts>;
 545                 reg = <0x20>;
 546                 interrupt-parent = <&gpio1>;
 547                 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
 548                 vdd-supply = <&reg_5p0v_main>;
 549                 vio-supply = <&reg_3p3v>;
 550
 551                 #address-cells = <1>;
 552                 #size-cells = <0>;
 553
 554                 rmi4-f01@1 {
 555                         reg = <0x1>;
 556                         syna,nosleep-mode = <2>;
 557                 };
 558
 559                 rmi4-f11@11 {
 560                         reg = <0x11>;
 561                         touchscreen-inverted-y;
 562                         touchscreen-swapped-x-y;
 563                         syna,sensor-type = <1>;
 564                 };
 565
 566                 rmi4-f12@12 {
 567                         reg = <0x12>;
 568                         touchscreen-inverted-y;
 569                         touchscreen-swapped-x-y;
 570                         syna,sensor-type = <1>;
 571                 };
 572         };
 573
 574         hpa1: amp@60 {
 575                 compatible = "ti,tpa6130a2";
 576                 pinctrl-names = "default";
 577                 pinctrl-0 = <&pinctrl_tpa1>;
 578                 reg = <0x60>;
 579                 power-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
 580                 Vdd-supply = <&reg_5p0v_main>;
 581         };
 582 };
 583
 584 &ipu1_di0_disp0 {
 585         remote-endpoint = <&disp0_in_0>;
 586 };
 587
 588 &pcie {
 589         pinctrl-names = "default";
 590         pinctrl-0 = <&pinctrl_pcie>;
 591         reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
 592         status = "okay";
 593
 594         host@0 {
 595                 reg = <0 0 0 0 0>;
 596
 597                 #address-cells = <3>;
 598                 #size-cells = <2>;
 599
 600                 i210: i210@0 {
 601                         reg = <0 0 0 0 0>;
 602                 };
 603         };
 604 };
 605
 606 &usdhc2 {
 607         pinctrl-names = "default";
 608         pinctrl-0 = <&pinctrl_usdhc2>;
 609         bus-width = <4>;
 610         cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
 611         wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
 612         vmmc-supply = <&reg_3p3v_sd>;
 613         vqmmc-supply = <&reg_3p3v>;
 614         no-1-8-v;
 615         no-sdio;
 616         status = "okay";
 617 };
 618
 619 &usdhc3 {
 620         pinctrl-names = "default";
 621         pinctrl-0 = <&pinctrl_usdhc3>;
 622         bus-width = <4>;
 623         cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
 624         wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
 625         vmmc-supply = <&reg_3p3v_sd>;
 626         vqmmc-supply = <&reg_3p3v>;
 627         no-1-8-v;
 628         no-sdio;
 629         status = "okay";
 630 };
 631
 632 &usdhc4 {
 633         pinctrl-names = "default";
 634         pinctrl-0 = <&pinctrl_usdhc4>;
 635         bus-width = <8>;
 636         vmmc-supply = <&reg_3p3v>;
 637         vqmmc-supply = <&reg_3p3v>;
 638         no-1-8-v;
 639         non-removable;
 640         no-sdio;
 641         no-sd;
 642         status = "okay";
 643 };
 644
 645 &sata {
 646         target-supply = <&reg_3p3v_ssd>;
 647         status = "okay";
 648 };
 649
 650 &fec {
 651         pinctrl-names = "default";
 652         pinctrl-0 = <&pinctrl_enet>;
 653         phy-mode = "rmii";
 654         phy-handle = <&phy>;
 655         phy-reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
 656         phy-reset-duration = <100>;
 657         phy-supply = <&reg_3p3v>;
 658         status = "okay";
 659
 660         mdio {
 661                 #address-cells = <1>;
 662                 #size-cells = <0>;
 663                 status = "okay";
 664
 665                 switch: switch@0 {
 666                         compatible = "marvell,mv88e6085";
 667                         pinctrl-0 = <&pinctrl_switch_irq>;
 668                         pinctrl-names = "default";
 669                         #address-cells = <1>;
 670                         #size-cells = <0>;
 671                         reg = <0>;
 672                         dsa,member = <0 0>;
 673                         eeprom-length = <512>;
 674                         interrupt-parent = <&gpio6>;
 675                         interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
 676                         interrupt-controller;
 677                         #interrupt-cells = <2>;
 678
 679                         ports {
 680                                 #address-cells = <1>;
 681                                 #size-cells = <0>;
 682
 683                                 port@0 {
 684                                         reg = <0>;
 685                                         label = "gigabit_proc";
 686                                         phy-handle = <&switchphy0>;
 687                                 };
 688
 689                                 port@1 {
 690                                         reg = <1>;
 691                                         label = "netaux";
 692                                         phy-handle = <&switchphy1>;
 693                                 };
 694
 695                                 port@2 {
 696                                         reg = <2>;
 697                                         label = "cpu";
 698                                         ethernet = <&fec>;
 699
 700                                         fixed-link {
 701                                                 speed = <100>;
 702                                                 full-duplex;
 703                                         };
 704                                 };
 705
 706                                 port@3 {
 707                                         reg = <3>;
 708                                         label = "netright";
 709                                         phy-handle = <&switchphy3>;
 710                                 };
 711
 712                                 port@4 {
 713                                         reg = <4>;
 714                                         label = "netleft";
 715                                         phy-handle = <&switchphy4>;
 716                                 };
 717                         };
 718
 719                         mdio {
 720                                 #address-cells = <1>;
 721                                 #size-cells = <0>;
 722
 723                                 switchphy0: switchphy@0 {
 724                                         reg = <0>;
 725                                         interrupt-parent = <&switch>;
 726                                         interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
 727                                 };
 728
 729                                 switchphy1: switchphy@1 {
 730                                         reg = <1>;
 731                                         interrupt-parent = <&switch>;
 732                                         interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
 733                                 };
 734
 735                                 switchphy2: switchphy@2 {
 736                                         reg = <2>;
 737                                         interrupt-parent = <&switch>;
 738                                         interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
 739                                 };
 740
 741                                 switchphy3: switchphy@3 {
 742                                         reg = <3>;
 743                                         interrupt-parent = <&switch>;
 744                                         interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
 745                                 };
 746
 747                                 switchphy4: switchphy@4 {
 748                                         reg = <4>;
 749                                         interrupt-parent = <&switch>;
 750                                         interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
 751                                 };
 752                         };
 753                 };
 754         };
 755 };
 756
 757 &usbh1 {
 758         vbus-supply = <&reg_5p0v_main>;
 759         disable-over-current;
 760         status = "okay";
 761 };
 762
 763 &usbotg {
 764         vbus-supply = <&reg_5p0v_user_usb>;
 765         disable-over-current;
 766         dr_mode = "host";
 767         status = "okay";
 768 };
 769
 770 &ssi1 {
 771         status = "okay";
 772 };
 773
 774 &ssi2 {
 775         status = "okay";
 776 };
 777
 778 &audmux {
 779         pinctrl-names = "default";
 780         pinctrl-0 = <&pinctrl_audmux>;
 781         status = "okay";
 782
 783         ssi1 {
 784                 fsl,audmux-port = <0>;
 785                 fsl,port-config = <
 786                         (IMX_AUDMUX_V2_PTCR_SYN |
 787                          IMX_AUDMUX_V2_PTCR_TFSEL(2) |
 788                          IMX_AUDMUX_V2_PTCR_TCSEL(2) |
 789                          IMX_AUDMUX_V2_PTCR_TFSDIR |
 790                          IMX_AUDMUX_V2_PTCR_TCLKDIR)
 791                         IMX_AUDMUX_V2_PDCR_RXDSEL(2)
 792                 >;
 793         };
 794
 795         aud3 {
 796                 fsl,audmux-port = <2>;
 797                 fsl,port-config = <
 798                         IMX_AUDMUX_V2_PTCR_SYN
 799                         IMX_AUDMUX_V2_PDCR_RXDSEL(0)
 800                 >;
 801         };
 802
 803         ssi2 {
 804                 fsl,audmux-port = <1>;
 805                 fsl,port-config = <
 806                         (IMX_AUDMUX_V2_PTCR_SYN |
 807                          IMX_AUDMUX_V2_PTCR_TFSEL(4) |
 808                          IMX_AUDMUX_V2_PTCR_TCSEL(4) |
 809                          IMX_AUDMUX_V2_PTCR_TFSDIR |
 810                          IMX_AUDMUX_V2_PTCR_TCLKDIR)
 811                         IMX_AUDMUX_V2_PDCR_RXDSEL(4)
 812                 >;
 813         };
 814
 815         aud5 {
 816                 fsl,audmux-port = <4>;
 817                 fsl,port-config = <
 818                         IMX_AUDMUX_V2_PTCR_SYN
 819                         IMX_AUDMUX_V2_PDCR_RXDSEL(1)
 820                 >;
 821         };
 822 };
 823
 824 &wdog1 {
 825         status = "disabled";
 826 };
 827
 828 &iomuxc {
 829         pinctrl_accel: accelgrp {
 830                 fsl,pins = <
 831                         MX6QDL_PAD_SD1_CMD__GPIO1_IO18          0x4001b000
 832                         MX6QDL_PAD_SD1_CLK__GPIO1_IO20          0x4001b000
 833                 >;
 834         };
 835
 836         pinctrl_audmux: audmuxgrp {
 837                 fsl,pins = <
 838                         MX6QDL_PAD_KEY_COL0__AUD5_TXC           0x130b0
 839                         MX6QDL_PAD_KEY_ROW0__AUD5_TXD           0x130b0
 840                         MX6QDL_PAD_KEY_COL1__AUD5_TXFS          0x130b0
 841                         MX6QDL_PAD_CSI0_DAT4__AUD3_TXC          0x130b0
 842                         MX6QDL_PAD_CSI0_DAT5__AUD3_TXD          0x130b0
 843                         MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS         0x130b0
 844                 >;
 845         };
 846
 847         pinctrl_codec1: dac1grp {
 848                 fsl,pins = <
 849                         MX6QDL_PAD_GPIO_0__GPIO1_IO00           0x40000038
 850                 >;
 851         };
 852
 853         pinctrl_codec2: dac2grp {
 854                 fsl,pins = <
 855                         MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x40000038
 856                 >;
 857         };
 858
 859         pinctrl_disp0: disp0grp {
 860                 fsl,pins = <
 861                         MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x100f9
 862                         MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x100f9
 863                         MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x100f9
 864                         MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x100f9
 865                         MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x100f9
 866                         MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x100f9
 867                         MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x100f9
 868                         MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x100f9
 869                         MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x100f9
 870                         MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x100f9
 871                         MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x100f9
 872                         MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x100f9
 873                         MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x100f9
 874                         MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x100f9
 875                         MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x100f9
 876                         MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x100f9
 877                         MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x100f9
 878                         MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x100f9
 879                         MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x100f9
 880                         MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x100f9
 881                         MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x100f9
 882                         MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x100f9
 883                         MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x100f9
 884                         MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x100f9
 885                         MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x100f9
 886                         MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x100f9
 887                         MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x100f9
 888                         MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x100f9
 889                 >;
 890         };
 891
 892         pinctrl_ecspi1: ecspi1grp {
 893                 fsl,pins = <
 894                         MX6QDL_PAD_EIM_D17__ECSPI1_MISO         0x100b1
 895                         MX6QDL_PAD_EIM_D18__ECSPI1_MOSI         0x100b1
 896                         MX6QDL_PAD_EIM_D16__ECSPI1_SCLK         0x100b1
 897                         MX6QDL_PAD_EIM_EB2__GPIO2_IO30          0x1b0b1
 898                 >;
 899         };
 900
 901         pinctrl_enet: enetgrp {
 902                 fsl,pins = <
 903                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x000b1
 904                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x100b1
 905                         MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN      0x100f5
 906                         MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN       0x100f5
 907                         MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0     0x100c0
 908                         MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1     0x100c0
 909                         MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0     0x100f5
 910                         MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1     0x100f5
 911                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x40010040
 912                         MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER       0x100b0
 913                         MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23     0x1b0b0
 914                 >;
 915         };
 916
 917         pinctrl_i2c1: i2c1grp {
 918                 fsl,pins = <
 919                         MX6QDL_PAD_CSI0_DAT8__I2C1_SDA          0x4001b8b1
 920                         MX6QDL_PAD_CSI0_DAT9__I2C1_SCL          0x4001b8b1
 921                 >;
 922         };
 923
 924         pinctrl_i2c2: i2c2grp {
 925                 fsl,pins = <
 926                         MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 927                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 928                 >;
 929         };
 930
 931         pinctrl_i2c3: i2c3grp {
 932                 fsl,pins = <
 933                         MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 934                         MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 935                 >;
 936         };
 937
 938         pinctrl_mdio1: bitbangmdiogrp {
 939                 fsl,pins = <
 940                         /* Bitbang MDIO for DEB Switch */
 941                         MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05       0x4001b030
 942                         MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04       0x40018830
 943                 >;
 944         };
 945
 946         pinctrl_pcie: pciegrp {
 947                 fsl,pins = <
 948                         MX6QDL_PAD_GPIO_17__GPIO7_IO12          0x10038
 949                 >;
 950         };
 951
 952         pinctrl_pfuze100_irq: pfuze100grp {
 953                 fsl,pins = <
 954                         MX6QDL_PAD_GPIO_18__GPIO7_IO13          0x40010000
 955                 >;
 956         };
 957
 958         pinctrl_reg_3p3v_sd: mmcsupply1grp {
 959                 fsl,pins = <
 960                         MX6QDL_PAD_SD3_RST__GPIO7_IO08          0x858
 961                 >;
 962         };
 963
 964         pinctrl_reg_user_usb: usbotggrp {
 965                 fsl,pins = <
 966                         MX6QDL_PAD_EIM_D22__GPIO3_IO22          0x40000038
 967                 >;
 968         };
 969
 970         pinctrl_rmii_phy_irq: phygrp {
 971                 fsl,pins = <
 972                         MX6QDL_PAD_EIM_D30__GPIO3_IO30          0x40010000
 973                 >;
 974         };
 975
 976         pinctrl_switch_irq: switchgrp {
 977                 fsl,pins = <
 978                         MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03       0x4001b000
 979                 >;
 980         };
 981
 982         pinctrl_tc358767: tc358767grp {
 983                 fsl,pins = <
 984                         MX6QDL_PAD_GPIO_9__GPIO1_IO09           0x10
 985                 >;
 986         };
 987
 988         pinctrl_tpa1: tpa6130-1grp {
 989                 fsl,pins = <
 990                         MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x40000038
 991                 >;
 992         };
 993
 994         pinctrl_tpa2: tpa6130-2grp {
 995                 fsl,pins = <
 996                         MX6QDL_PAD_GPIO_5__GPIO1_IO05           0x40000038
 997                 >;
 998         };
 999
1000         pinctrl_ts: tsgrp {
1001                 fsl,pins = <
1002                         MX6QDL_PAD_GPIO_8__GPIO1_IO08           0x1b0b0
1003                         MX6QDL_PAD_GPIO_7__GPIO1_IO07           0x1b0b0
1004                 >;
1005         };
1006
1007         pinctrl_uart1: uart1grp {
1008                 fsl,pins = <
1009                         MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA    0x1b0b1
1010                         MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA    0x1b0b1
1011                 >;
1012         };
1013
1014         pinctrl_uart3: uart3grp {
1015                 fsl,pins = <
1016                         MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
1017                         MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
1018                         MX6QDL_PAD_EIM_D31__UART3_RTS_B         0x1b0b1
1019                 >;
1020         };
1021
1022         pinctrl_uart4: uart4grp {
1023                 fsl,pins = <
1024                         MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA    0x1b0b1
1025                         MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA    0x1b0b1
1026                 >;
1027         };
1028
1029         pinctrl_usdhc2: usdhc2grp {
1030                 fsl,pins = <
1031                         MX6QDL_PAD_SD2_CMD__SD2_CMD             0x10059
1032                         MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10069
1033                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17059
1034                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17059
1035                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17059
1036                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17059
1037                         MX6QDL_PAD_NANDF_D3__GPIO2_IO03         0x40010040
1038                         MX6QDL_PAD_NANDF_D2__GPIO2_IO02         0x40010040
1039                 >;
1040         };
1041
1042         pinctrl_usdhc3: usdhc3grp {
1043                 fsl,pins = <
1044                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x10059
1045                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10069
1046                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
1047                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
1048                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
1049                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
1050                         MX6QDL_PAD_NANDF_D1__GPIO2_IO01         0x40010040
1051                         MX6QDL_PAD_NANDF_D0__GPIO2_IO00         0x40010040
1052
1053                 >;
1054         };
1055
1056         pinctrl_usdhc4: usdhc4grp {
1057                 fsl,pins = <
1058                         MX6QDL_PAD_SD4_CMD__SD4_CMD             0x17059
1059                         MX6QDL_PAD_SD4_CLK__SD4_CLK             0x10059
1060                         MX6QDL_PAD_SD4_DAT0__SD4_DATA0          0x17059
1061                         MX6QDL_PAD_SD4_DAT1__SD4_DATA1          0x17059
1062                         MX6QDL_PAD_SD4_DAT2__SD4_DATA2          0x17059
1063                         MX6QDL_PAD_SD4_DAT3__SD4_DATA3          0x17059
1064                         MX6QDL_PAD_SD4_DAT4__SD4_DATA4          0x17059
1065                         MX6QDL_PAD_SD4_DAT5__SD4_DATA5          0x17059
1066                         MX6QDL_PAD_SD4_DAT6__SD4_DATA6          0x17059
1067                         MX6QDL_PAD_SD4_DAT7__SD4_DATA7          0x17059
1068                         MX6QDL_PAD_NANDF_ALE__SD4_RESET         0x1b0b1
1069                 >;
1070         };
1071 };