arch/arm/boot/dts/imx6qdl-gw53xx.dtsi

   1 /*
   2  * Copyright 2013 Gateworks Corporation
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License. You may obtain a copy of the GNU General Public License
   6  * Version 2 or later at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  */
  11
  12 #include <dt-bindings/gpio/gpio.h>
  13
  14 / {
  15         /* these are used by bootloader for disabling nodes */
  16         aliases {
  17                 ethernet1 = &eth1;
  18                 led0 = &led0;
  19                 led1 = &led1;
  20                 led2 = &led2;
  21                 nand = &gpmi;
  22                 ssi0 = &ssi1;
  23                 usb0 = &usbh1;
  24                 usb1 = &usbotg;
  25         };
  26
  27         chosen {
  28                 bootargs = "console=ttymxc1,115200";
  29         };
  30
  31         backlight {
  32                 compatible = "pwm-backlight";
  33                 pwms = <&pwm4 0 5000000>;
  34                 brightness-levels = <0 4 8 16 32 64 128 255>;
  35                 default-brightness-level = <7>;
  36         };
  37
  38         leds {
  39                 compatible = "gpio-leds";
  40                 pinctrl-names = "default";
  41                 pinctrl-0 = <&pinctrl_gpio_leds>;
  42
  43                 led0: user1 {
  44                         label = "user1";
  45                         gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
  46                         default-state = "on";
  47                         linux,default-trigger = "heartbeat";
  48                 };
  49
  50                 led1: user2 {
  51                         label = "user2";
  52                         gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
  53                         default-state = "off";
  54                 };
  55
  56                 led2: user3 {
  57                         label = "user3";
  58                         gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
  59                         default-state = "off";
  60                 };
  61         };
  62
  63         memory {
  64                 reg = <0x10000000 0x40000000>;
  65         };
  66
  67         pps {
  68                 compatible = "pps-gpio";
  69                 pinctrl-names = "default";
  70                 pinctrl-0 = <&pinctrl_pps>;
  71                 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
  72                 status = "okay";
  73         };
  74
  75         reg_1p0v: regulator-1p0v {
  76                 compatible = "regulator-fixed";
  77                 regulator-name = "1P0V";
  78                 regulator-min-microvolt = <1000000>;
  79                 regulator-max-microvolt = <1000000>;
  80                 regulator-always-on;
  81         };
  82
  83         reg_3p3v: regulator-3p3v {
  84                 compatible = "regulator-fixed";
  85                 regulator-name = "3P3V";
  86                 regulator-min-microvolt = <3300000>;
  87                 regulator-max-microvolt = <3300000>;
  88                 regulator-always-on;
  89         };
  90
  91         reg_usb_h1_vbus: regulator-usb-h1-vbus {
  92                 compatible = "regulator-fixed";
  93                 regulator-name = "usb_h1_vbus";
  94                 regulator-min-microvolt = <5000000>;
  95                 regulator-max-microvolt = <5000000>;
  96                 regulator-always-on;
  97         };
  98
  99         reg_usb_otg_vbus: regulator-usb-otg-vbus {
 100                 compatible = "regulator-fixed";
 101                 regulator-name = "usb_otg_vbus";
 102                 regulator-min-microvolt = <5000000>;
 103                 regulator-max-microvolt = <5000000>;
 104                 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
 105                 enable-active-high;
 106         };
 107
 108         sound {
 109                 compatible = "fsl,imx6q-ventana-sgtl5000",
 110                              "fsl,imx-audio-sgtl5000";
 111                 model = "sgtl5000-audio";
 112                 ssi-controller = <&ssi1>;
 113                 audio-codec = <&codec>;
 114                 audio-routing =
 115                         "MIC_IN", "Mic Jack",
 116                         "Mic Jack", "Mic Bias",
 117                         "Headphone Jack", "HP_OUT";
 118                 mux-int-port = <1>;
 119                 mux-ext-port = <4>;
 120         };
 121 };
 122
 123 &audmux {
 124         pinctrl-names = "default";
 125         pinctrl-0 = <&pinctrl_audmux>;
 126         status = "okay";
 127 };
 128
 129 &can1 {
 130         pinctrl-names = "default";
 131         pinctrl-0 = <&pinctrl_flexcan1>;
 132         status = "okay";
 133 };
 134
 135 &clks {
 136         assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
 137                           <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
 138         assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
 139                                  <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
 140 };
 141
 142 &fec {
 143         pinctrl-names = "default";
 144         pinctrl-0 = <&pinctrl_enet>;
 145         phy-mode = "rgmii-id";
 146         phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
 147         status = "okay";
 148 };
 149
 150 &gpmi {
 151         pinctrl-names = "default";
 152         pinctrl-0 = <&pinctrl_gpmi_nand>;
 153         status = "okay";
 154 };
 155
 156 &hdmi {
 157         ddc-i2c-bus = <&i2c3>;
 158         status = "okay";
 159 };
 160
 161 &i2c1 {
 162         clock-frequency = <100000>;
 163         pinctrl-names = "default";
 164         pinctrl-0 = <&pinctrl_i2c1>;
 165         status = "okay";
 166
 167         eeprom1: eeprom@50 {
 168                 compatible = "atmel,24c02";
 169                 reg = <0x50>;
 170                 pagesize = <16>;
 171         };
 172
 173         eeprom2: eeprom@51 {
 174                 compatible = "atmel,24c02";
 175                 reg = <0x51>;
 176                 pagesize = <16>;
 177         };
 178
 179         eeprom3: eeprom@52 {
 180                 compatible = "atmel,24c02";
 181                 reg = <0x52>;
 182                 pagesize = <16>;
 183         };
 184
 185         eeprom4: eeprom@53 {
 186                 compatible = "atmel,24c02";
 187                 reg = <0x53>;
 188                 pagesize = <16>;
 189         };
 190
 191         gpio: pca9555@23 {
 192                 compatible = "nxp,pca9555";
 193                 reg = <0x23>;
 194                 gpio-controller;
 195                 #gpio-cells = <2>;
 196         };
 197
 198         rtc: ds1672@68 {
 199                 compatible = "dallas,ds1672";
 200                 reg = <0x68>;
 201         };
 202 };
 203
 204 &i2c2 {
 205         clock-frequency = <100000>;
 206         pinctrl-names = "default";
 207         pinctrl-0 = <&pinctrl_i2c2>;
 208         status = "okay";
 209
 210         ltc3676: pmic@3c {
 211                 compatible = "lltc,ltc3676";
 212                 reg = <0x3c>;
 213                 interrupt-parent = <&gpio1>;
 214                 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
 215
 216                 regulators {
 217                         /* VDD_SOC (1+R1/R2 = 1.635) */
 218                         reg_vdd_soc: sw1 {
 219                                 regulator-name = "vddsoc";
 220                                 regulator-min-microvolt = <674400>;
 221                                 regulator-max-microvolt = <1308000>;
 222                                 lltc,fb-voltage-divider = <127000 200000>;
 223                                 regulator-ramp-delay = <7000>;
 224                                 regulator-boot-on;
 225                                 regulator-always-on;
 226                         };
 227
 228                         /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */
 229                         reg_1p8v: sw2 {
 230                                 regulator-name = "vdd1p8";
 231                                 regulator-min-microvolt = <1033310>;
 232                                 regulator-max-microvolt = <2004000>;
 233                                 lltc,fb-voltage-divider = <301000 200000>;
 234                                 regulator-ramp-delay = <7000>;
 235                                 regulator-boot-on;
 236                                 regulator-always-on;
 237                         };
 238
 239                         /* VDD_ARM (1+R1/R2 = 1.635) */
 240                         reg_vdd_arm: sw3 {
 241                                 regulator-name = "vddarm";
 242                                 regulator-min-microvolt = <674400>;
 243                                 regulator-max-microvolt = <1308000>;
 244                                 lltc,fb-voltage-divider = <127000 200000>;
 245                                 regulator-ramp-delay = <7000>;
 246                                 regulator-boot-on;
 247                                 regulator-always-on;
 248                         };
 249
 250                         /* VDD_DDR (1+R1/R2 = 2.105) */
 251                         reg_vdd_ddr: sw4 {
 252                                 regulator-name = "vddddr";
 253                                 regulator-min-microvolt = <868310>;
 254                                 regulator-max-microvolt = <1684000>;
 255                                 lltc,fb-voltage-divider = <221000 200000>;
 256                                 regulator-ramp-delay = <7000>;
 257                                 regulator-boot-on;
 258                                 regulator-always-on;
 259                         };
 260
 261                         /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
 262                         reg_2p5v: ldo2 {
 263                                 regulator-name = "vdd2p5";
 264                                 regulator-min-microvolt = <2490375>;
 265                                 regulator-max-microvolt = <2490375>;
 266                                 lltc,fb-voltage-divider = <487000 200000>;
 267                                 regulator-boot-on;
 268                                 regulator-always-on;
 269                         };
 270
 271                         /* VDD_AUD_1P8: Audio codec */
 272                         reg_aud_1p8v: ldo3 {
 273                                 regulator-name = "vdd1p8a";
 274                                 regulator-min-microvolt = <1800000>;
 275                                 regulator-max-microvolt = <1800000>;
 276                                 regulator-boot-on;
 277                         };
 278
 279                         /* VDD_HIGH (1+R1/R2 = 4.17) */
 280                         reg_3p0v: ldo4 {
 281                                 regulator-name = "vdd3p0";
 282                                 regulator-min-microvolt = <3023250>;
 283                                 regulator-max-microvolt = <3023250>;
 284                                 lltc,fb-voltage-divider = <634000 200000>;
 285                                 regulator-boot-on;
 286                                 regulator-always-on;
 287                         };
 288                 };
 289         };
 290 };
 291
 292 &i2c3 {
 293         clock-frequency = <100000>;
 294         pinctrl-names = "default";
 295         pinctrl-0 = <&pinctrl_i2c3>;
 296         status = "okay";
 297
 298         codec: sgtl5000@0a {
 299                 compatible = "fsl,sgtl5000";
 300                 reg = <0x0a>;
 301                 clocks = <&clks IMX6QDL_CLK_CKO>;
 302                 VDDA-supply = <&reg_1p8v>;
 303                 VDDIO-supply = <&reg_3p3v>;
 304         };
 305
 306         touchscreen: egalax_ts@04 {
 307                 compatible = "eeti,egalax_ts";
 308                 reg = <0x04>;
 309                 interrupt-parent = <&gpio1>;
 310                 interrupts = <11 2>;
 311                 wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
 312         };
 313 };
 314
 315 &ldb {
 316         status = "okay";
 317
 318         lvds-channel@0 {
 319                 fsl,data-mapping = "spwg";
 320                 fsl,data-width = <18>;
 321                 status = "okay";
 322
 323                 display-timings {
 324                         native-mode = <&timing0>;
 325                         timing0: hsd100pxn1 {
 326                                 clock-frequency = <65000000>;
 327                                 hactive = <1024>;
 328                                 vactive = <768>;
 329                                 hback-porch = <220>;
 330                                 hfront-porch = <40>;
 331                                 vback-porch = <21>;
 332                                 vfront-porch = <7>;
 333                                 hsync-len = <60>;
 334                                 vsync-len = <10>;
 335                         };
 336                 };
 337         };
 338 };
 339
 340 &pcie {
 341         pinctrl-names = "default";
 342         pinctrl-0 = <&pinctrl_pcie>;
 343         reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
 344         status = "okay";
 345
 346         eth1: sky2@8 { /* MAC/PHY on bus 8 */
 347                 compatible = "marvell,sky2";
 348         };
 349 };
 350
 351 &pwm2 {
 352         pinctrl-names = "default";
 353         pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
 354         status = "disabled";
 355 };
 356
 357 &pwm3 {
 358         pinctrl-names = "default";
 359         pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
 360         status = "disabled";
 361 };
 362
 363 &pwm4 {
 364         pinctrl-names = "default";
 365         pinctrl-0 = <&pinctrl_pwm4>;
 366         status = "okay";
 367 };
 368
 369 &ssi1 {
 370         status = "okay";
 371 };
 372
 373 &uart1 {
 374         pinctrl-names = "default";
 375         pinctrl-0 = <&pinctrl_uart1>;
 376         uart-has-rtscts;
 377         rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
 378         status = "okay";
 379 };
 380
 381 &uart2 {
 382         pinctrl-names = "default";
 383         pinctrl-0 = <&pinctrl_uart2>;
 384         status = "okay";
 385 };
 386
 387 &uart5 {
 388         pinctrl-names = "default";
 389         pinctrl-0 = <&pinctrl_uart5>;
 390         status = "okay";
 391 };
 392
 393 &usbotg {
 394         vbus-supply = <&reg_usb_otg_vbus>;
 395         pinctrl-names = "default";
 396         pinctrl-0 = <&pinctrl_usbotg>;
 397         disable-over-current;
 398         status = "okay";
 399 };
 400
 401 &usbh1 {
 402         vbus-supply = <&reg_usb_h1_vbus>;
 403         status = "okay";
 404 };
 405
 406 &usdhc3 {
 407         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 408         pinctrl-0 = <&pinctrl_usdhc3>;
 409         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 410         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 411         cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
 412         vmmc-supply = <&reg_3p3v>;
 413         no-1-8-v; /* firmware will remove if board revision supports */
 414         status = "okay";
 415 };
 416
 417 &wdog1 {
 418         pinctrl-names = "default";
 419         pinctrl-0 = <&pinctrl_wdog>;
 420         fsl,ext-reset-output;
 421 };
 422
 423 &iomuxc {
 424         imx6qdl-gw53xx {
 425                 pinctrl_audmux: audmuxgrp {
 426                         fsl,pins = <
 427                                 MX6QDL_PAD_SD2_DAT0__AUD4_RXD           0x130b0
 428                                 MX6QDL_PAD_SD2_DAT3__AUD4_TXC           0x130b0
 429                                 MX6QDL_PAD_SD2_DAT2__AUD4_TXD           0x110b0
 430                                 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS          0x130b0
 431                                 MX6QDL_PAD_GPIO_0__CCM_CLKO1            0x130b0 /* AUD4_MCK */
 432                         >;
 433                 };
 434
 435                 pinctrl_enet: enetgrp {
 436                         fsl,pins = <
 437                                 MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 438                                 MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
 439                                 MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
 440                                 MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 441                                 MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 442                                 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
 443                                 MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
 444                                 MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
 445                                 MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
 446                                 MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
 447                                 MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
 448                                 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
 449                                 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 450                                 MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 451                                 MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 452                                 MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
 453                         >;
 454                 };
 455
 456                 pinctrl_flexcan1: flexcan1grp {
 457                         fsl,pins = <
 458                                 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX        0x1b0b1
 459                                 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX        0x1b0b1
 460                                 MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x4001b0b0 /* CAN_STBY */
 461                         >;
 462                 };
 463
 464                 pinctrl_gpio_leds: gpioledsgrp {
 465                         fsl,pins = <
 466                                 MX6QDL_PAD_KEY_COL0__GPIO4_IO06   0x1b0b0
 467                                 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07   0x1b0b0
 468                                 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15   0x1b0b0
 469                         >;
 470                 };
 471
 472                 pinctrl_gpmi_nand: gpminandgrp {
 473                         fsl,pins = <
 474                                 MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
 475                                 MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
 476                                 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
 477                                 MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
 478                                 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
 479                                 MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
 480                                 MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
 481                                 MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
 482                                 MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
 483                                 MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
 484                                 MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
 485                                 MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
 486                                 MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
 487                                 MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
 488                                 MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
 489                         >;
 490                 };
 491
 492                 pinctrl_i2c1: i2c1grp {
 493                         fsl,pins = <
 494                                 MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 495                                 MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 496                         >;
 497                 };
 498
 499                 pinctrl_i2c2: i2c2grp {
 500                         fsl,pins = <
 501                                 MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 502                                 MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 503                         >;
 504                 };
 505
 506                 pinctrl_i2c3: i2c3grp {
 507                         fsl,pins = <
 508                                 MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 509                                 MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 510                         >;
 511                 };
 512
 513                 pinctrl_pcie: pciegrp {
 514                         fsl,pins = <
 515                                 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */
 516                                 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29  0x1b0b0 /* PCIE RST */
 517                         >;
 518                 };
 519
 520                 pinctrl_pmic: pmicgrp {
 521                         fsl,pins = <
 522                                 MX6QDL_PAD_GPIO_8__GPIO1_IO08           0x0001b0b0 /* PMIC_IRQ# */
 523                         >;
 524                 };
 525
 526                 pinctrl_pps: ppsgrp {
 527                         fsl,pins = <
 528                                 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26        0x1b0b1
 529                         >;
 530                 };
 531
 532                 pinctrl_pwm2: pwm2grp {
 533                         fsl,pins = <
 534                                 MX6QDL_PAD_SD1_DAT2__PWM2_OUT           0x1b0b1
 535                         >;
 536                 };
 537
 538                 pinctrl_pwm3: pwm3grp {
 539                         fsl,pins = <
 540                                 MX6QDL_PAD_SD1_DAT1__PWM3_OUT           0x1b0b1
 541                         >;
 542                 };
 543
 544                 pinctrl_pwm4: pwm4grp {
 545                         fsl,pins = <
 546                                 MX6QDL_PAD_SD1_CMD__PWM4_OUT            0x1b0b1
 547                         >;
 548                 };
 549
 550                 pinctrl_uart1: uart1grp {
 551                         fsl,pins = <
 552                                 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
 553                                 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA      0x1b0b1
 554                                 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01         0x4001b0b1 /* TEN */
 555                         >;
 556                 };
 557
 558                 pinctrl_uart2: uart2grp {
 559                         fsl,pins = <
 560                                 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 561                                 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 562                         >;
 563                 };
 564
 565                 pinctrl_uart5: uart5grp {
 566                         fsl,pins = <
 567                                 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA      0x1b0b1
 568                                 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA      0x1b0b1
 569                         >;
 570                 };
 571
 572                 pinctrl_usbotg: usbotggrp {
 573                         fsl,pins = <
 574                                 MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
 575                                 MX6QDL_PAD_EIM_D22__GPIO3_IO22          0x1b0b0 /* PWR_EN */
 576                                 MX6QDL_PAD_KEY_COL4__GPIO4_IO14         0x1b0b0 /* OC */
 577                         >;
 578                 };
 579
 580                 pinctrl_usdhc3: usdhc3grp {
 581                         fsl,pins = <
 582                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 583                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 584                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 585                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 586                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 587                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 588                                 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x17059 /* CD */
 589                                 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x17059
 590                         >;
 591                 };
 592
 593                 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
 594                         fsl,pins = <
 595                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170b9
 596                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100b9
 597                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170b9
 598                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170b9
 599                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170b9
 600                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170b9
 601                                 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x170b9 /* CD */
 602                                 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x170b9
 603                         >;
 604                 };
 605
 606                 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
 607                         fsl,pins = <
 608                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170f9
 609                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100f9
 610                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170f9
 611                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170f9
 612                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170f9
 613                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170f9
 614                                 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x170f9 /* CD */
 615                                 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x170f9
 616                         >;
 617                 };
 618
 619                 pinctrl_wdog: wdoggrp {
 620                         fsl,pins = <
 621                                 MX6QDL_PAD_DISP0_DAT8__WDOG1_B          0x1b0b0
 622                         >;
 623                 };
 624         };
 625 };