arch/arm/boot/dts/imx6qdl-colibri.dtsi

   1 /*
   2  * Copyright 2014-2016 Toradex AG
   3  * Copyright 2012 Freescale Semiconductor, Inc.
   4  * Copyright 2011 Linaro Ltd.
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License
  13  *     version 2 as published by the Free Software Foundation.
  14  *
  15  *     This file is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  * Or, alternatively,
  21  *
  22  *  b) Permission is hereby granted, free of charge, to any person
  23  *     obtaining a copy of this software and associated documentation
  24  *     files (the "Software"), to deal in the Software without
  25  *     restriction, including without limitation the rights to use,
  26  *     copy, modify, merge, publish, distribute, sublicense, and/or
  27  *     sell copies of the Software, and to permit persons to whom the
  28  *     Software is furnished to do so, subject to the following
  29  *     conditions:
  30  *
  31  *     The above copyright notice and this permission notice shall be
  32  *     included in all copies or substantial portions of the Software.
  33  *
  34  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  36  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  38  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  40  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  41  *     OTHER DEALINGS IN THE SOFTWARE.
  42  */
  43
  44 #include <dt-bindings/gpio/gpio.h>
  45
  46 / {
  47         model = "Toradex Colibri iMX6DL/S Module";
  48         compatible = "toradex,colibri_imx6dl", "fsl,imx6dl";
  49
  50         backlight: backlight {
  51                 compatible = "pwm-backlight";
  52                 pinctrl-names = "default";
  53                 pinctrl-0 = <&pinctrl_gpio_bl_on>;
  54                 pwms = <&pwm3 0 5000000>;
  55                 enable-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */
  56                 status = "disabled";
  57         };
  58
  59         reg_module_3v3: regulator-module-3v3 {
  60                 compatible = "regulator-fixed";
  61                 regulator-name = "+V3.3";
  62                 regulator-min-microvolt = <3300000>;
  63                 regulator-max-microvolt = <3300000>;
  64                 regulator-always-on;
  65         };
  66
  67         reg_module_3v3_audio: regulator-module-3v3-audio {
  68                 compatible = "regulator-fixed";
  69                 regulator-name = "+V3.3_AUDIO";
  70                 regulator-min-microvolt = <3300000>;
  71                 regulator-max-microvolt = <3300000>;
  72                 regulator-always-on;
  73         };
  74
  75         reg_usb_host_vbus: regulator-usb-host-vbus {
  76                 compatible = "regulator-fixed";
  77                 pinctrl-names = "default";
  78                 pinctrl-0 = <&pinctrl_regulator_usbh_pwr>;
  79                 regulator-name = "usb_host_vbus";
  80                 regulator-min-microvolt = <5000000>;
  81                 regulator-max-microvolt = <5000000>;
  82                 gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; /* USBH_PEN */
  83                 status = "disabled";
  84         };
  85
  86         sound {
  87                 compatible = "fsl,imx-audio-sgtl5000";
  88                 model = "imx6dl-colibri-sgtl5000";
  89                 ssi-controller = <&ssi1>;
  90                 audio-codec = <&codec>;
  91                 audio-routing =
  92                         "Headphone Jack", "HP_OUT",
  93                         "LINE_IN", "Line In Jack",
  94                         "MIC_IN", "Mic Jack",
  95                         "Mic Jack", "Mic Bias";
  96                 mux-int-port = <1>;
  97                 mux-ext-port = <5>;
  98         };
  99
 100         /* Optional S/PDIF in on SODIMM 88 and out on SODIMM 90, 137 or 168 */
 101         sound_spdif: sound-spdif {
 102                 compatible = "fsl,imx-audio-spdif";
 103                 model = "imx-spdif";
 104                 spdif-controller = <&spdif>;
 105                 spdif-in;
 106                 spdif-out;
 107                 status = "disabled";
 108         };
 109 };
 110
 111 &audmux {
 112         pinctrl-names = "default";
 113         pinctrl-0 = <&pinctrl_audmux &pinctrl_mic_gnd>;
 114         status = "okay";
 115 };
 116
 117 /* Optional on SODIMM 55/63 */
 118 &can1 {
 119         pinctrl-names = "default";
 120         pinctrl-0 = <&pinctrl_flexcan1>;
 121         status = "disabled";
 122 };
 123
 124 /* Optional on SODIMM 178/188 */
 125 &can2 {
 126         pinctrl-names = "default";
 127         pinctrl-0 = <&pinctrl_flexcan2>;
 128         status = "disabled";
 129 };
 130
 131 /* Colibri SSP */
 132 &ecspi4 {
 133         cs-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
 134         pinctrl-names = "default";
 135         pinctrl-0 = <&pinctrl_ecspi4>;
 136         status = "disabled";
 137 };
 138
 139 &fec {
 140         pinctrl-names = "default";
 141         pinctrl-0 = <&pinctrl_enet>;
 142         phy-mode = "rmii";
 143         phy-handle = <&ethphy>;
 144         status = "okay";
 145
 146         mdio {
 147                 #address-cells = <1>;
 148                 #size-cells = <0>;
 149
 150                 ethphy: ethernet-phy@0 {
 151                         reg = <0>;
 152                         micrel,led-mode = <0>;
 153                 };
 154         };
 155 };
 156
 157 &hdmi {
 158         pinctrl-names = "default";
 159         pinctrl-0 = <&pinctrl_hdmi_ddc>;
 160         status = "disabled";
 161 };
 162
 163 /*
 164  * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
 165  * touch screen controller
 166  */
 167 &i2c2 {
 168         clock-frequency = <100000>;
 169         pinctrl-names = "default";
 170         pinctrl-0 = <&pinctrl_i2c2>;
 171         status = "okay";
 172
 173         pmic: pfuze100@8 {
 174                 compatible = "fsl,pfuze100";
 175                 reg = <0x08>;
 176
 177                 regulators {
 178                         sw1a_reg: sw1ab {
 179                                 regulator-min-microvolt = <300000>;
 180                                 regulator-max-microvolt = <1875000>;
 181                                 regulator-boot-on;
 182                                 regulator-always-on;
 183                                 regulator-ramp-delay = <6250>;
 184                         };
 185
 186                         sw1c_reg: sw1c {
 187                                 regulator-min-microvolt = <300000>;
 188                                 regulator-max-microvolt = <1875000>;
 189                                 regulator-boot-on;
 190                                 regulator-always-on;
 191                                 regulator-ramp-delay = <6250>;
 192                         };
 193
 194                         sw3a_reg: sw3a {
 195                                 regulator-min-microvolt = <400000>;
 196                                 regulator-max-microvolt = <1975000>;
 197                                 regulator-boot-on;
 198                                 regulator-always-on;
 199                         };
 200
 201                         swbst_reg: swbst {
 202                                 regulator-min-microvolt = <5000000>;
 203                                 regulator-max-microvolt = <5150000>;
 204                                 regulator-boot-on;
 205                                 regulator-always-on;
 206                         };
 207
 208                         snvs_reg: vsnvs {
 209                                 regulator-min-microvolt = <1000000>;
 210                                 regulator-max-microvolt = <3000000>;
 211                                 regulator-boot-on;
 212                                 regulator-always-on;
 213                         };
 214
 215                         vref_reg: vrefddr {
 216                                 regulator-boot-on;
 217                                 regulator-always-on;
 218                         };
 219
 220                         /* vgen1: unused */
 221
 222                         vgen2_reg: vgen2 {
 223                                 regulator-min-microvolt = <800000>;
 224                                 regulator-max-microvolt = <1550000>;
 225                                 regulator-boot-on;
 226                                 regulator-always-on;
 227                         };
 228
 229                         /* vgen3: unused */
 230
 231                         vgen4_reg: vgen4 {
 232                                 regulator-min-microvolt = <1800000>;
 233                                 regulator-max-microvolt = <1800000>;
 234                                 regulator-boot-on;
 235                                 regulator-always-on;
 236                         };
 237
 238                         vgen5_reg: vgen5 {
 239                                 regulator-min-microvolt = <1800000>;
 240                                 regulator-max-microvolt = <3300000>;
 241                                 regulator-boot-on;
 242                                 regulator-always-on;
 243                         };
 244
 245                         vgen6_reg: vgen6 {
 246                                 regulator-min-microvolt = <1800000>;
 247                                 regulator-max-microvolt = <3300000>;
 248                                 regulator-boot-on;
 249                                 regulator-always-on;
 250                         };
 251                 };
 252         };
 253
 254         codec: sgtl5000@a {
 255                 compatible = "fsl,sgtl5000";
 256                 reg = <0x0a>;
 257                 clocks = <&clks IMX6QDL_CLK_CKO>;
 258                 VDDA-supply = <&reg_module_3v3_audio>;
 259                 VDDIO-supply = <&reg_module_3v3>;
 260                 VDDD-supply = <&vgen4_reg>;
 261                 lrclk-strength = <3>;
 262         };
 263
 264         /* STMPE811 touch screen controller */
 265         stmpe811@41 {
 266                 compatible = "st,stmpe811";
 267                 pinctrl-names = "default";
 268                 pinctrl-0 = <&pinctrl_touch_int>;
 269                 reg = <0x41>;
 270                 interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
 271                 interrupt-parent = <&gpio6>;
 272                 interrupt-controller;
 273                 id = <0>;
 274                 blocks = <0x5>;
 275                 irq-trigger = <0x1>;
 276                 /* 3.25 MHz ADC clock speed */
 277                 st,adc-freq = <1>;
 278                 /* 12-bit ADC */
 279                 st,mod-12b = <1>;
 280                 /* internal ADC reference */
 281                 st,ref-sel = <0>;
 282                 /* ADC converstion time: 80 clocks */
 283                 st,sample-time = <4>;
 284
 285                 stmpe_touchscreen {
 286                         compatible = "st,stmpe-ts";
 287                         /* 8 sample average control */
 288                         st,ave-ctrl = <3>;
 289                         /* 7 length fractional part in z */
 290                         st,fraction-z = <7>;
 291                         /*
 292                          * 50 mA typical 80 mA max touchscreen drivers
 293                          * current limit value
 294                          */
 295                         st,i-drive = <1>;
 296                         /* 1 ms panel driver settling time */
 297                         st,settling = <3>;
 298                         /* 5 ms touch detect interrupt delay */
 299                         st,touch-det-delay = <5>;
 300                 };
 301
 302                 stmpe_adc {
 303                         compatible = "st,stmpe-adc";
 304                         /* forbid to use ADC channels 3-0 (touch) */
 305                         st,norequest-mask = <0x0F>;
 306                 };
 307         };
 308 };
 309
 310 /*
 311  * I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board)
 312  */
 313 &i2c3 {
 314         clock-frequency = <100000>;
 315         pinctrl-names = "default", "recovery";
 316         pinctrl-0 = <&pinctrl_i2c3>;
 317         pinctrl-1 = <&pinctrl_i2c3_recovery>;
 318         scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 319         sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 320         status = "disabled";
 321 };
 322
 323 /* Colibri PWM<B> */
 324 &pwm1 {
 325         pinctrl-names = "default";
 326         pinctrl-0 = <&pinctrl_pwm1>;
 327         status = "disabled";
 328 };
 329
 330 /* Colibri PWM<D> */
 331 &pwm2 {
 332         pinctrl-names = "default";
 333         pinctrl-0 = <&pinctrl_pwm2>;
 334         status = "disabled";
 335 };
 336
 337 /* Colibri PWM<A> */
 338 &pwm3 {
 339         pinctrl-names = "default";
 340         pinctrl-0 = <&pinctrl_pwm3>;
 341         status = "disabled";
 342 };
 343
 344 /* Colibri PWM<C> */
 345 &pwm4 {
 346         pinctrl-names = "default";
 347         pinctrl-0 = <&pinctrl_pwm4>;
 348         status = "disabled";
 349 };
 350
 351 /* Optional S/PDIF out on SODIMM 137 */
 352 &spdif {
 353         pinctrl-names = "default";
 354         pinctrl-0 = <&pinctrl_spdif>;
 355         status = "disabled";
 356 };
 357
 358 &ssi1 {
 359         status = "okay";
 360 };
 361
 362 /* Colibri UART_A */
 363 &uart1 {
 364         pinctrl-names = "default";
 365         pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>;
 366         fsl,dte-mode;
 367         uart-has-rtscts;
 368         status = "disabled";
 369 };
 370
 371 /* Colibri UART_B */
 372 &uart2 {
 373         pinctrl-names = "default";
 374         pinctrl-0 = <&pinctrl_uart2_dte>;
 375         fsl,dte-mode;
 376         uart-has-rtscts;
 377         status = "disabled";
 378 };
 379
 380 /* Colibri UART_C */
 381 &uart3 {
 382         pinctrl-names = "default";
 383         pinctrl-0 = <&pinctrl_uart3_dte>;
 384         fsl,dte-mode;
 385         status = "disabled";
 386 };
 387
 388 &usbotg {
 389         pinctrl-names = "default";
 390         disable-over-current;
 391         dr_mode = "peripheral";
 392         status = "disabled";
 393 };
 394
 395 /* Colibri MMC */
 396 &usdhc1 {
 397         pinctrl-names = "default";
 398         pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>;
 399         cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */
 400         disable-wp;
 401         vqmmc-supply = <&reg_module_3v3>;
 402         bus-width = <4>;
 403         no-1-8-v;
 404         status = "disabled";
 405 };
 406
 407 /* eMMC */
 408 &usdhc3 {
 409         pinctrl-names = "default";
 410         pinctrl-0 = <&pinctrl_usdhc3>;
 411         vqmmc-supply = <&reg_module_3v3>;
 412         bus-width = <8>;
 413         no-1-8-v;
 414         non-removable;
 415         status = "okay";
 416 };
 417
 418 &weim {
 419         pinctrl-names = "default";
 420         pinctrl-0 = <&pinctrl_weim_sram  &pinctrl_weim_cs0
 421                      &pinctrl_weim_cs1   &pinctrl_weim_cs2
 422                      &pinctrl_weim_rdnwr &pinctrl_weim_npwe>;
 423         #address-cells = <2>;
 424         #size-cells = <1>;
 425         status = "disabled";
 426 };
 427
 428 &iomuxc {
 429         pinctrl_audmux: audmuxgrp {
 430                 fsl,pins = <
 431                         MX6QDL_PAD_KEY_COL0__AUD5_TXC   0x130b0
 432                         MX6QDL_PAD_KEY_ROW0__AUD5_TXD   0x130b0
 433                         MX6QDL_PAD_KEY_COL1__AUD5_TXFS  0x130b0
 434                         MX6QDL_PAD_KEY_ROW1__AUD5_RXD   0x130b0
 435                         /* SGTL5000 sys_mclk */
 436                         MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x000b0
 437                 >;
 438         };
 439
 440         pinctrl_cam_mclk: cammclkgrp {
 441                 fsl,pins = <
 442                         /* Parallel Camera CAM sys_mclk */
 443                         MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0
 444                 >;
 445         };
 446
 447         pinctrl_ecspi4: ecspi4grp {
 448                 fsl,pins = <
 449                         MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
 450                         MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
 451                         MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
 452                         /* SPI CS */
 453                         MX6QDL_PAD_EIM_A25__GPIO5_IO02  0x000b1
 454                 >;
 455         };
 456
 457         pinctrl_enet: enetgrp {
 458                 fsl,pins = <
 459                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 460                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 461                         MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0     0x1b0b0
 462                         MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1     0x1b0b0
 463                         MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER       0x1b0b0
 464                         MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN       0x1b0b0
 465                         MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0     0x1b0b0
 466                         MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1     0x1b0b0
 467                         MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN      0x1b0b0
 468                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK     ((1<<30) | 0x1b0b0)
 469                 >;
 470         };
 471
 472         pinctrl_flexcan1: flexcan1grp {
 473                 fsl,pins = <
 474                         MX6QDL_PAD_GPIO_7__FLEXCAN1_TX          0x1b0b0
 475                         MX6QDL_PAD_GPIO_8__FLEXCAN1_RX          0x1b0b0
 476                 >;
 477         };
 478
 479         pinctrl_flexcan2: flexcan2grp {
 480                 fsl,pins = <
 481                         MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX        0x1b0b0
 482                         MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX        0x1b0b0
 483                 >;
 484         };
 485
 486         pinctrl_gpio_bl_on: gpioblon {
 487                 fsl,pins = <
 488                         MX6QDL_PAD_EIM_D26__GPIO3_IO26          0x1b0b0
 489                 >;
 490         };
 491
 492         pinctrl_gpio_keys: gpiokeys {
 493                 fsl,pins = <
 494                         MX6QDL_PAD_EIM_A16__GPIO2_IO22          0x130b0
 495                 >;
 496         };
 497
 498         pinctrl_hdmi_ddc: hdmiddcgrp {
 499                 fsl,pins = <
 500                         MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
 501                         MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
 502                 >;
 503         };
 504
 505         pinctrl_i2c2: i2c2grp {
 506                 fsl,pins = <
 507                         MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
 508                         MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
 509                 >;
 510         };
 511
 512         pinctrl_i2c3: i2c3grp {
 513                 fsl,pins = <
 514                         MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
 515                         MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
 516                 >;
 517         };
 518
 519         pinctrl_i2c3_recovery: i2c3recoverygrp {
 520                 fsl,pins = <
 521                         MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1
 522                         MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1
 523                 >;
 524         };
 525
 526         pinctrl_ipu1_csi0: ipu1csi0grp { /* Parallel Camera */
 527                 fsl,pins = <
 528                         MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12    0xb0b1
 529                         MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13    0xb0b1
 530                         MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14    0xb0b1
 531                         MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15    0xb0b1
 532                         MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16    0xb0b1
 533                         MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17    0xb0b1
 534                         MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18    0xb0b1
 535                         MX6QDL_PAD_EIM_A24__IPU1_CSI1_DATA19    0xb0b1
 536                         MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK    0xb0b1
 537                         MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC     0xb0b1
 538                         MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC     0xb0b1
 539                         /* Disable PWM pins on camera interface */
 540                         MX6QDL_PAD_SD4_DAT1__GPIO2_IO09         0x40
 541                         MX6QDL_PAD_GPIO_1__GPIO1_IO01           0x40
 542                 >;
 543         };
 544
 545         pinctrl_ipu1_lcdif: ipu1lcdifgrp {
 546                 fsl,pins = <
 547                         MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK      0xa1
 548                         MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15            0xa1
 549                         MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02             0xa1
 550                         MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03             0xa1
 551                         MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00        0xa1
 552                         MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01        0xa1
 553                         MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02        0xa1
 554                         MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03        0xa1
 555                         MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04        0xa1
 556                         MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05        0xa1
 557                         MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06        0xa1
 558                         MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07        0xa1
 559                         MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08        0xa1
 560                         MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09        0xa1
 561                         MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10       0xa1
 562                         MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11       0xa1
 563                         MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12       0xa1
 564                         MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13       0xa1
 565                         MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14       0xa1
 566                         MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15       0xa1
 567                         MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16       0xa1
 568                         MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17       0xa1
 569                 >;
 570         };
 571
 572         pinctrl_mic_gnd: gpiomicgnd {
 573                 fsl,pins = <
 574                         /* Controls Mic GND, PU or '1' pull Mic GND to GND */
 575                         MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x1b0b0
 576                 >;
 577         };
 578
 579         pinctrl_mmc_cd: gpiommccd {
 580                 fsl,pins = <
 581                         MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x1b0b1
 582                 >;
 583         };
 584
 585         pinctrl_pwm1: pwm1grp {
 586                 fsl,pins = <
 587                         MX6QDL_PAD_GPIO_9__PWM1_OUT     0x1b0b1
 588                 >;
 589         };
 590
 591         pinctrl_pwm2: pwm2grp {
 592                 fsl,pins = <
 593                         MX6QDL_PAD_GPIO_1__PWM2_OUT     0x1b0b1
 594                         MX6QDL_PAD_EIM_A21__GPIO2_IO17  0x00040
 595                 >;
 596         };
 597
 598         pinctrl_pwm3: pwm3grp {
 599                 fsl,pins = <
 600                         MX6QDL_PAD_SD4_DAT1__PWM3_OUT   0x1b0b1
 601                         MX6QDL_PAD_EIM_A22__GPIO2_IO16  0x00040
 602                 >;
 603         };
 604
 605         pinctrl_pwm4: pwm4grp {
 606                 fsl,pins = <
 607                         MX6QDL_PAD_SD4_DAT2__PWM4_OUT   0x1b0b1
 608                 >;
 609         };
 610
 611         pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp {
 612                 fsl,pins = <
 613                         /* USBH_EN */
 614                         MX6QDL_PAD_EIM_D31__GPIO3_IO31  0x0f058
 615                 >;
 616         };
 617
 618         pinctrl_spdif: spdifgrp {
 619                 fsl,pins = <
 620                         MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
 621                 >;
 622         };
 623
 624         pinctrl_touch_int: gpiotouchintgrp {
 625                 fsl,pins = <
 626                         /* STMPE811 interrupt */
 627                         MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x1b0b0
 628                 >;
 629         };
 630
 631         pinctrl_uart1_dce: uart1dcegrp {
 632                 fsl,pins = <
 633                         MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
 634                         MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
 635                 >;
 636         };
 637
 638         /* DTE mode */
 639         pinctrl_uart1_dte: uart1dtegrp {
 640                 fsl,pins = <
 641                         MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1
 642                         MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1
 643                         MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1
 644                         MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1
 645                 >;
 646         };
 647
 648         /* Additional DTR, DSR, DCD */
 649         pinctrl_uart1_ctrl: uart1ctrlgrp {
 650                 fsl,pins = <
 651                         MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0
 652                         MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0
 653                         MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0
 654                 >;
 655         };
 656
 657         pinctrl_uart2_dte: uart2dtegrp {
 658                 fsl,pins = <
 659                         MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA      0x1b0b1
 660                         MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA      0x1b0b1
 661                         MX6QDL_PAD_SD4_DAT6__UART2_RTS_B        0x1b0b1
 662                         MX6QDL_PAD_SD4_DAT5__UART2_CTS_B        0x1b0b1
 663                 >;
 664         };
 665
 666         pinctrl_uart3_dte: uart3dtegrp {
 667                 fsl,pins = <
 668                         MX6QDL_PAD_SD4_CLK__UART3_TX_DATA       0x1b0b1
 669                         MX6QDL_PAD_SD4_CMD__UART3_RX_DATA       0x1b0b1
 670                 >;
 671         };
 672
 673         pinctrl_usbc_det: usbcdetgrp {
 674                 fsl,pins = <
 675                         /* USBC_DET */
 676                         MX6QDL_PAD_GPIO_17__GPIO7_IO12          0x1b0b0
 677                         /* USBC_DET_EN */
 678                         MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26     0x0f058
 679                         /* USBC_DET_OVERWRITE */
 680                         MX6QDL_PAD_RGMII_RXC__GPIO6_IO30        0x0f058
 681                 >;
 682         };
 683
 684         pinctrl_usdhc1: usdhc1grp {
 685                 fsl,pins = <
 686                         MX6QDL_PAD_SD1_CMD__SD1_CMD     0x17071
 687                         MX6QDL_PAD_SD1_CLK__SD1_CLK     0x10071
 688                         MX6QDL_PAD_SD1_DAT0__SD1_DATA0  0x17071
 689                         MX6QDL_PAD_SD1_DAT1__SD1_DATA1  0x17071
 690                         MX6QDL_PAD_SD1_DAT2__SD1_DATA2  0x17071
 691                         MX6QDL_PAD_SD1_DAT3__SD1_DATA3  0x17071
 692                 >;
 693         };
 694
 695         pinctrl_usdhc3: usdhc3grp {
 696                 fsl,pins = <
 697                         MX6QDL_PAD_SD3_CMD__SD3_CMD     0x17059
 698                         MX6QDL_PAD_SD3_CLK__SD3_CLK     0x10059
 699                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0  0x17059
 700                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1  0x17059
 701                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2  0x17059
 702                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3  0x17059
 703                         MX6QDL_PAD_SD3_DAT4__SD3_DATA4  0x17059
 704                         MX6QDL_PAD_SD3_DAT5__SD3_DATA5  0x17059
 705                         MX6QDL_PAD_SD3_DAT6__SD3_DATA6  0x17059
 706                         MX6QDL_PAD_SD3_DAT7__SD3_DATA7  0x17059
 707                         /* eMMC reset */
 708                         MX6QDL_PAD_SD3_RST__SD3_RESET   0x17059
 709                 >;
 710         };
 711
 712         pinctrl_weim_cs0: weimcs0grp {
 713                 fsl,pins = <
 714                         /* nEXT_CS0 */
 715                         MX6QDL_PAD_EIM_CS0__EIM_CS0_B   0xb0b1
 716                 >;
 717         };
 718
 719         pinctrl_weim_cs1: weimcs1grp {
 720                 fsl,pins = <
 721                         /* nEXT_CS1 */
 722                         MX6QDL_PAD_EIM_CS1__EIM_CS1_B   0xb0b1
 723                 >;
 724         };
 725
 726         pinctrl_weim_cs2: weimcs2grp {
 727                 fsl,pins = <
 728                         /* nEXT_CS2 */
 729                         MX6QDL_PAD_SD2_DAT1__EIM_CS2_B  0xb0b1
 730                 >;
 731         };
 732
 733         pinctrl_weim_sram: weimsramgrp {
 734                 fsl,pins = <
 735                         MX6QDL_PAD_EIM_OE__EIM_OE_B             0xb0b1
 736                         MX6QDL_PAD_EIM_RW__EIM_RW               0xb0b1
 737                         /* Data */
 738                         MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00     0x1b0b0
 739                         MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01       0x1b0b0
 740                         MX6QDL_PAD_CSI0_DAT4__EIM_DATA02        0x1b0b0
 741                         MX6QDL_PAD_CSI0_DAT5__EIM_DATA03        0x1b0b0
 742                         MX6QDL_PAD_CSI0_DAT6__EIM_DATA04        0x1b0b0
 743                         MX6QDL_PAD_CSI0_DAT7__EIM_DATA05        0x1b0b0
 744                         MX6QDL_PAD_CSI0_DAT8__EIM_DATA06        0x1b0b0
 745                         MX6QDL_PAD_CSI0_DAT9__EIM_DATA07        0x1b0b0
 746                         MX6QDL_PAD_CSI0_DAT12__EIM_DATA08       0x1b0b0
 747                         MX6QDL_PAD_CSI0_DAT13__EIM_DATA09       0x1b0b0
 748                         MX6QDL_PAD_CSI0_DAT14__EIM_DATA10       0x1b0b0
 749                         MX6QDL_PAD_CSI0_DAT15__EIM_DATA11       0x1b0b0
 750                         MX6QDL_PAD_CSI0_DAT16__EIM_DATA12       0x1b0b0
 751                         MX6QDL_PAD_CSI0_DAT17__EIM_DATA13       0x1b0b0
 752                         MX6QDL_PAD_CSI0_DAT18__EIM_DATA14       0x1b0b0
 753                         MX6QDL_PAD_CSI0_DAT19__EIM_DATA15       0x1b0b0
 754                         /* Address */
 755                         MX6QDL_PAD_EIM_DA15__EIM_AD15           0xb0b1
 756                         MX6QDL_PAD_EIM_DA14__EIM_AD14           0xb0b1
 757                         MX6QDL_PAD_EIM_DA13__EIM_AD13           0xb0b1
 758                         MX6QDL_PAD_EIM_DA12__EIM_AD12           0xb0b1
 759                         MX6QDL_PAD_EIM_DA11__EIM_AD11           0xb0b1
 760                         MX6QDL_PAD_EIM_DA10__EIM_AD10           0xb0b1
 761                         MX6QDL_PAD_EIM_DA9__EIM_AD09            0xb0b1
 762                         MX6QDL_PAD_EIM_DA8__EIM_AD08            0xb0b1
 763                         MX6QDL_PAD_EIM_DA7__EIM_AD07            0xb0b1
 764                         MX6QDL_PAD_EIM_DA6__EIM_AD06            0xb0b1
 765                         MX6QDL_PAD_EIM_DA5__EIM_AD05            0xb0b1
 766                         MX6QDL_PAD_EIM_DA4__EIM_AD04            0xb0b1
 767                         MX6QDL_PAD_EIM_DA3__EIM_AD03            0xb0b1
 768                         MX6QDL_PAD_EIM_DA2__EIM_AD02            0xb0b1
 769                         MX6QDL_PAD_EIM_DA1__EIM_AD01            0xb0b1
 770                         MX6QDL_PAD_EIM_DA0__EIM_AD00            0xb0b1
 771                 >;
 772         };
 773
 774         pinctrl_weim_rdnwr: weimrdnwr {
 775                 fsl,pins = <
 776                         MX6QDL_PAD_SD2_CLK__GPIO1_IO10          0x0040
 777                         MX6QDL_PAD_RGMII_TD3__GPIO6_IO23        0x130b0
 778                 >;
 779         };
 780
 781         pinctrl_weim_npwe: weimnpwe {
 782                 fsl,pins = <
 783                         MX6QDL_PAD_SD2_DAT3__GPIO1_IO12         0x0040
 784                         MX6QDL_PAD_RGMII_TD2__GPIO6_IO22        0x130b0
 785                 >;
 786         };
 787
 788         /* ADDRESS[16:18] [25] used as GPIO */
 789         pinctrl_weim_gpio_1: weimgpio-1 {
 790                 fsl,pins = <
 791                         MX6QDL_PAD_KEY_ROW4__GPIO4_IO15         0x1b0b0
 792                         MX6QDL_PAD_KEY_ROW2__GPIO4_IO11         0x1b0b0
 793                         MX6QDL_PAD_KEY_COL2__GPIO4_IO10         0x1b0b0
 794                         MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17      0x1b0b0
 795                         MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16      0x1b0b0
 796                         MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15      0x1b0b0
 797                         MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14      0x1b0b0
 798                         MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13      0x1b0b0
 799                         MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12      0x1b0b0
 800                         MX6QDL_PAD_NANDF_D1__GPIO2_IO01         0x1b0b0
 801                 >;
 802         };
 803
 804         /* ADDRESS[19:24] used as GPIO */
 805         pinctrl_weim_gpio_2: weimgpio-2 {
 806                 fsl,pins = <
 807                         MX6QDL_PAD_KEY_ROW2__GPIO4_IO11         0x1b0b0
 808                         MX6QDL_PAD_KEY_COL2__GPIO4_IO10         0x1b0b0
 809                         MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17      0x1b0b0
 810                         MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16      0x1b0b0
 811                         MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15      0x1b0b0
 812                         MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14      0x1b0b0
 813                         MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13      0x1b0b0
 814                         MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12      0x1b0b0
 815                         MX6QDL_PAD_NANDF_D1__GPIO2_IO01         0x1b0b0
 816                 >;
 817         };
 818
 819         /* DATA[16:31] used as GPIO */
 820         pinctrl_weim_gpio_3: weimgpio-3 {
 821                 fsl,pins = <
 822                         MX6QDL_PAD_EIM_LBA__GPIO2_IO27          0x1b0b0
 823                         MX6QDL_PAD_EIM_BCLK__GPIO6_IO31         0x1b0b0
 824                         MX6QDL_PAD_NANDF_CS3__GPIO6_IO16        0x1b0b0
 825                         MX6QDL_PAD_NANDF_CS1__GPIO6_IO14        0x1b0b0
 826                         MX6QDL_PAD_NANDF_RB0__GPIO6_IO10        0x1b0b0
 827                         MX6QDL_PAD_NANDF_ALE__GPIO6_IO08        0x1b0b0
 828                         MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09       0x1b0b0
 829                         MX6QDL_PAD_NANDF_CS0__GPIO6_IO11        0x1b0b0
 830                         MX6QDL_PAD_NANDF_CLE__GPIO6_IO07        0x1b0b0
 831                         MX6QDL_PAD_GPIO_19__GPIO4_IO05          0x1b0b0
 832                         MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19        0x1b0b0
 833                         MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18      0x1b0b0
 834                         MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x1b0b0
 835                         MX6QDL_PAD_GPIO_5__GPIO1_IO05           0x1b0b0
 836                         MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x1b0b0
 837                 >;
 838         };
 839
 840         /* DQM[0:3] used as GPIO */
 841         pinctrl_weim_gpio_4: weimgpio-4 {
 842                 fsl,pins = <
 843                         MX6QDL_PAD_EIM_EB0__GPIO2_IO28          0x1b0b0
 844                         MX6QDL_PAD_EIM_EB1__GPIO2_IO29          0x1b0b0
 845                         MX6QDL_PAD_SD2_DAT2__GPIO1_IO13         0x1b0b0
 846                         MX6QDL_PAD_NANDF_D0__GPIO2_IO00         0x1b0b0
 847                 >;
 848         };
 849
 850         /* RDY used as GPIO */
 851         pinctrl_weim_gpio_5: weimgpio-5 {
 852                 fsl,pins = <
 853                         MX6QDL_PAD_EIM_WAIT__GPIO5_IO00         0x1b0b0
 854                 >;
 855         };
 856
 857         /* ADDRESS[16] DATA[30] used as GPIO */
 858         pinctrl_weim_gpio_6: weimgpio-6 {
 859                 fsl,pins = <
 860                         MX6QDL_PAD_KEY_ROW4__GPIO4_IO15         0x1b0b0
 861                         MX6QDL_PAD_KEY_COL4__GPIO4_IO14         0x1b0b0
 862                 >;
 863         };
 864 };