arch/arm/boot/dts/imx6q.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Copyright 2013 Freescale Semiconductor, Inc.
   4
   5 #include <dt-bindings/interrupt-controller/irq.h>
   6 #include "imx6q-pinfunc.h"
   7 #include "imx6qdl.dtsi"
   8
   9 / {
  10         aliases {
  11                 ipu1 = &ipu2;
  12                 spi4 = &ecspi5;
  13         };
  14
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu0: cpu@0 {
  20                         compatible = "arm,cortex-a9";
  21                         device_type = "cpu";
  22                         reg = <0>;
  23                         next-level-cache = <&L2>;
  24                         operating-points = <
  25                                 /* kHz    uV */
  26                                 1200000 1275000
  27                                 996000  1250000
  28                                 852000  1250000
  29                                 792000  1175000
  30                                 396000  975000
  31                         >;
  32                         fsl,soc-operating-points = <
  33                                 /* ARM kHz  SOC-PU uV */
  34                                 1200000 1275000
  35                                 996000  1250000
  36                                 852000  1250000
  37                                 792000  1175000
  38                                 396000  1175000
  39                         >;
  40                         clock-latency = <61036>; /* two CLK32 periods */
  41                         #cooling-cells = <2>;
  42                         clocks = <&clks IMX6QDL_CLK_ARM>,
  43                                  <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
  44                                  <&clks IMX6QDL_CLK_STEP>,
  45                                  <&clks IMX6QDL_CLK_PLL1_SW>,
  46                                  <&clks IMX6QDL_CLK_PLL1_SYS>;
  47                         clock-names = "arm", "pll2_pfd2_396m", "step",
  48                                       "pll1_sw", "pll1_sys";
  49                         arm-supply = <&reg_arm>;
  50                         pu-supply = <&reg_pu>;
  51                         soc-supply = <&reg_soc>;
  52                 };
  53
  54                 cpu1: cpu@1 {
  55                         compatible = "arm,cortex-a9";
  56                         device_type = "cpu";
  57                         reg = <1>;
  58                         next-level-cache = <&L2>;
  59                         operating-points = <
  60                                 /* kHz    uV */
  61                                 1200000 1275000
  62                                 996000  1250000
  63                                 852000  1250000
  64                                 792000  1175000
  65                                 396000  975000
  66                         >;
  67                         fsl,soc-operating-points = <
  68                                 /* ARM kHz  SOC-PU uV */
  69                                 1200000 1275000
  70                                 996000  1250000
  71                                 852000  1250000
  72                                 792000  1175000
  73                                 396000  1175000
  74                         >;
  75                         clock-latency = <61036>; /* two CLK32 periods */
  76                         #cooling-cells = <2>;
  77                         clocks = <&clks IMX6QDL_CLK_ARM>,
  78                                  <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
  79                                  <&clks IMX6QDL_CLK_STEP>,
  80                                  <&clks IMX6QDL_CLK_PLL1_SW>,
  81                                  <&clks IMX6QDL_CLK_PLL1_SYS>;
  82                         clock-names = "arm", "pll2_pfd2_396m", "step",
  83                                       "pll1_sw", "pll1_sys";
  84                         arm-supply = <&reg_arm>;
  85                         pu-supply = <&reg_pu>;
  86                         soc-supply = <&reg_soc>;
  87                 };
  88
  89                 cpu2: cpu@2 {
  90                         compatible = "arm,cortex-a9";
  91                         device_type = "cpu";
  92                         reg = <2>;
  93                         next-level-cache = <&L2>;
  94                         operating-points = <
  95                                 /* kHz    uV */
  96                                 1200000 1275000
  97                                 996000  1250000
  98                                 852000  1250000
  99                                 792000  1175000
 100                                 396000  975000
 101                         >;
 102                         fsl,soc-operating-points = <
 103                                 /* ARM kHz  SOC-PU uV */
 104                                 1200000 1275000
 105                                 996000  1250000
 106                                 852000  1250000
 107                                 792000  1175000
 108                                 396000  1175000
 109                         >;
 110                         clock-latency = <61036>; /* two CLK32 periods */
 111                         #cooling-cells = <2>;
 112                         clocks = <&clks IMX6QDL_CLK_ARM>,
 113                                  <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
 114                                  <&clks IMX6QDL_CLK_STEP>,
 115                                  <&clks IMX6QDL_CLK_PLL1_SW>,
 116                                  <&clks IMX6QDL_CLK_PLL1_SYS>;
 117                         clock-names = "arm", "pll2_pfd2_396m", "step",
 118                                       "pll1_sw", "pll1_sys";
 119                         arm-supply = <&reg_arm>;
 120                         pu-supply = <&reg_pu>;
 121                         soc-supply = <&reg_soc>;
 122                 };
 123
 124                 cpu3: cpu@3 {
 125                         compatible = "arm,cortex-a9";
 126                         device_type = "cpu";
 127                         reg = <3>;
 128                         next-level-cache = <&L2>;
 129                         operating-points = <
 130                                 /* kHz    uV */
 131                                 1200000 1275000
 132                                 996000  1250000
 133                                 852000  1250000
 134                                 792000  1175000
 135                                 396000  975000
 136                         >;
 137                         fsl,soc-operating-points = <
 138                                 /* ARM kHz  SOC-PU uV */
 139                                 1200000 1275000
 140                                 996000  1250000
 141                                 852000  1250000
 142                                 792000  1175000
 143                                 396000  1175000
 144                         >;
 145                         clock-latency = <61036>; /* two CLK32 periods */
 146                         #cooling-cells = <2>;
 147                         clocks = <&clks IMX6QDL_CLK_ARM>,
 148                                  <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
 149                                  <&clks IMX6QDL_CLK_STEP>,
 150                                  <&clks IMX6QDL_CLK_PLL1_SW>,
 151                                  <&clks IMX6QDL_CLK_PLL1_SYS>;
 152                         clock-names = "arm", "pll2_pfd2_396m", "step",
 153                                       "pll1_sw", "pll1_sys";
 154                         arm-supply = <&reg_arm>;
 155                         pu-supply = <&reg_pu>;
 156                         soc-supply = <&reg_soc>;
 157                 };
 158         };
 159
 160         soc {
 161                 ocram: sram@900000 {
 162                         compatible = "mmio-sram";
 163                         reg = <0x00900000 0x40000>;
 164                         clocks = <&clks IMX6QDL_CLK_OCRAM>;
 165                 };
 166
 167                 aips-bus@2000000 { /* AIPS1 */
 168                         spba-bus@2000000 {
 169                                 ecspi5: spi@2018000 {
 170                                         #address-cells = <1>;
 171                                         #size-cells = <0>;
 172                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 173                                         reg = <0x02018000 0x4000>;
 174                                         interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
 175                                         clocks = <&clks IMX6Q_CLK_ECSPI5>,
 176                                                  <&clks IMX6Q_CLK_ECSPI5>;
 177                                         clock-names = "ipg", "per";
 178                                         dmas = <&sdma 11 8 1>, <&sdma 12 8 2>;
 179                                         dma-names = "rx", "tx";
 180                                         status = "disabled";
 181                                 };
 182                         };
 183
 184                         iomuxc: iomuxc@20e0000 {
 185                                 compatible = "fsl,imx6q-iomuxc";
 186                         };
 187                 };
 188
 189                 sata: sata@2200000 {
 190                         compatible = "fsl,imx6q-ahci";
 191                         reg = <0x02200000 0x4000>;
 192                         interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
 193                         clocks = <&clks IMX6QDL_CLK_SATA>,
 194                                  <&clks IMX6QDL_CLK_SATA_REF_100M>,
 195                                  <&clks IMX6QDL_CLK_AHB>;
 196                         clock-names = "sata", "sata_ref", "ahb";
 197                         status = "disabled";
 198                 };
 199
 200                 gpu_vg: gpu@2204000 {
 201                         compatible = "vivante,gc";
 202                         reg = <0x02204000 0x4000>;
 203                         interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
 204                         clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>,
 205                                  <&clks IMX6QDL_CLK_GPU2D_CORE>;
 206                         clock-names = "bus", "core";
 207                         power-domains = <&pd_pu>;
 208                         #cooling-cells = <2>;
 209                 };
 210
 211                 ipu2: ipu@2800000 {
 212                         #address-cells = <1>;
 213                         #size-cells = <0>;
 214                         compatible = "fsl,imx6q-ipu";
 215                         reg = <0x02800000 0x400000>;
 216                         interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
 217                                      <0 7 IRQ_TYPE_LEVEL_HIGH>;
 218                         clocks = <&clks IMX6QDL_CLK_IPU2>,
 219                                  <&clks IMX6QDL_CLK_IPU2_DI0>,
 220                                  <&clks IMX6QDL_CLK_IPU2_DI1>;
 221                         clock-names = "bus", "di0", "di1";
 222                         resets = <&src 4>;
 223
 224                         ipu2_csi0: port@0 {
 225                                 reg = <0>;
 226
 227                                 ipu2_csi0_from_mipi_vc2: endpoint {
 228                                         remote-endpoint = <&mipi_vc2_to_ipu2_csi0>;
 229                                 };
 230                         };
 231
 232                         ipu2_csi1: port@1 {
 233                                 reg = <1>;
 234
 235                                 ipu2_csi1_from_ipu2_csi1_mux: endpoint {
 236                                         remote-endpoint = <&ipu2_csi1_mux_to_ipu2_csi1>;
 237                                 };
 238                         };
 239
 240                         ipu2_di0: port@2 {
 241                                 #address-cells = <1>;
 242                                 #size-cells = <0>;
 243                                 reg = <2>;
 244
 245                                 ipu2_di0_disp0: endpoint@0 {
 246                                         reg = <0>;
 247                                 };
 248
 249                                 ipu2_di0_hdmi: endpoint@1 {
 250                                         reg = <1>;
 251                                         remote-endpoint = <&hdmi_mux_2>;
 252                                 };
 253
 254                                 ipu2_di0_mipi: endpoint@2 {
 255                                         reg = <2>;
 256                                         remote-endpoint = <&mipi_mux_2>;
 257                                 };
 258
 259                                 ipu2_di0_lvds0: endpoint@3 {
 260                                         reg = <3>;
 261                                         remote-endpoint = <&lvds0_mux_2>;
 262                                 };
 263
 264                                 ipu2_di0_lvds1: endpoint@4 {
 265                                         reg = <4>;
 266                                         remote-endpoint = <&lvds1_mux_2>;
 267                                 };
 268                         };
 269
 270                         ipu2_di1: port@3 {
 271                                 #address-cells = <1>;
 272                                 #size-cells = <0>;
 273                                 reg = <3>;
 274
 275                                 ipu2_di1_hdmi: endpoint@1 {
 276                                         reg = <1>;
 277                                         remote-endpoint = <&hdmi_mux_3>;
 278                                 };
 279
 280                                 ipu2_di1_mipi: endpoint@2 {
 281                                         reg = <2>;
 282                                         remote-endpoint = <&mipi_mux_3>;
 283                                 };
 284
 285                                 ipu2_di1_lvds0: endpoint@3 {
 286                                         reg = <3>;
 287                                         remote-endpoint = <&lvds0_mux_3>;
 288                                 };
 289
 290                                 ipu2_di1_lvds1: endpoint@4 {
 291                                         reg = <4>;
 292                                         remote-endpoint = <&lvds1_mux_3>;
 293                                 };
 294                         };
 295                 };
 296         };
 297
 298         capture-subsystem {
 299                 compatible = "fsl,imx-capture-subsystem";
 300                 ports = <&ipu1_csi0>, <&ipu1_csi1>, <&ipu2_csi0>, <&ipu2_csi1>;
 301         };
 302
 303         display-subsystem {
 304                 compatible = "fsl,imx-display-subsystem";
 305                 ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
 306         };
 307 };
 308
 309 &gpio1 {
 310         gpio-ranges = <&iomuxc  0 136  2>, <&iomuxc  2 141 1>, <&iomuxc  3 139 1>,
 311                       <&iomuxc  4 142  2>, <&iomuxc  6 140 1>, <&iomuxc  7 144 2>,
 312                       <&iomuxc  9 138  1>, <&iomuxc 10 213 3>, <&iomuxc 13  20 1>,
 313                       <&iomuxc 14  19  1>, <&iomuxc 15  21 1>, <&iomuxc 16 208 1>,
 314                       <&iomuxc 17 207  1>, <&iomuxc 18 210 3>, <&iomuxc 21 209 1>,
 315                       <&iomuxc 22 116 10>;
 316 };
 317
 318 &gpio2 {
 319         gpio-ranges = <&iomuxc  0 191 16>, <&iomuxc 16 55 14>, <&iomuxc 30 35 1>,
 320                       <&iomuxc 31  44  1>;
 321 };
 322
 323 &gpio3 {
 324         gpio-ranges = <&iomuxc 0 69 16>, <&iomuxc 16 36 8>, <&iomuxc 24 45 8>;
 325 };
 326
 327 &gpio4 {
 328         gpio-ranges = <&iomuxc 5 149 1>, <&iomuxc 6 126 10>, <&iomuxc 16 87 16>;
 329 };
 330
 331 &gpio5 {
 332         gpio-ranges = <&iomuxc 0  85  1>, <&iomuxc  2  34  1>, <&iomuxc 4 53 1>,
 333                       <&iomuxc 5 103 13>, <&iomuxc 18 150 14>;
 334 };
 335
 336 &gpio6 {
 337         gpio-ranges = <&iomuxc  0 164 6>, <&iomuxc  6  54 1>, <&iomuxc  7 181  5>,
 338                       <&iomuxc 14 186 3>, <&iomuxc 17 170 2>, <&iomuxc 19  22 12>,
 339                       <&iomuxc 31  86 1>;
 340 };
 341
 342 &gpio7 {
 343         gpio-ranges = <&iomuxc 0 172 9>, <&iomuxc 9 189 2>, <&iomuxc 11 146 3>;
 344 };
 345
 346 &gpr {
 347         ipu1_csi0_mux {
 348                 compatible = "video-mux";
 349                 mux-controls = <&mux 0>;
 350                 #address-cells = <1>;
 351                 #size-cells = <0>;
 352
 353                 port@0 {
 354                         reg = <0>;
 355
 356                         ipu1_csi0_mux_from_mipi_vc0: endpoint {
 357                                 remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
 358                         };
 359                 };
 360
 361                 port@1 {
 362                         reg = <1>;
 363
 364                         ipu1_csi0_mux_from_parallel_sensor: endpoint {
 365                         };
 366                 };
 367
 368                 port@2 {
 369                         reg = <2>;
 370
 371                         ipu1_csi0_mux_to_ipu1_csi0: endpoint {
 372                                 remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
 373                         };
 374                 };
 375         };
 376
 377         ipu2_csi1_mux {
 378                 compatible = "video-mux";
 379                 mux-controls = <&mux 1>;
 380                 #address-cells = <1>;
 381                 #size-cells = <0>;
 382
 383                 port@0 {
 384                         reg = <0>;
 385
 386                         ipu2_csi1_mux_from_mipi_vc3: endpoint {
 387                                 remote-endpoint = <&mipi_vc3_to_ipu2_csi1_mux>;
 388                         };
 389                 };
 390
 391                 port@1 {
 392                         reg = <1>;
 393
 394                         ipu2_csi1_mux_from_parallel_sensor: endpoint {
 395                         };
 396                 };
 397
 398                 port@2 {
 399                         reg = <2>;
 400
 401                         ipu2_csi1_mux_to_ipu2_csi1: endpoint {
 402                                 remote-endpoint = <&ipu2_csi1_from_ipu2_csi1_mux>;
 403                         };
 404                 };
 405         };
 406 };
 407
 408 &hdmi {
 409         compatible = "fsl,imx6q-hdmi";
 410
 411         port@2 {
 412                 reg = <2>;
 413
 414                 hdmi_mux_2: endpoint {
 415                         remote-endpoint = <&ipu2_di0_hdmi>;
 416                 };
 417         };
 418
 419         port@3 {
 420                 reg = <3>;
 421
 422                 hdmi_mux_3: endpoint {
 423                         remote-endpoint = <&ipu2_di1_hdmi>;
 424                 };
 425         };
 426 };
 427
 428 &ipu1_csi1 {
 429         ipu1_csi1_from_mipi_vc1: endpoint {
 430                 remote-endpoint = <&mipi_vc1_to_ipu1_csi1>;
 431         };
 432 };
 433
 434 &ldb {
 435         clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
 436                  <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
 437                  <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
 438                  <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
 439         clock-names = "di0_pll", "di1_pll",
 440                       "di0_sel", "di1_sel", "di2_sel", "di3_sel",
 441                       "di0", "di1";
 442
 443         lvds-channel@0 {
 444                 port@2 {
 445                         reg = <2>;
 446
 447                         lvds0_mux_2: endpoint {
 448                                 remote-endpoint = <&ipu2_di0_lvds0>;
 449                         };
 450                 };
 451
 452                 port@3 {
 453                         reg = <3>;
 454
 455                         lvds0_mux_3: endpoint {
 456                                 remote-endpoint = <&ipu2_di1_lvds0>;
 457                         };
 458                 };
 459         };
 460
 461         lvds-channel@1 {
 462                 port@2 {
 463                         reg = <2>;
 464
 465                         lvds1_mux_2: endpoint {
 466                                 remote-endpoint = <&ipu2_di0_lvds1>;
 467                         };
 468                 };
 469
 470                 port@3 {
 471                         reg = <3>;
 472
 473                         lvds1_mux_3: endpoint {
 474                                 remote-endpoint = <&ipu2_di1_lvds1>;
 475                         };
 476                 };
 477         };
 478 };
 479
 480 &mipi_csi {
 481         port@1 {
 482                 reg = <1>;
 483
 484                 mipi_vc0_to_ipu1_csi0_mux: endpoint {
 485                         remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
 486                 };
 487         };
 488
 489         port@2 {
 490                 reg = <2>;
 491
 492                 mipi_vc1_to_ipu1_csi1: endpoint {
 493                         remote-endpoint = <&ipu1_csi1_from_mipi_vc1>;
 494                 };
 495         };
 496
 497         port@3 {
 498                 reg = <3>;
 499
 500                 mipi_vc2_to_ipu2_csi0: endpoint {
 501                         remote-endpoint = <&ipu2_csi0_from_mipi_vc2>;
 502                 };
 503         };
 504
 505         port@4 {
 506                 reg = <4>;
 507
 508                 mipi_vc3_to_ipu2_csi1_mux: endpoint {
 509                         remote-endpoint = <&ipu2_csi1_mux_from_mipi_vc3>;
 510                 };
 511         };
 512 };
 513
 514 &mipi_dsi {
 515         ports {
 516                 port@2 {
 517                         reg = <2>;
 518
 519                         mipi_mux_2: endpoint {
 520                                 remote-endpoint = <&ipu2_di0_mipi>;
 521                         };
 522                 };
 523
 524                 port@3 {
 525                         reg = <3>;
 526
 527                         mipi_mux_3: endpoint {
 528                                 remote-endpoint = <&ipu2_di1_mipi>;
 529                         };
 530                 };
 531         };
 532 };
 533
 534 &mux {
 535         mux-reg-masks = <0x04 0x00080000>, /* MIPI_IPU1_MUX */
 536                         <0x04 0x00100000>, /* MIPI_IPU2_MUX */
 537                         <0x0c 0x0000000c>, /* HDMI_MUX_CTL */
 538                         <0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
 539                         <0x0c 0x00000300>, /* LVDS1_MUX_CTL */
 540                         <0x28 0x00000003>, /* DCIC1_MUX_CTL */
 541                         <0x28 0x0000000c>; /* DCIC2_MUX_CTL */
 542 };
 543
 544 &vpu {
 545         compatible = "fsl,imx6q-vpu", "cnm,coda960";
 546 };