arch/arm/boot/dts/imx6q-tbs2910.dts

   1 /*
   2  * Copyright 2014 Soeren Moch <smoch@web.de>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of
  12  *     the License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  *     You should have received a copy of the GNU General Public
  20  *     License along with this file; if not, write to the Free
  21  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  22  *     MA 02110-1301 USA
  23  *
  24  * Or, alternatively,
  25  *
  26  *  b) Permission is hereby granted, free of charge, to any person
  27  *     obtaining a copy of this software and associated documentation
  28  *     files (the "Software"), to deal in the Software without
  29  *     restriction, including without limitation the rights to use,
  30  *     copy, modify, merge, publish, distribute, sublicense, and/or
  31  *     sell copies of the Software, and to permit persons to whom the
  32  *     Software is furnished to do so, subject to the following
  33  *     conditions:
  34  *
  35  *     The above copyright notice and this permission notice shall be
  36  *     included in all copies or substantial portions of the Software.
  37  *
  38  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  39  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  40  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  41  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  42  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  43  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  44  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  45  *     OTHER DEALINGS IN THE SOFTWARE.
  46  */
  47
  48 /dts-v1/;
  49
  50 #include "imx6q.dtsi"
  51 #include <dt-bindings/gpio/gpio.h>
  52 #include <dt-bindings/input/input.h>
  53
  54 / {
  55         model = "TBS2910 Matrix ARM mini PC";
  56         compatible = "tbs,imx6q-tbs2910", "fsl,imx6q";
  57
  58         chosen {
  59                 stdout-path = &uart1;
  60         };
  61
  62         memory@10000000 {
  63                 device_type = "memory";
  64                 reg = <0x10000000 0x80000000>;
  65         };
  66
  67         fan {
  68                 compatible = "gpio-fan";
  69                 pinctrl-names = "default";
  70                 pinctrl-0 = <&pinctrl_gpio_fan>;
  71                 gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>;
  72                 gpio-fan,speed-map = <0    0
  73                                       3000 1>;
  74         };
  75
  76         ir_recv {
  77                 compatible = "gpio-ir-receiver";
  78                 gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;
  79                 pinctrl-names = "default";
  80                 pinctrl-0 = <&pinctrl_ir>;
  81         };
  82
  83         leds {
  84                 compatible = "gpio-leds";
  85                 pinctrl-names = "default";
  86                 pinctrl-0 = <&pinctrl_gpio_leds>;
  87
  88                 blue {
  89                         label = "blue_status_led";
  90                         gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
  91                         default-state = "keep";
  92                 };
  93         };
  94
  95         reg_2p5v: regulator-2p5v {
  96                 compatible = "regulator-fixed";
  97                 regulator-name = "2P5V";
  98                 regulator-min-microvolt = <2500000>;
  99                 regulator-max-microvolt = <2500000>;
 100         };
 101
 102         reg_3p3v: regulator-3p3v {
 103                 compatible = "regulator-fixed";
 104                 regulator-name = "3P3V";
 105                 regulator-min-microvolt = <3300000>;
 106                 regulator-max-microvolt = <3300000>;
 107         };
 108
 109         reg_5p0v: regulator-5p0v {
 110                 compatible = "regulator-fixed";
 111                 regulator-name = "5P0V";
 112                 regulator-min-microvolt = <5000000>;
 113                 regulator-max-microvolt = <5000000>;
 114         };
 115
 116         sound-sgtl5000 {
 117                 audio-codec = <&sgtl5000>;
 118                 audio-routing =
 119                         "MIC_IN", "Mic Jack",
 120                         "Mic Jack", "Mic Bias",
 121                         "Headphone Jack", "HP_OUT";
 122                 compatible = "fsl,imx-audio-sgtl5000";
 123                 model = "On-board Codec";
 124                 mux-ext-port = <3>;
 125                 mux-int-port = <1>;
 126                 ssi-controller = <&ssi1>;
 127         };
 128
 129         sound-spdif {
 130                 compatible = "fsl,imx-audio-spdif";
 131                 model = "On-board SPDIF";
 132                 spdif-controller = <&spdif>;
 133                 spdif-out;
 134         };
 135 };
 136
 137 &audmux {
 138         status = "okay";
 139 };
 140
 141 &fec {
 142         pinctrl-names = "default";
 143         pinctrl-0 = <&pinctrl_enet>;
 144         phy-mode = "rgmii";
 145         phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
 146         status = "okay";
 147 };
 148
 149 &hdmi {
 150         pinctrl-names = "default";
 151         pinctrl-0 = <&pinctrl_hdmi>;
 152         ddc-i2c-bus = <&i2c2>;
 153         status = "okay";
 154 };
 155
 156 &i2c1 {
 157         clock-frequency = <100000>;
 158         pinctrl-names = "default";
 159         pinctrl-0 = <&pinctrl_i2c1>;
 160         status = "okay";
 161
 162         sgtl5000: sgtl5000@a {
 163                 clocks = <&clks IMX6QDL_CLK_CKO>;
 164                 compatible = "fsl,sgtl5000";
 165                 pinctrl-names = "default";
 166                 pinctrl-0 = <&pinctrl_sgtl5000>;
 167                 reg = <0x0a>;
 168                 VDDA-supply = <&reg_2p5v>;
 169                 VDDIO-supply = <&reg_3p3v>;
 170         };
 171 };
 172
 173 &i2c2 {
 174         clock-frequency = <100000>;
 175         pinctrl-names = "default";
 176         pinctrl-0 = <&pinctrl_i2c2>;
 177         status = "okay";
 178 };
 179
 180 &i2c3 {
 181         clock-frequency = <100000>;
 182         pinctrl-names = "default";
 183         pinctrl-0 = <&pinctrl_i2c3>;
 184         status = "okay";
 185
 186         rtc: ds1307@68 {
 187                 compatible = "dallas,ds1307";
 188                 reg = <0x68>;
 189         };
 190 };
 191
 192 &pcie {
 193         pinctrl-names = "default";
 194         pinctrl-0 = <&pinctrl_pcie>;
 195         reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
 196         status = "okay";
 197 };
 198
 199 &sata {
 200         fsl,transmit-level-mV = <1104>;
 201         fsl,transmit-boost-mdB = <3330>;
 202         fsl,transmit-atten-16ths = <16>;
 203         fsl,receive-eq-mdB = <3000>;
 204         status = "okay";
 205 };
 206
 207 &snvs_poweroff {
 208         status = "okay";
 209 };
 210
 211 &spdif {
 212         pinctrl-names = "default";
 213         pinctrl-0 = <&pinctrl_spdif>;
 214         status = "okay";
 215 };
 216
 217 &ssi1 {
 218         status = "okay";
 219 };
 220
 221 &uart1 {
 222         pinctrl-names = "default";
 223         pinctrl-0 = <&pinctrl_uart1>;
 224         status = "okay";
 225 };
 226
 227 &uart2 {
 228         pinctrl-names = "default";
 229         pinctrl-0 = <&pinctrl_uart2>;
 230         status = "okay";
 231 };
 232
 233 &usbh1 {
 234         vbus-supply = <&reg_5p0v>;
 235         status = "okay";
 236 };
 237
 238 &usbotg {
 239         vbus-supply = <&reg_5p0v>;
 240         pinctrl-names = "default";
 241         pinctrl-0 = <&pinctrl_usbotg>;
 242         disable-over-current;
 243         status = "okay";
 244 };
 245
 246 &usdhc2 {
 247         pinctrl-names = "default";
 248         pinctrl-0 = <&pinctrl_usdhc2>;
 249         bus-width = <4>;
 250         cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
 251         vmmc-supply = <&reg_3p3v>;
 252         vqmmc-supply = <&reg_3p3v>;
 253         voltage-ranges = <3300 3300>;
 254         no-1-8-v;
 255         status = "okay";
 256 };
 257
 258 &usdhc3 {
 259         pinctrl-names = "default";
 260         pinctrl-0 = <&pinctrl_usdhc3>;
 261         bus-width = <4>;
 262         cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
 263         wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
 264         vmmc-supply = <&reg_3p3v>;
 265         vqmmc-supply = <&reg_3p3v>;
 266         voltage-ranges = <3300 3300>;
 267         no-1-8-v;
 268         status = "okay";
 269 };
 270
 271 &usdhc4 {
 272         pinctrl-names = "default";
 273         pinctrl-0 = <&pinctrl_usdhc4>;
 274         bus-width = <8>;
 275         vmmc-supply = <&reg_3p3v>;
 276         vqmmc-supply = <&reg_3p3v>;
 277         voltage-ranges = <3300 3300>;
 278         non-removable;
 279         no-1-8-v;
 280         status = "okay";
 281 };
 282
 283 &iomuxc {
 284         pinctrl_enet: enetgrp {
 285                 fsl,pins = <
 286                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
 287                         MX6QDL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
 288                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x1b030
 289                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x1b030
 290                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x1b030
 291                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x1b030
 292                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x1b030
 293                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
 294                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
 295                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b030
 296                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b030
 297                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b030
 298                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b030
 299                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b030
 300                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
 301                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK      0x4001b0a8
 302                         MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25    0x1b059
 303                 >;
 304         };
 305
 306         pinctrl_gpio_fan: gpiofangrp {
 307                 fsl,pins = <
 308                         MX6QDL_PAD_EIM_D28__GPIO3_IO28        0x130b1
 309                 >;
 310         };
 311
 312         pinctrl_gpio_leds: gpioledsgrp {
 313                 fsl,pins = <
 314                         MX6QDL_PAD_GPIO_2__GPIO1_IO02         0x130b1
 315                 >;
 316         };
 317
 318         pinctrl_hdmi: hdmigrp {
 319                 fsl,pins = <
 320                         MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
 321                 >;
 322         };
 323
 324         pinctrl_i2c1: i2c1grp {
 325                 fsl,pins = <
 326                         MX6QDL_PAD_CSI0_DAT9__I2C1_SCL        0x4001b8b1
 327                         MX6QDL_PAD_CSI0_DAT8__I2C1_SDA        0x4001b8b1
 328                 >;
 329         };
 330
 331         pinctrl_i2c2: i2c2grp {
 332                 fsl,pins = <
 333                         MX6QDL_PAD_KEY_COL3__I2C2_SCL         0x4001b8b1
 334                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA         0x4001b8b1
 335                 >;
 336         };
 337
 338         pinctrl_i2c3: i2c3grp {
 339                 fsl,pins = <
 340                         MX6QDL_PAD_GPIO_3__I2C3_SCL           0x4001b8b1
 341                         MX6QDL_PAD_GPIO_6__I2C3_SDA           0x4001b8b1
 342                 >;
 343         };
 344
 345         pinctrl_ir: irgrp {
 346                 fsl,pins = <
 347                         MX6QDL_PAD_EIM_D18__GPIO3_IO18        0x17059
 348                 >;
 349         };
 350
 351         pinctrl_pcie: pciegrp {
 352                 fsl,pins = <
 353                         MX6QDL_PAD_GPIO_17__GPIO7_IO12        0x17059
 354                 >;
 355         };
 356
 357         pinctrl_sgtl5000: sgtl5000grp {
 358                 fsl,pins = <
 359                         MX6QDL_PAD_CSI0_DAT7__AUD3_RXD        0x130b0
 360                         MX6QDL_PAD_CSI0_DAT4__AUD3_TXC        0x130b0
 361                         MX6QDL_PAD_CSI0_DAT5__AUD3_TXD        0x110b0
 362                         MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS       0x130b0
 363                         MX6QDL_PAD_GPIO_0__CCM_CLKO1          0x130b0
 364                 >;
 365         };
 366
 367         pinctrl_spdif: spdifgrp {
 368                 fsl,pins = <MX6QDL_PAD_GPIO_19__SPDIF_OUT     0x13091
 369                 >;
 370         };
 371
 372         pinctrl_uart1: uart1grp {
 373                 fsl,pins = <
 374                         MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA  0x1b0b1
 375                         MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA  0x1b0b1
 376                 >;
 377         };
 378
 379         pinctrl_uart2: uart2grp {
 380                 fsl,pins = <
 381                         MX6QDL_PAD_EIM_D26__UART2_TX_DATA     0x1b0b1
 382                         MX6QDL_PAD_EIM_D27__UART2_RX_DATA     0x1b0b1
 383                 >;
 384         };
 385
 386         pinctrl_usbotg: usbotggrp {
 387                 fsl,pins = <
 388                         MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID     0x17059
 389                 >;
 390         };
 391
 392         pinctrl_usdhc2: usdhc2grp {
 393                 fsl,pins = <
 394                         MX6QDL_PAD_SD2_CMD__SD2_CMD           0x17059
 395                         MX6QDL_PAD_SD2_CLK__SD2_CLK           0x10059
 396                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0        0x17059
 397                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1        0x17059
 398                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2        0x17059
 399                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3        0x17059
 400                         MX6QDL_PAD_NANDF_D2__GPIO2_IO02       0x17059
 401                 >;
 402         };
 403
 404         pinctrl_usdhc3: usdhc3grp {
 405                 fsl,pins = <
 406                         MX6QDL_PAD_SD3_CMD__SD3_CMD           0x17059
 407                         MX6QDL_PAD_SD3_CLK__SD3_CLK           0x10059
 408                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0        0x17059
 409                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1        0x17059
 410                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2        0x17059
 411                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3        0x17059
 412                         MX6QDL_PAD_NANDF_D0__GPIO2_IO00       0x17059
 413                         MX6QDL_PAD_NANDF_D1__GPIO2_IO01       0x17059
 414                 >;
 415         };
 416
 417         pinctrl_usdhc4: usdhc4grp {
 418                 fsl,pins = <
 419                         MX6QDL_PAD_SD4_CMD__SD4_CMD           0x17059
 420                         MX6QDL_PAD_SD4_CLK__SD4_CLK           0x10059
 421                         MX6QDL_PAD_SD4_DAT0__SD4_DATA0        0x17059
 422                         MX6QDL_PAD_SD4_DAT1__SD4_DATA1        0x17059
 423                         MX6QDL_PAD_SD4_DAT2__SD4_DATA2        0x17059
 424                         MX6QDL_PAD_SD4_DAT3__SD4_DATA3        0x17059
 425                         MX6QDL_PAD_SD4_DAT4__SD4_DATA4        0x17059
 426                         MX6QDL_PAD_SD4_DAT5__SD4_DATA5        0x17059
 427                         MX6QDL_PAD_SD4_DAT6__SD4_DATA6        0x17059
 428                         MX6QDL_PAD_SD4_DAT7__SD4_DATA7        0x17059
 429                 >;
 430         };
 431 };