arch/arm/boot/dts/imx51.dtsi

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include "imx51-pinfunc.h"
  14 #include <dt-bindings/clock/imx5-clock.h>
  15 #include <dt-bindings/gpio/gpio.h>
  16 #include <dt-bindings/input/input.h>
  17 #include <dt-bindings/interrupt-controller/irq.h>
  18
  19 / {
  20         #address-cells = <1>;
  21         #size-cells = <1>;
  22
  23         aliases {
  24                 ethernet0 = &fec;
  25                 gpio0 = &gpio1;
  26                 gpio1 = &gpio2;
  27                 gpio2 = &gpio3;
  28                 gpio3 = &gpio4;
  29                 i2c0 = &i2c1;
  30                 i2c1 = &i2c2;
  31                 mmc0 = &esdhc1;
  32                 mmc1 = &esdhc2;
  33                 mmc2 = &esdhc3;
  34                 mmc3 = &esdhc4;
  35                 serial0 = &uart1;
  36                 serial1 = &uart2;
  37                 serial2 = &uart3;
  38                 spi0 = &ecspi1;
  39                 spi1 = &ecspi2;
  40                 spi2 = &cspi;
  41         };
  42
  43         tzic: tz-interrupt-controller@e0000000 {
  44                 compatible = "fsl,imx51-tzic", "fsl,tzic";
  45                 interrupt-controller;
  46                 #interrupt-cells = <1>;
  47                 reg = <0xe0000000 0x4000>;
  48         };
  49
  50         clocks {
  51                 #address-cells = <1>;
  52                 #size-cells = <0>;
  53
  54                 ckil {
  55                         compatible = "fsl,imx-ckil", "fixed-clock";
  56                         #clock-cells = <0>;
  57                         clock-frequency = <32768>;
  58                 };
  59
  60                 ckih1 {
  61                         compatible = "fsl,imx-ckih1", "fixed-clock";
  62                         #clock-cells = <0>;
  63                         clock-frequency = <0>;
  64                 };
  65
  66                 ckih2 {
  67                         compatible = "fsl,imx-ckih2", "fixed-clock";
  68                         #clock-cells = <0>;
  69                         clock-frequency = <0>;
  70                 };
  71
  72                 osc {
  73                         compatible = "fsl,imx-osc", "fixed-clock";
  74                         #clock-cells = <0>;
  75                         clock-frequency = <24000000>;
  76                 };
  77         };
  78
  79         cpus {
  80                 #address-cells = <1>;
  81                 #size-cells = <0>;
  82                 cpu: cpu@0 {
  83                         device_type = "cpu";
  84                         compatible = "arm,cortex-a8";
  85                         reg = <0>;
  86                         clock-latency = <62500>;
  87                         clocks = <&clks IMX5_CLK_CPU_PODF>;
  88                         clock-names = "cpu";
  89                         operating-points = <
  90                                 166000  1000000
  91                                 600000  1050000
  92                                 800000  1100000
  93                         >;
  94                         voltage-tolerance = <5>;
  95                 };
  96         };
  97
  98         usbphy {
  99                 #address-cells = <1>;
 100                 #size-cells = <0>;
 101                 compatible = "simple-bus";
 102
 103                 usbphy0: usbphy@0 {
 104                         compatible = "usb-nop-xceiv";
 105                         reg = <0>;
 106                         clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
 107                         clock-names = "main_clk";
 108                 };
 109         };
 110
 111         display-subsystem {
 112                 compatible = "fsl,imx-display-subsystem";
 113                 ports = <&ipu_di0>, <&ipu_di1>;
 114         };
 115
 116         soc {
 117                 #address-cells = <1>;
 118                 #size-cells = <1>;
 119                 compatible = "simple-bus";
 120                 interrupt-parent = <&tzic>;
 121                 ranges;
 122
 123                 iram: iram@1ffe0000 {
 124                         compatible = "mmio-sram";
 125                         reg = <0x1ffe0000 0x20000>;
 126                 };
 127
 128                 ipu: ipu@40000000 {
 129                         #address-cells = <1>;
 130                         #size-cells = <0>;
 131                         compatible = "fsl,imx51-ipu";
 132                         reg = <0x40000000 0x20000000>;
 133                         interrupts = <11 10>;
 134                         clocks = <&clks IMX5_CLK_IPU_GATE>,
 135                                  <&clks IMX5_CLK_IPU_DI0_GATE>,
 136                                  <&clks IMX5_CLK_IPU_DI1_GATE>;
 137                         clock-names = "bus", "di0", "di1";
 138                         resets = <&src 2>;
 139
 140                         ipu_di0: port@2 {
 141                                 reg = <2>;
 142
 143                                 ipu_di0_disp0: endpoint {
 144                                 };
 145                         };
 146
 147                         ipu_di1: port@3 {
 148                                 reg = <3>;
 149
 150                                 ipu_di1_disp1: endpoint {
 151                                 };
 152                         };
 153                 };
 154
 155                 aips@70000000 { /* AIPS1 */
 156                         compatible = "fsl,aips-bus", "simple-bus";
 157                         #address-cells = <1>;
 158                         #size-cells = <1>;
 159                         reg = <0x70000000 0x10000000>;
 160                         ranges;
 161
 162                         spba@70000000 {
 163                                 compatible = "fsl,spba-bus", "simple-bus";
 164                                 #address-cells = <1>;
 165                                 #size-cells = <1>;
 166                                 reg = <0x70000000 0x40000>;
 167                                 ranges;
 168
 169                                 esdhc1: esdhc@70004000 {
 170                                         compatible = "fsl,imx51-esdhc";
 171                                         reg = <0x70004000 0x4000>;
 172                                         interrupts = <1>;
 173                                         clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
 174                                                  <&clks IMX5_CLK_DUMMY>,
 175                                                  <&clks IMX5_CLK_ESDHC1_PER_GATE>;
 176                                         clock-names = "ipg", "ahb", "per";
 177                                         status = "disabled";
 178                                 };
 179
 180                                 esdhc2: esdhc@70008000 {
 181                                         compatible = "fsl,imx51-esdhc";
 182                                         reg = <0x70008000 0x4000>;
 183                                         interrupts = <2>;
 184                                         clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
 185                                                  <&clks IMX5_CLK_DUMMY>,
 186                                                  <&clks IMX5_CLK_ESDHC2_PER_GATE>;
 187                                         clock-names = "ipg", "ahb", "per";
 188                                         bus-width = <4>;
 189                                         status = "disabled";
 190                                 };
 191
 192                                 uart3: serial@7000c000 {
 193                                         compatible = "fsl,imx51-uart", "fsl,imx21-uart";
 194                                         reg = <0x7000c000 0x4000>;
 195                                         interrupts = <33>;
 196                                         clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
 197                                                  <&clks IMX5_CLK_UART3_PER_GATE>;
 198                                         clock-names = "ipg", "per";
 199                                         status = "disabled";
 200                                 };
 201
 202                                 ecspi1: ecspi@70010000 {
 203                                         #address-cells = <1>;
 204                                         #size-cells = <0>;
 205                                         compatible = "fsl,imx51-ecspi";
 206                                         reg = <0x70010000 0x4000>;
 207                                         interrupts = <36>;
 208                                         clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
 209                                                  <&clks IMX5_CLK_ECSPI1_PER_GATE>;
 210                                         clock-names = "ipg", "per";
 211                                         status = "disabled";
 212                                 };
 213
 214                                 ssi2: ssi@70014000 {
 215                                         #sound-dai-cells = <0>;
 216                                         compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
 217                                         reg = <0x70014000 0x4000>;
 218                                         interrupts = <30>;
 219                                         clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
 220                                                  <&clks IMX5_CLK_SSI2_ROOT_GATE>;
 221                                         clock-names = "ipg", "baud";
 222                                         dmas = <&sdma 24 1 0>,
 223                                                <&sdma 25 1 0>;
 224                                         dma-names = "rx", "tx";
 225                                         fsl,fifo-depth = <15>;
 226                                         status = "disabled";
 227                                 };
 228
 229                                 esdhc3: esdhc@70020000 {
 230                                         compatible = "fsl,imx51-esdhc";
 231                                         reg = <0x70020000 0x4000>;
 232                                         interrupts = <3>;
 233                                         clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
 234                                                  <&clks IMX5_CLK_DUMMY>,
 235                                                  <&clks IMX5_CLK_ESDHC3_PER_GATE>;
 236                                         clock-names = "ipg", "ahb", "per";
 237                                         bus-width = <4>;
 238                                         status = "disabled";
 239                                 };
 240
 241                                 esdhc4: esdhc@70024000 {
 242                                         compatible = "fsl,imx51-esdhc";
 243                                         reg = <0x70024000 0x4000>;
 244                                         interrupts = <4>;
 245                                         clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
 246                                                  <&clks IMX5_CLK_DUMMY>,
 247                                                  <&clks IMX5_CLK_ESDHC4_PER_GATE>;
 248                                         clock-names = "ipg", "ahb", "per";
 249                                         bus-width = <4>;
 250                                         status = "disabled";
 251                                 };
 252                         };
 253
 254                         usbotg: usb@73f80000 {
 255                                 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
 256                                 reg = <0x73f80000 0x0200>;
 257                                 interrupts = <18>;
 258                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
 259                                 fsl,usbmisc = <&usbmisc 0>;
 260                                 fsl,usbphy = <&usbphy0>;
 261                                 status = "disabled";
 262                         };
 263
 264                         usbh1: usb@73f80200 {
 265                                 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
 266                                 reg = <0x73f80200 0x0200>;
 267                                 interrupts = <14>;
 268                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
 269                                 fsl,usbmisc = <&usbmisc 1>;
 270                                 dr_mode = "host";
 271                                 status = "disabled";
 272                         };
 273
 274                         usbh2: usb@73f80400 {
 275                                 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
 276                                 reg = <0x73f80400 0x0200>;
 277                                 interrupts = <16>;
 278                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
 279                                 fsl,usbmisc = <&usbmisc 2>;
 280                                 dr_mode = "host";
 281                                 status = "disabled";
 282                         };
 283
 284                         usbh3: usb@73f80600 {
 285                                 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
 286                                 reg = <0x73f80600 0x0200>;
 287                                 interrupts = <17>;
 288                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
 289                                 fsl,usbmisc = <&usbmisc 3>;
 290                                 dr_mode = "host";
 291                                 status = "disabled";
 292                         };
 293
 294                         usbmisc: usbmisc@73f80800 {
 295                                 #index-cells = <1>;
 296                                 compatible = "fsl,imx51-usbmisc";
 297                                 reg = <0x73f80800 0x200>;
 298                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
 299                         };
 300
 301                         gpio1: gpio@73f84000 {
 302                                 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
 303                                 reg = <0x73f84000 0x4000>;
 304                                 interrupts = <50 51>;
 305                                 gpio-controller;
 306                                 #gpio-cells = <2>;
 307                                 interrupt-controller;
 308                                 #interrupt-cells = <2>;
 309                         };
 310
 311                         gpio2: gpio@73f88000 {
 312                                 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
 313                                 reg = <0x73f88000 0x4000>;
 314                                 interrupts = <52 53>;
 315                                 gpio-controller;
 316                                 #gpio-cells = <2>;
 317                                 interrupt-controller;
 318                                 #interrupt-cells = <2>;
 319                         };
 320
 321                         gpio3: gpio@73f8c000 {
 322                                 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
 323                                 reg = <0x73f8c000 0x4000>;
 324                                 interrupts = <54 55>;
 325                                 gpio-controller;
 326                                 #gpio-cells = <2>;
 327                                 interrupt-controller;
 328                                 #interrupt-cells = <2>;
 329                         };
 330
 331                         gpio4: gpio@73f90000 {
 332                                 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
 333                                 reg = <0x73f90000 0x4000>;
 334                                 interrupts = <56 57>;
 335                                 gpio-controller;
 336                                 #gpio-cells = <2>;
 337                                 interrupt-controller;
 338                                 #interrupt-cells = <2>;
 339                         };
 340
 341                         kpp: kpp@73f94000 {
 342                                 compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
 343                                 reg = <0x73f94000 0x4000>;
 344                                 interrupts = <60>;
 345                                 clocks = <&clks IMX5_CLK_DUMMY>;
 346                                 status = "disabled";
 347                         };
 348
 349                         wdog1: wdog@73f98000 {
 350                                 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
 351                                 reg = <0x73f98000 0x4000>;
 352                                 interrupts = <58>;
 353                                 clocks = <&clks IMX5_CLK_DUMMY>;
 354                         };
 355
 356                         wdog2: wdog@73f9c000 {
 357                                 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
 358                                 reg = <0x73f9c000 0x4000>;
 359                                 interrupts = <59>;
 360                                 clocks = <&clks IMX5_CLK_DUMMY>;
 361                                 status = "disabled";
 362                         };
 363
 364                         gpt: timer@73fa0000 {
 365                                 compatible = "fsl,imx51-gpt", "fsl,imx31-gpt";
 366                                 reg = <0x73fa0000 0x4000>;
 367                                 interrupts = <39>;
 368                                 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
 369                                          <&clks IMX5_CLK_GPT_HF_GATE>;
 370                                 clock-names = "ipg", "per";
 371                         };
 372
 373                         iomuxc: iomuxc@73fa8000 {
 374                                 compatible = "fsl,imx51-iomuxc";
 375                                 reg = <0x73fa8000 0x4000>;
 376                         };
 377
 378                         pwm1: pwm@73fb4000 {
 379                                 #pwm-cells = <2>;
 380                                 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
 381                                 reg = <0x73fb4000 0x4000>;
 382                                 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
 383                                          <&clks IMX5_CLK_PWM1_HF_GATE>;
 384                                 clock-names = "ipg", "per";
 385                                 interrupts = <61>;
 386                         };
 387
 388                         pwm2: pwm@73fb8000 {
 389                                 #pwm-cells = <2>;
 390                                 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
 391                                 reg = <0x73fb8000 0x4000>;
 392                                 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
 393                                          <&clks IMX5_CLK_PWM2_HF_GATE>;
 394                                 clock-names = "ipg", "per";
 395                                 interrupts = <94>;
 396                         };
 397
 398                         uart1: serial@73fbc000 {
 399                                 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
 400                                 reg = <0x73fbc000 0x4000>;
 401                                 interrupts = <31>;
 402                                 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
 403                                          <&clks IMX5_CLK_UART1_PER_GATE>;
 404                                 clock-names = "ipg", "per";
 405                                 status = "disabled";
 406                         };
 407
 408                         uart2: serial@73fc0000 {
 409                                 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
 410                                 reg = <0x73fc0000 0x4000>;
 411                                 interrupts = <32>;
 412                                 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
 413                                          <&clks IMX5_CLK_UART2_PER_GATE>;
 414                                 clock-names = "ipg", "per";
 415                                 status = "disabled";
 416                         };
 417
 418                         src: src@73fd0000 {
 419                                 compatible = "fsl,imx51-src";
 420                                 reg = <0x73fd0000 0x4000>;
 421                                 #reset-cells = <1>;
 422                         };
 423
 424                         clks: ccm@73fd4000{
 425                                 compatible = "fsl,imx51-ccm";
 426                                 reg = <0x73fd4000 0x4000>;
 427                                 interrupts = <0 71 0x04 0 72 0x04>;
 428                                 #clock-cells = <1>;
 429                         };
 430                 };
 431
 432                 aips@80000000 { /* AIPS2 */
 433                         compatible = "fsl,aips-bus", "simple-bus";
 434                         #address-cells = <1>;
 435                         #size-cells = <1>;
 436                         reg = <0x80000000 0x10000000>;
 437                         ranges;
 438
 439                         iim: iim@83f98000 {
 440                                 compatible = "fsl,imx51-iim", "fsl,imx27-iim";
 441                                 reg = <0x83f98000 0x4000>;
 442                                 interrupts = <69>;
 443                                 clocks = <&clks IMX5_CLK_IIM_GATE>;
 444                         };
 445
 446                         owire: owire@83fa4000 {
 447                                 compatible = "fsl,imx51-owire", "fsl,imx21-owire";
 448                                 reg = <0x83fa4000 0x4000>;
 449                                 interrupts = <88>;
 450                                 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
 451                                 status = "disabled";
 452                         };
 453
 454                         ecspi2: ecspi@83fac000 {
 455                                 #address-cells = <1>;
 456                                 #size-cells = <0>;
 457                                 compatible = "fsl,imx51-ecspi";
 458                                 reg = <0x83fac000 0x4000>;
 459                                 interrupts = <37>;
 460                                 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
 461                                          <&clks IMX5_CLK_ECSPI2_PER_GATE>;
 462                                 clock-names = "ipg", "per";
 463                                 status = "disabled";
 464                         };
 465
 466                         sdma: sdma@83fb0000 {
 467                                 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
 468                                 reg = <0x83fb0000 0x4000>;
 469                                 interrupts = <6>;
 470                                 clocks = <&clks IMX5_CLK_SDMA_GATE>,
 471                                          <&clks IMX5_CLK_SDMA_GATE>;
 472                                 clock-names = "ipg", "ahb";
 473                                 #dma-cells = <3>;
 474                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
 475                         };
 476
 477                         cspi: cspi@83fc0000 {
 478                                 #address-cells = <1>;
 479                                 #size-cells = <0>;
 480                                 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
 481                                 reg = <0x83fc0000 0x4000>;
 482                                 interrupts = <38>;
 483                                 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
 484                                          <&clks IMX5_CLK_CSPI_IPG_GATE>;
 485                                 clock-names = "ipg", "per";
 486                                 status = "disabled";
 487                         };
 488
 489                         i2c2: i2c@83fc4000 {
 490                                 #address-cells = <1>;
 491                                 #size-cells = <0>;
 492                                 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
 493                                 reg = <0x83fc4000 0x4000>;
 494                                 interrupts = <63>;
 495                                 clocks = <&clks IMX5_CLK_I2C2_GATE>;
 496                                 status = "disabled";
 497                         };
 498
 499                         i2c1: i2c@83fc8000 {
 500                                 #address-cells = <1>;
 501                                 #size-cells = <0>;
 502                                 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
 503                                 reg = <0x83fc8000 0x4000>;
 504                                 interrupts = <62>;
 505                                 clocks = <&clks IMX5_CLK_I2C1_GATE>;
 506                                 status = "disabled";
 507                         };
 508
 509                         ssi1: ssi@83fcc000 {
 510                                 #sound-dai-cells = <0>;
 511                                 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
 512                                 reg = <0x83fcc000 0x4000>;
 513                                 interrupts = <29>;
 514                                 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
 515                                          <&clks IMX5_CLK_SSI1_ROOT_GATE>;
 516                                 clock-names = "ipg", "baud";
 517                                 dmas = <&sdma 28 0 0>,
 518                                        <&sdma 29 0 0>;
 519                                 dma-names = "rx", "tx";
 520                                 fsl,fifo-depth = <15>;
 521                                 status = "disabled";
 522                         };
 523
 524                         audmux: audmux@83fd0000 {
 525                                 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
 526                                 reg = <0x83fd0000 0x4000>;
 527                                 clocks = <&clks IMX5_CLK_DUMMY>;
 528                                 clock-names = "audmux";
 529                                 status = "disabled";
 530                         };
 531
 532                         weim: weim@83fda000 {
 533                                 #address-cells = <2>;
 534                                 #size-cells = <1>;
 535                                 compatible = "fsl,imx51-weim";
 536                                 reg = <0x83fda000 0x1000>;
 537                                 clocks = <&clks IMX5_CLK_EMI_SLOW_GATE>;
 538                                 ranges = <
 539                                         0 0 0xb0000000 0x08000000
 540                                         1 0 0xb8000000 0x08000000
 541                                         2 0 0xc0000000 0x08000000
 542                                         3 0 0xc8000000 0x04000000
 543                                         4 0 0xcc000000 0x02000000
 544                                         5 0 0xce000000 0x02000000
 545                                 >;
 546                                 status = "disabled";
 547                         };
 548
 549                         nfc: nand@83fdb000 {
 550                                 #address-cells = <1>;
 551                                 #size-cells = <1>;
 552                                 compatible = "fsl,imx51-nand";
 553                                 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
 554                                 interrupts = <8>;
 555                                 clocks = <&clks IMX5_CLK_NFC_GATE>;
 556                                 status = "disabled";
 557                         };
 558
 559                         pata: pata@83fe0000 {
 560                                 compatible = "fsl,imx51-pata", "fsl,imx27-pata";
 561                                 reg = <0x83fe0000 0x4000>;
 562                                 interrupts = <70>;
 563                                 clocks = <&clks IMX5_CLK_PATA_GATE>;
 564                                 status = "disabled";
 565                         };
 566
 567                         ssi3: ssi@83fe8000 {
 568                                 #sound-dai-cells = <0>;
 569                                 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
 570                                 reg = <0x83fe8000 0x4000>;
 571                                 interrupts = <96>;
 572                                 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
 573                                          <&clks IMX5_CLK_SSI3_ROOT_GATE>;
 574                                 clock-names = "ipg", "baud";
 575                                 dmas = <&sdma 46 0 0>,
 576                                        <&sdma 47 0 0>;
 577                                 dma-names = "rx", "tx";
 578                                 fsl,fifo-depth = <15>;
 579                                 status = "disabled";
 580                         };
 581
 582                         fec: ethernet@83fec000 {
 583                                 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
 584                                 reg = <0x83fec000 0x4000>;
 585                                 interrupts = <87>;
 586                                 clocks = <&clks IMX5_CLK_FEC_GATE>,
 587                                          <&clks IMX5_CLK_FEC_GATE>,
 588                                          <&clks IMX5_CLK_FEC_GATE>;
 589                                 clock-names = "ipg", "ahb", "ptp";
 590                                 status = "disabled";
 591                         };
 592                 };
 593         };
 594 };