arch/arm/boot/dts/imx1.dtsi

   1 /*
   2  * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License. You may obtain a copy of the GNU General Public License
   6  * Version 2 or later at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  */
  11
  12 #include "imx1-pinfunc.h"
  13
  14 #include <dt-bindings/clock/imx1-clock.h>
  15 #include <dt-bindings/gpio/gpio.h>
  16 #include <dt-bindings/interrupt-controller/irq.h>
  17
  18 / {
  19         #address-cells = <1>;
  20         #size-cells = <1>;
  21
  22         aliases {
  23                 gpio0 = &gpio1;
  24                 gpio1 = &gpio2;
  25                 gpio2 = &gpio3;
  26                 gpio3 = &gpio4;
  27                 i2c0 = &i2c;
  28                 serial0 = &uart1;
  29                 serial1 = &uart2;
  30                 serial2 = &uart3;
  31                 spi0 = &cspi1;
  32                 spi1 = &cspi2;
  33         };
  34
  35         aitc: aitc-interrupt-controller@00223000 {
  36                 compatible = "fsl,imx1-aitc", "fsl,avic";
  37                 interrupt-controller;
  38                 #interrupt-cells = <1>;
  39                 reg = <0x00223000 0x1000>;
  40         };
  41
  42         cpus {
  43                 #size-cells = <0>;
  44                 #address-cells = <1>;
  45
  46                 cpu: cpu@0 {
  47                         device_type = "cpu";
  48                         compatible = "arm,arm920t";
  49                         operating-points = <200000 1900000>;
  50                         clock-latency = <62500>;
  51                         clocks = <&clks IMX1_CLK_MCU>;
  52                         voltage-tolerance = <5>;
  53                 };
  54         };
  55
  56         soc {
  57                 #address-cells = <1>;
  58                 #size-cells = <1>;
  59                 compatible = "simple-bus";
  60                 interrupt-parent = <&aitc>;
  61                 ranges;
  62
  63                 aipi@00200000 {
  64                         compatible = "fsl,aipi-bus", "simple-bus";
  65                         #address-cells = <1>;
  66                         #size-cells = <1>;
  67                         reg = <0x00200000 0x10000>;
  68                         ranges;
  69
  70                         gpt1: timer@00202000 {
  71                                 compatible = "fsl,imx1-gpt";
  72                                 reg = <0x00202000 0x1000>;
  73                                 interrupts = <59>;
  74                                 clocks = <&clks IMX1_CLK_HCLK>,
  75                                          <&clks IMX1_CLK_PER1>;
  76                                 clock-names = "ipg", "per";
  77                         };
  78
  79                         gpt2: timer@00203000 {
  80                                 compatible = "fsl,imx1-gpt";
  81                                 reg = <0x00203000 0x1000>;
  82                                 interrupts = <58>;
  83                                 clocks = <&clks IMX1_CLK_HCLK>,
  84                                          <&clks IMX1_CLK_PER1>;
  85                                 clock-names = "ipg", "per";
  86                         };
  87
  88                         fb: fb@00205000 {
  89                                 compatible = "fsl,imx1-fb";
  90                                 reg = <0x00205000 0x1000>;
  91                                 interrupts = <14>;
  92                                 clocks = <&clks IMX1_CLK_DUMMY>,
  93                                          <&clks IMX1_CLK_DUMMY>,
  94                                          <&clks IMX1_CLK_PER2>;
  95                                 clock-names = "ipg", "ahb", "per";
  96                                 status = "disabled";
  97                         };
  98
  99                         uart1: serial@00206000 {
 100                                 compatible = "fsl,imx1-uart";
 101                                 reg = <0x00206000 0x1000>;
 102                                 interrupts = <30 29 26>;
 103                                 clocks = <&clks IMX1_CLK_HCLK>,
 104                                          <&clks IMX1_CLK_PER1>;
 105                                 clock-names = "ipg", "per";
 106                                 status = "disabled";
 107                         };
 108
 109                         uart2: serial@00207000 {
 110                                 compatible = "fsl,imx1-uart";
 111                                 reg = <0x00207000 0x1000>;
 112                                 interrupts = <24 23 20>;
 113                                 clocks = <&clks IMX1_CLK_HCLK>,
 114                                          <&clks IMX1_CLK_PER1>;
 115                                 clock-names = "ipg", "per";
 116                                 status = "disabled";
 117                         };
 118
 119                         pwm: pwm@00208000 {
 120                                 #pwm-cells = <2>;
 121                                 compatible = "fsl,imx1-pwm";
 122                                 reg = <0x00208000 0x1000>;
 123                                 interrupts = <34>;
 124                                 clocks = <&clks IMX1_CLK_DUMMY>,
 125                                          <&clks IMX1_CLK_PER1>;
 126                                 clock-names = "ipg", "per";
 127                         };
 128
 129                         dma: dma@00209000 {
 130                                 compatible = "fsl,imx1-dma";
 131                                 reg = <0x00209000 0x1000>;
 132                                 interrupts = <61 60>;
 133                                 clocks = <&clks IMX1_CLK_HCLK>,
 134                                          <&clks IMX1_CLK_DMA_GATE>;
 135                                 clock-names = "ipg", "ahb";
 136                                 #dma-cells = <1>;
 137                         };
 138
 139                         uart3: serial@0020a000 {
 140                                 compatible = "fsl,imx1-uart";
 141                                 reg = <0x0020a000 0x1000>;
 142                                 interrupts = <54 4 1>;
 143                                 clocks = <&clks IMX1_CLK_UART3_GATE>,
 144                                          <&clks IMX1_CLK_PER1>;
 145                                 clock-names = "ipg", "per";
 146                                 status = "disabled";
 147                         };
 148                 };
 149
 150                 aipi@00210000 {
 151                         compatible = "fsl,aipi-bus", "simple-bus";
 152                         #address-cells = <1>;
 153                         #size-cells = <1>;
 154                         reg = <0x00210000 0x10000>;
 155                         ranges;
 156
 157                         cspi1: cspi@00213000 {
 158                                 #address-cells = <1>;
 159                                 #size-cells = <0>;
 160                                 compatible = "fsl,imx1-cspi";
 161                                 reg = <0x00213000 0x1000>;
 162                                 interrupts = <41>;
 163                                 clocks = <&clks IMX1_CLK_DUMMY>,
 164                                          <&clks IMX1_CLK_PER1>;
 165                                 clock-names = "ipg", "per";
 166                                 status = "disabled";
 167                         };
 168
 169                         i2c: i2c@00217000 {
 170                                 #address-cells = <1>;
 171                                 #size-cells = <0>;
 172                                 compatible = "fsl,imx1-i2c";
 173                                 reg = <0x00217000 0x1000>;
 174                                 interrupts = <39>;
 175                                 clocks = <&clks IMX1_CLK_HCLK>;
 176                                 status = "disabled";
 177                         };
 178
 179                         cspi2: cspi@00219000 {
 180                                 #address-cells = <1>;
 181                                 #size-cells = <0>;
 182                                 compatible = "fsl,imx1-cspi";
 183                                 reg = <0x00219000 0x1000>;
 184                                 interrupts = <40>;
 185                                 clocks = <&clks IMX1_CLK_DUMMY>,
 186                                          <&clks IMX1_CLK_PER1>;
 187                                 clock-names = "ipg", "per";
 188                                 status = "disabled";
 189                         };
 190
 191                         clks: ccm@0021b000 {
 192                                 compatible = "fsl,imx1-ccm";
 193                                 reg = <0x0021b000 0x1000>;
 194                                 #clock-cells = <1>;
 195                         };
 196
 197                         iomuxc: iomuxc@0021c000 {
 198                                 compatible = "fsl,imx1-iomuxc";
 199                                 reg = <0x0021c000 0x1000>;
 200                                 #address-cells = <1>;
 201                                 #size-cells = <1>;
 202                                 ranges;
 203
 204                                 gpio1: gpio@0021c000 {
 205                                         compatible = "fsl,imx1-gpio";
 206                                         reg = <0x0021c000 0x100>;
 207                                         interrupts = <11>;
 208                                         gpio-controller;
 209                                         #gpio-cells = <2>;
 210                                         interrupt-controller;
 211                                         #interrupt-cells = <2>;
 212                                 };
 213
 214                                 gpio2: gpio@0021c100 {
 215                                         compatible = "fsl,imx1-gpio";
 216                                         reg = <0x0021c100 0x100>;
 217                                         interrupts = <12>;
 218                                         gpio-controller;
 219                                         #gpio-cells = <2>;
 220                                         interrupt-controller;
 221                                         #interrupt-cells = <2>;
 222                                 };
 223
 224                                 gpio3: gpio@0021c200 {
 225                                         compatible = "fsl,imx1-gpio";
 226                                         reg = <0x0021c200 0x100>;
 227                                         interrupts = <13>;
 228                                         gpio-controller;
 229                                         #gpio-cells = <2>;
 230                                         interrupt-controller;
 231                                         #interrupt-cells = <2>;
 232                                 };
 233
 234                                 gpio4: gpio@0021c300 {
 235                                         compatible = "fsl,imx1-gpio";
 236                                         reg = <0x0021c300 0x100>;
 237                                         interrupts = <62>;
 238                                         gpio-controller;
 239                                         #gpio-cells = <2>;
 240                                         interrupt-controller;
 241                                         #interrupt-cells = <2>;
 242                                 };
 243                         };
 244                 };
 245
 246                 weim: weim@00220000 {
 247                         #address-cells = <2>;
 248                         #size-cells = <1>;
 249                         compatible = "fsl,imx1-weim";
 250                         reg = <0x00220000 0x1000>;
 251                         clocks = <&clks IMX1_CLK_DUMMY>;
 252                         ranges = <
 253                                 0 0 0x10000000 0x02000000
 254                                 1 0 0x12000000 0x01000000
 255                                 2 0 0x13000000 0x01000000
 256                                 3 0 0x14000000 0x01000000
 257                                 4 0 0x15000000 0x01000000
 258                                 5 0 0x16000000 0x01000000
 259                         >;
 260                         status = "disabled";
 261                 };
 262
 263                 esram: esram@00300000 {
 264                         compatible = "mmio-sram";
 265                         reg = <0x00300000 0x20000>;
 266                 };
 267         };
 268 };