arch/arm/boot/dts/gemini.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree file for Cortina systems Gemini SoC
   4  */
   5
   6 /include/ "skeleton.dtsi"
   7
   8 #include <dt-bindings/interrupt-controller/irq.h>
   9 #include <dt-bindings/clock/cortina,gemini-clock.h>
  10 #include <dt-bindings/reset/cortina,gemini-reset.h>
  11 #include <dt-bindings/gpio/gpio.h>
  12
  13 / {
  14         soc {
  15                 #address-cells = <1>;
  16                 #size-cells = <1>;
  17                 ranges;
  18                 compatible = "simple-bus";
  19                 interrupt-parent = <&intcon>;
  20
  21                 flash@30000000 {
  22                         compatible = "cortina,gemini-flash", "cfi-flash";
  23                         syscon = <&syscon>;
  24                         pinctrl-names = "default";
  25                         pinctrl-0 = <&pflash_default_pins>;
  26                         bank-width = <2>;
  27                         #address-cells = <1>;
  28                         #size-cells = <1>;
  29                         status = "disabled";
  30                 };
  31
  32                 syscon: syscon@40000000 {
  33                         compatible = "cortina,gemini-syscon",
  34                                      "syscon", "simple-mfd";
  35                         reg = <0x40000000 0x1000>;
  36                         #clock-cells = <1>;
  37                         #reset-cells = <1>;
  38
  39                         syscon-reboot {
  40                                 compatible = "syscon-reboot";
  41                                 regmap = <&syscon>;
  42                                 /* GLOBAL_RESET register */
  43                                 offset = <0x0c>;
  44                                 /* RESET_GLOBAL | RESET_CPU1 */
  45                                 mask = <0xC0000000>;
  46                         };
  47
  48                         pinctrl {
  49                                 compatible = "cortina,gemini-pinctrl";
  50                                 regmap = <&syscon>;
  51                                 /* Hog the DRAM pins */
  52                                 pinctrl-names = "default";
  53                                 pinctrl-0 = <&dram_default_pins>, <&system_default_pins>,
  54                                             <&vcontrol_default_pins>;
  55
  56                                 dram_default_pins: pinctrl-dram {
  57                                         mux {
  58                                                 function = "dram";
  59                                                 groups = "dramgrp";
  60                                         };
  61                                 };
  62                                 rtc_default_pins: pinctrl-rtc {
  63                                         mux {
  64                                                 function = "rtc";
  65                                                 groups = "rtcgrp";
  66                                         };
  67                                 };
  68                                 power_default_pins: pinctrl-power {
  69                                         mux {
  70                                                 function = "power";
  71                                                 groups = "powergrp";
  72                                         };
  73                                 };
  74                                 cir_default_pins: pinctrl-cir {
  75                                         mux {
  76                                                 function = "cir";
  77                                                 groups = "cirgrp";
  78                                         };
  79                                 };
  80                                 system_default_pins: pinctrl-system {
  81                                         mux {
  82                                                 function = "system";
  83                                                 groups = "systemgrp";
  84                                         };
  85                                 };
  86                                 vcontrol_default_pins: pinctrl-vcontrol {
  87                                         mux {
  88                                                 function = "vcontrol";
  89                                                 groups = "vcontrolgrp";
  90                                         };
  91                                 };
  92                                 ice_default_pins: pinctrl-ice {
  93                                         mux {
  94                                                 function = "ice";
  95                                                 groups = "icegrp";
  96                                         };
  97                                 };
  98                                 uart_default_pins: pinctrl-uart {
  99                                         mux {
 100                                                 function = "uart";
 101                                                 groups = "uartrxtxgrp";
 102                                         };
 103                                 };
 104                                 pflash_default_pins: pinctrl-pflash {
 105                                         mux {
 106                                                 function = "pflash";
 107                                                 groups = "pflashgrp";
 108                                         };
 109                                 };
 110                                 usb_default_pins: pinctrl-usb {
 111                                         mux {
 112                                                 function = "usb";
 113                                                 groups = "usbgrp";
 114                                         };
 115                                 };
 116                                 gmii_default_pins: pinctrl-gmii {
 117                                         mux {
 118                                                 function = "gmii";
 119                                                 groups = "gmiigrp";
 120                                         };
 121                                 };
 122                                 pci_default_pins: pinctrl-pci {
 123                                         mux {
 124                                                 function = "pci";
 125                                                 groups = "pcigrp";
 126                                         };
 127                                 };
 128                                 sata_default_pins: pinctrl-sata {
 129                                         mux {
 130                                                 function = "sata";
 131                                                 groups = "satagrp";
 132                                         };
 133                                 };
 134                                 /* Activate both groups of pins for this state */
 135                                 sata_and_ide_pins: pinctrl-sata-ide {
 136                                         mux0 {
 137                                                 function = "sata";
 138                                                 groups = "satagrp";
 139                                         };
 140                                         mux1 {
 141                                                 function = "ide";
 142                                                 groups = "idegrp";
 143                                         };
 144                                 };
 145                                 tvc_default_pins: pinctrl-tvc {
 146                                         mux {
 147                                                 function = "tvc";
 148                                                 groups = "tvcgrp";
 149                                         };
 150                                 };
 151                         };
 152                 };
 153
 154                 watchdog@41000000 {
 155                         compatible = "cortina,gemini-watchdog", "faraday,ftwdt010";
 156                         reg = <0x41000000 0x1000>;
 157                         interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
 158                         resets = <&syscon GEMINI_RESET_WDOG>;
 159                         clocks = <&syscon GEMINI_CLK_APB>;
 160                         clock-names = "PCLK";
 161                 };
 162
 163                 uart0: serial@42000000 {
 164                         compatible = "ns16550a";
 165                         reg = <0x42000000 0x100>;
 166                         resets = <&syscon GEMINI_RESET_UART>;
 167                         clocks = <&syscon GEMINI_CLK_UART>;
 168                         interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
 169                         pinctrl-names = "default";
 170                         pinctrl-0 = <&uart_default_pins>;
 171                         reg-shift = <2>;
 172                 };
 173
 174                 timer@43000000 {
 175                         compatible = "faraday,fttmr010";
 176                         reg = <0x43000000 0x1000>;
 177                         interrupt-parent = <&intcon>;
 178                         interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */
 179                                      <15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */
 180                                      <16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */
 181                         resets = <&syscon GEMINI_RESET_TIMER>;
 182                         /* APB clock or RTC clock */
 183                         clocks = <&syscon GEMINI_CLK_APB>, <&syscon GEMINI_CLK_RTC>;
 184                         clock-names = "PCLK", "EXTCLK";
 185                         syscon = <&syscon>;
 186                 };
 187
 188                 rtc@45000000 {
 189                         compatible = "cortina,gemini-rtc";
 190                         reg = <0x45000000 0x100>;
 191                         interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
 192                         resets = <&syscon GEMINI_RESET_RTC>;
 193                         clocks = <&syscon GEMINI_CLK_APB>, <&syscon GEMINI_CLK_RTC>;
 194                         clock-names = "PCLK", "EXTCLK";
 195                         pinctrl-names = "default";
 196                         pinctrl-0 = <&rtc_default_pins>;
 197                 };
 198
 199                 sata: sata@46000000 {
 200                         compatible = "cortina,gemini-sata-bridge";
 201                         reg = <0x46000000 0x100>;
 202                         resets = <&syscon GEMINI_RESET_SATA0>,
 203                                  <&syscon GEMINI_RESET_SATA1>;
 204                         reset-names = "sata0", "sata1";
 205                         clocks = <&syscon GEMINI_CLK_GATE_SATA0>,
 206                                  <&syscon GEMINI_CLK_GATE_SATA1>;
 207                         clock-names = "SATA0_PCLK", "SATA1_PCLK";
 208                         /*
 209                          * This defines the special "ide" state that needs
 210                          * to be explicitly enabled to enable the IDE pins,
 211                          * as these pins are normally used for other things.
 212                          */
 213                         pinctrl-names = "default", "ide";
 214                         pinctrl-0 = <&sata_default_pins>;
 215                         pinctrl-1 = <&sata_and_ide_pins>;
 216                         syscon = <&syscon>;
 217                         status = "disabled";
 218                 };
 219
 220                 intcon: interrupt-controller@48000000 {
 221                         compatible = "faraday,ftintc010";
 222                         reg = <0x48000000 0x1000>;
 223                         resets = <&syscon GEMINI_RESET_INTCON0>;
 224                         interrupt-controller;
 225                         #interrupt-cells = <2>;
 226                 };
 227
 228                 power-controller@4b000000 {
 229                         compatible = "cortina,gemini-power-controller";
 230                         reg = <0x4b000000 0x100>;
 231                         interrupts = <26 IRQ_TYPE_EDGE_RISING>;
 232                         pinctrl-names = "default";
 233                         pinctrl-0 = <&power_default_pins>;
 234                 };
 235
 236                 gpio0: gpio@4d000000 {
 237                         compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
 238                         reg = <0x4d000000 0x100>;
 239                         interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
 240                         resets = <&syscon GEMINI_RESET_GPIO0>;
 241                         clocks = <&syscon GEMINI_CLK_APB>;
 242                         gpio-controller;
 243                         #gpio-cells = <2>;
 244                         interrupt-controller;
 245                         #interrupt-cells = <2>;
 246                 };
 247
 248                 gpio1: gpio@4e000000 {
 249                         compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
 250                         reg = <0x4e000000 0x100>;
 251                         interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
 252                         resets = <&syscon GEMINI_RESET_GPIO1>;
 253                         clocks = <&syscon GEMINI_CLK_APB>;
 254                         gpio-controller;
 255                         #gpio-cells = <2>;
 256                         interrupt-controller;
 257                         #interrupt-cells = <2>;
 258                 };
 259
 260                 gpio2: gpio@4f000000 {
 261                         compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
 262                         reg = <0x4f000000 0x100>;
 263                         interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
 264                         resets = <&syscon GEMINI_RESET_GPIO2>;
 265                         clocks = <&syscon GEMINI_CLK_APB>;
 266                         gpio-controller;
 267                         #gpio-cells = <2>;
 268                         interrupt-controller;
 269                         #interrupt-cells = <2>;
 270                 };
 271
 272                 pci@50000000 {
 273                         compatible = "cortina,gemini-pci", "faraday,ftpci100";
 274                         /*
 275                          * The first 256 bytes in the IO range is actually used
 276                          * to configure the host bridge.
 277                          */
 278                         reg = <0x50000000 0x100>;
 279                         resets = <&syscon GEMINI_RESET_PCI>;
 280                         clocks = <&syscon GEMINI_CLK_GATE_PCI>, <&syscon GEMINI_CLK_PCI>;
 281                         clock-names = "PCLK", "PCICLK";
 282                         pinctrl-names = "default";
 283                         pinctrl-0 = <&pci_default_pins>;
 284                         #address-cells = <3>;
 285                         #size-cells = <2>;
 286                         #interrupt-cells = <1>;
 287                         status = "disabled";
 288
 289                         bus-range = <0x00 0xff>;
 290                         /* PCI ranges mappings */
 291                         ranges =
 292                         /* 1MiB I/O space 0x50000000-0x500fffff */
 293                         <0x01000000 0 0          0x50000000 0 0x00100000>,
 294                         /* 128MiB non-prefetchable memory 0x58000000-0x5fffffff */
 295                         <0x02000000 0 0x58000000 0x58000000 0 0x08000000>;
 296
 297                         /* DMA ranges */
 298                         dma-ranges =
 299                         /* 128MiB at 0x00000000-0x07ffffff */
 300                         <0x02000000 0 0x00000000 0x00000000 0 0x08000000>,
 301                         /* 64MiB at 0x00000000-0x03ffffff */
 302                         <0x02000000 0 0x00000000 0x00000000 0 0x04000000>,
 303                         /* 64MiB at 0x00000000-0x03ffffff */
 304                         <0x02000000 0 0x00000000 0x00000000 0 0x04000000>;
 305
 306                         /*
 307                          * This PCI host bridge variant has a cascaded interrupt
 308                          * controller embedded in the host bridge.
 309                          */
 310                         pci_intc: interrupt-controller {
 311                                 interrupt-parent = <&intcon>;
 312                                 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
 313                                 interrupt-controller;
 314                                 #address-cells = <0>;
 315                                 #interrupt-cells = <1>;
 316                         };
 317                 };
 318
 319                 ata@63000000 {
 320                         compatible = "cortina,gemini-pata", "faraday,ftide010";
 321                         reg = <0x63000000 0x1000>;
 322                         interrupts = <4 IRQ_TYPE_EDGE_RISING>;
 323                         resets = <&syscon GEMINI_RESET_IDE>;
 324                         clocks = <&syscon GEMINI_CLK_GATE_IDE>;
 325                         clock-names = "PCLK";
 326                         sata = <&sata>;
 327                         status = "disabled";
 328                 };
 329
 330                 ata@63400000 {
 331                         compatible = "cortina,gemini-pata", "faraday,ftide010";
 332                         reg = <0x63400000 0x1000>;
 333                         interrupts = <5 IRQ_TYPE_EDGE_RISING>;
 334                         resets = <&syscon GEMINI_RESET_IDE>;
 335                         clocks = <&syscon GEMINI_CLK_GATE_IDE>;
 336                         clock-names = "PCLK";
 337                         sata = <&sata>;
 338                         status = "disabled";
 339                 };
 340
 341                 dma-controller@67000000 {
 342                         compatible = "faraday,ftdma020", "arm,pl080", "arm,primecell";
 343                         /* Faraday Technology FTDMAC020 variant */
 344                         arm,primecell-periphid = <0x0003b080>;
 345                         reg = <0x67000000 0x1000>;
 346                         interrupts = <9 IRQ_TYPE_EDGE_RISING>;
 347                         resets = <&syscon GEMINI_RESET_DMAC>;
 348                         clocks = <&syscon GEMINI_CLK_AHB>;
 349                         clock-names = "apb_pclk";
 350                         /* Bus interface AHB1 (AHB0) is totally tilted */
 351                         lli-bus-interface-ahb2;
 352                         mem-bus-interface-ahb2;
 353                         memcpy-burst-size = <256>;
 354                         memcpy-bus-width = <32>;
 355                         #dma-cells = <2>;
 356                 };
 357
 358                 display-controller@6a000000 {
 359                         compatible = "cortina,gemini-tvc", "faraday,tve200";
 360                         reg = <0x6a000000 0x1000>;
 361                         interrupts = <13 IRQ_TYPE_EDGE_RISING>;
 362                         resets = <&syscon GEMINI_RESET_TVC>;
 363                         clocks = <&syscon GEMINI_CLK_GATE_TVC>,
 364                                  <&syscon GEMINI_CLK_TVC>;
 365                         clock-names = "PCLK", "TVE";
 366                         pinctrl-names = "default";
 367                         pinctrl-0 = <&tvc_default_pins>;
 368                         #address-cells = <1>;
 369                         #size-cells = <0>;
 370                         status = "disabled";
 371                 };
 372         };
 373 };