arch/arm/boot/dts/exynos5420.dtsi

   1 /*
   2  * SAMSUNG EXYNOS5420 SoC device tree source
   3  *
   4  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
   8  * EXYNOS5420 based board files can include this file and provide
   9  * values for board specfic bindings.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include <dt-bindings/clock/exynos5420.h>
  17 #include "exynos5.dtsi"
  18 #include "exynos5420-pinctrl.dtsi"
  19
  20 #include <dt-bindings/clock/exynos-audss-clk.h>
  21
  22 / {
  23         compatible = "samsung,exynos5420", "samsung,exynos5";
  24
  25         aliases {
  26                 mshc0 = &mmc_0;
  27                 mshc1 = &mmc_1;
  28                 mshc2 = &mmc_2;
  29                 pinctrl0 = &pinctrl_0;
  30                 pinctrl1 = &pinctrl_1;
  31                 pinctrl2 = &pinctrl_2;
  32                 pinctrl3 = &pinctrl_3;
  33                 pinctrl4 = &pinctrl_4;
  34                 i2c0 = &i2c_0;
  35                 i2c1 = &i2c_1;
  36                 i2c2 = &i2c_2;
  37                 i2c3 = &i2c_3;
  38                 i2c4 = &hsi2c_4;
  39                 i2c5 = &hsi2c_5;
  40                 i2c6 = &hsi2c_6;
  41                 i2c7 = &hsi2c_7;
  42                 i2c8 = &hsi2c_8;
  43                 i2c9 = &hsi2c_9;
  44                 i2c10 = &hsi2c_10;
  45                 gsc0 = &gsc_0;
  46                 gsc1 = &gsc_1;
  47                 spi0 = &spi_0;
  48                 spi1 = &spi_1;
  49                 spi2 = &spi_2;
  50                 usbdrdphy0 = &usbdrd_phy0;
  51                 usbdrdphy1 = &usbdrd_phy1;
  52         };
  53
  54         cpus {
  55                 #address-cells = <1>;
  56                 #size-cells = <0>;
  57
  58                 cpu0: cpu@0 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a15";
  61                         reg = <0x0>;
  62                         clock-frequency = <1800000000>;
  63                         cci-control-port = <&cci_control1>;
  64                 };
  65
  66                 cpu1: cpu@1 {
  67                         device_type = "cpu";
  68                         compatible = "arm,cortex-a15";
  69                         reg = <0x1>;
  70                         clock-frequency = <1800000000>;
  71                         cci-control-port = <&cci_control1>;
  72                 };
  73
  74                 cpu2: cpu@2 {
  75                         device_type = "cpu";
  76                         compatible = "arm,cortex-a15";
  77                         reg = <0x2>;
  78                         clock-frequency = <1800000000>;
  79                         cci-control-port = <&cci_control1>;
  80                 };
  81
  82                 cpu3: cpu@3 {
  83                         device_type = "cpu";
  84                         compatible = "arm,cortex-a15";
  85                         reg = <0x3>;
  86                         clock-frequency = <1800000000>;
  87                         cci-control-port = <&cci_control1>;
  88                 };
  89
  90                 cpu4: cpu@100 {
  91                         device_type = "cpu";
  92                         compatible = "arm,cortex-a7";
  93                         reg = <0x100>;
  94                         clock-frequency = <1000000000>;
  95                         cci-control-port = <&cci_control0>;
  96                 };
  97
  98                 cpu5: cpu@101 {
  99                         device_type = "cpu";
 100                         compatible = "arm,cortex-a7";
 101                         reg = <0x101>;
 102                         clock-frequency = <1000000000>;
 103                         cci-control-port = <&cci_control0>;
 104                 };
 105
 106                 cpu6: cpu@102 {
 107                         device_type = "cpu";
 108                         compatible = "arm,cortex-a7";
 109                         reg = <0x102>;
 110                         clock-frequency = <1000000000>;
 111                         cci-control-port = <&cci_control0>;
 112                 };
 113
 114                 cpu7: cpu@103 {
 115                         device_type = "cpu";
 116                         compatible = "arm,cortex-a7";
 117                         reg = <0x103>;
 118                         clock-frequency = <1000000000>;
 119                         cci-control-port = <&cci_control0>;
 120                 };
 121         };
 122
 123         cci@10d20000 {
 124                 compatible = "arm,cci-400";
 125                 #address-cells = <1>;
 126                 #size-cells = <1>;
 127                 reg = <0x10d20000 0x1000>;
 128                 ranges = <0x0 0x10d20000 0x6000>;
 129
 130                 cci_control0: slave-if@4000 {
 131                         compatible = "arm,cci-400-ctrl-if";
 132                         interface-type = "ace";
 133                         reg = <0x4000 0x1000>;
 134                 };
 135                 cci_control1: slave-if@5000 {
 136                         compatible = "arm,cci-400-ctrl-if";
 137                         interface-type = "ace";
 138                         reg = <0x5000 0x1000>;
 139                 };
 140         };
 141
 142         sysram@02020000 {
 143                 compatible = "mmio-sram";
 144                 reg = <0x02020000 0x54000>;
 145                 #address-cells = <1>;
 146                 #size-cells = <1>;
 147                 ranges = <0 0x02020000 0x54000>;
 148
 149                 smp-sysram@0 {
 150                         compatible = "samsung,exynos4210-sysram";
 151                         reg = <0x0 0x1000>;
 152                 };
 153
 154                 smp-sysram@53000 {
 155                         compatible = "samsung,exynos4210-sysram-ns";
 156                         reg = <0x53000 0x1000>;
 157                 };
 158         };
 159
 160         clock: clock-controller@10010000 {
 161                 compatible = "samsung,exynos5420-clock";
 162                 reg = <0x10010000 0x30000>;
 163                 #clock-cells = <1>;
 164         };
 165
 166         clock_audss: audss-clock-controller@3810000 {
 167                 compatible = "samsung,exynos5420-audss-clock";
 168                 reg = <0x03810000 0x0C>;
 169                 #clock-cells = <1>;
 170                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
 171                          <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
 172                 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
 173         };
 174
 175         mfc: codec@11000000 {
 176                 compatible = "samsung,mfc-v7";
 177                 reg = <0x11000000 0x10000>;
 178                 interrupts = <0 96 0>;
 179                 clocks = <&clock CLK_MFC>;
 180                 clock-names = "mfc";
 181                 samsung,power-domain = <&mfc_pd>;
 182         };
 183
 184         mmc_0: mmc@12200000 {
 185                 compatible = "samsung,exynos5420-dw-mshc-smu";
 186                 interrupts = <0 75 0>;
 187                 #address-cells = <1>;
 188                 #size-cells = <0>;
 189                 reg = <0x12200000 0x2000>;
 190                 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
 191                 clock-names = "biu", "ciu";
 192                 fifo-depth = <0x40>;
 193                 status = "disabled";
 194         };
 195
 196         mmc_1: mmc@12210000 {
 197                 compatible = "samsung,exynos5420-dw-mshc-smu";
 198                 interrupts = <0 76 0>;
 199                 #address-cells = <1>;
 200                 #size-cells = <0>;
 201                 reg = <0x12210000 0x2000>;
 202                 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
 203                 clock-names = "biu", "ciu";
 204                 fifo-depth = <0x40>;
 205                 status = "disabled";
 206         };
 207
 208         mmc_2: mmc@12220000 {
 209                 compatible = "samsung,exynos5420-dw-mshc";
 210                 interrupts = <0 77 0>;
 211                 #address-cells = <1>;
 212                 #size-cells = <0>;
 213                 reg = <0x12220000 0x1000>;
 214                 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
 215                 clock-names = "biu", "ciu";
 216                 fifo-depth = <0x40>;
 217                 status = "disabled";
 218         };
 219
 220         mct: mct@101C0000 {
 221                 compatible = "samsung,exynos4210-mct";
 222                 reg = <0x101C0000 0x800>;
 223                 interrupt-controller;
 224                 #interrups-cells = <1>;
 225                 interrupt-parent = <&mct_map>;
 226                 interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
 227                                 <8>, <9>, <10>, <11>;
 228                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
 229                 clock-names = "fin_pll", "mct";
 230
 231                 mct_map: mct-map {
 232                         #interrupt-cells = <1>;
 233                         #address-cells = <0>;
 234                         #size-cells = <0>;
 235                         interrupt-map = <0 &combiner 23 3>,
 236                                         <1 &combiner 23 4>,
 237                                         <2 &combiner 25 2>,
 238                                         <3 &combiner 25 3>,
 239                                         <4 &gic 0 120 0>,
 240                                         <5 &gic 0 121 0>,
 241                                         <6 &gic 0 122 0>,
 242                                         <7 &gic 0 123 0>,
 243                                         <8 &gic 0 128 0>,
 244                                         <9 &gic 0 129 0>,
 245                                         <10 &gic 0 130 0>,
 246                                         <11 &gic 0 131 0>;
 247                 };
 248         };
 249
 250         gsc_pd: power-domain@10044000 {
 251                 compatible = "samsung,exynos4210-pd";
 252                 reg = <0x10044000 0x20>;
 253         };
 254
 255         isp_pd: power-domain@10044020 {
 256                 compatible = "samsung,exynos4210-pd";
 257                 reg = <0x10044020 0x20>;
 258         };
 259
 260         mfc_pd: power-domain@10044060 {
 261                 compatible = "samsung,exynos4210-pd";
 262                 reg = <0x10044060 0x20>;
 263                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>,
 264                         <&clock CLK_MOUT_USER_ACLK333>;
 265                 clock-names = "oscclk", "pclk0", "clk0";
 266         };
 267
 268         disp_pd: power-domain@100440C0 {
 269                 compatible = "samsung,exynos4210-pd";
 270                 reg = <0x100440C0 0x20>;
 271         };
 272
 273         msc_pd: power-domain@10044120 {
 274                 compatible = "samsung,exynos4210-pd";
 275                 reg = <0x10044120 0x20>;
 276         };
 277
 278         pinctrl_0: pinctrl@13400000 {
 279                 compatible = "samsung,exynos5420-pinctrl";
 280                 reg = <0x13400000 0x1000>;
 281                 interrupts = <0 45 0>;
 282
 283                 wakeup-interrupt-controller {
 284                         compatible = "samsung,exynos4210-wakeup-eint";
 285                         interrupt-parent = <&gic>;
 286                         interrupts = <0 32 0>;
 287                 };
 288         };
 289
 290         pinctrl_1: pinctrl@13410000 {
 291                 compatible = "samsung,exynos5420-pinctrl";
 292                 reg = <0x13410000 0x1000>;
 293                 interrupts = <0 78 0>;
 294         };
 295
 296         pinctrl_2: pinctrl@14000000 {
 297                 compatible = "samsung,exynos5420-pinctrl";
 298                 reg = <0x14000000 0x1000>;
 299                 interrupts = <0 46 0>;
 300         };
 301
 302         pinctrl_3: pinctrl@14010000 {
 303                 compatible = "samsung,exynos5420-pinctrl";
 304                 reg = <0x14010000 0x1000>;
 305                 interrupts = <0 50 0>;
 306         };
 307
 308         pinctrl_4: pinctrl@03860000 {
 309                 compatible = "samsung,exynos5420-pinctrl";
 310                 reg = <0x03860000 0x1000>;
 311                 interrupts = <0 47 0>;
 312         };
 313
 314         rtc: rtc@101E0000 {
 315                 clocks = <&clock CLK_RTC>;
 316                 clock-names = "rtc";
 317                 status = "disabled";
 318         };
 319
 320         amba {
 321                 #address-cells = <1>;
 322                 #size-cells = <1>;
 323                 compatible = "arm,amba-bus";
 324                 interrupt-parent = <&gic>;
 325                 ranges;
 326
 327                 adma: adma@03880000 {
 328                         compatible = "arm,pl330", "arm,primecell";
 329                         reg = <0x03880000 0x1000>;
 330                         interrupts = <0 110 0>;
 331                         clocks = <&clock_audss EXYNOS_ADMA>;
 332                         clock-names = "apb_pclk";
 333                         #dma-cells = <1>;
 334                         #dma-channels = <6>;
 335                         #dma-requests = <16>;
 336                 };
 337
 338                 pdma0: pdma@121A0000 {
 339                         compatible = "arm,pl330", "arm,primecell";
 340                         reg = <0x121A0000 0x1000>;
 341                         interrupts = <0 34 0>;
 342                         clocks = <&clock CLK_PDMA0>;
 343                         clock-names = "apb_pclk";
 344                         #dma-cells = <1>;
 345                         #dma-channels = <8>;
 346                         #dma-requests = <32>;
 347                 };
 348
 349                 pdma1: pdma@121B0000 {
 350                         compatible = "arm,pl330", "arm,primecell";
 351                         reg = <0x121B0000 0x1000>;
 352                         interrupts = <0 35 0>;
 353                         clocks = <&clock CLK_PDMA1>;
 354                         clock-names = "apb_pclk";
 355                         #dma-cells = <1>;
 356                         #dma-channels = <8>;
 357                         #dma-requests = <32>;
 358                 };
 359
 360                 mdma0: mdma@10800000 {
 361                         compatible = "arm,pl330", "arm,primecell";
 362                         reg = <0x10800000 0x1000>;
 363                         interrupts = <0 33 0>;
 364                         clocks = <&clock CLK_MDMA0>;
 365                         clock-names = "apb_pclk";
 366                         #dma-cells = <1>;
 367                         #dma-channels = <8>;
 368                         #dma-requests = <1>;
 369                 };
 370
 371                 mdma1: mdma@11C10000 {
 372                         compatible = "arm,pl330", "arm,primecell";
 373                         reg = <0x11C10000 0x1000>;
 374                         interrupts = <0 124 0>;
 375                         clocks = <&clock CLK_MDMA1>;
 376                         clock-names = "apb_pclk";
 377                         #dma-cells = <1>;
 378                         #dma-channels = <8>;
 379                         #dma-requests = <1>;
 380                         /*
 381                          * MDMA1 can support both secure and non-secure
 382                          * AXI transactions. When this is enabled in the kernel
 383                          * for boards that run in secure mode, we are getting
 384                          * imprecise external aborts causing the kernel to oops.
 385                          */
 386                         status = "disabled";
 387                 };
 388         };
 389
 390         i2s0: i2s@03830000 {
 391                 compatible = "samsung,exynos5420-i2s";
 392                 reg = <0x03830000 0x100>;
 393                 dmas = <&adma 0
 394                         &adma 2
 395                         &adma 1>;
 396                 dma-names = "tx", "rx", "tx-sec";
 397                 clocks = <&clock_audss EXYNOS_I2S_BUS>,
 398                         <&clock_audss EXYNOS_I2S_BUS>,
 399                         <&clock_audss EXYNOS_SCLK_I2S>;
 400                 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
 401                 samsung,idma-addr = <0x03000000>;
 402                 pinctrl-names = "default";
 403                 pinctrl-0 = <&i2s0_bus>;
 404                 status = "disabled";
 405         };
 406
 407         i2s1: i2s@12D60000 {
 408                 compatible = "samsung,exynos5420-i2s";
 409                 reg = <0x12D60000 0x100>;
 410                 dmas = <&pdma1 12
 411                         &pdma1 11>;
 412                 dma-names = "tx", "rx";
 413                 clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
 414                 clock-names = "iis", "i2s_opclk0";
 415                 pinctrl-names = "default";
 416                 pinctrl-0 = <&i2s1_bus>;
 417                 status = "disabled";
 418         };
 419
 420         i2s2: i2s@12D70000 {
 421                 compatible = "samsung,exynos5420-i2s";
 422                 reg = <0x12D70000 0x100>;
 423                 dmas = <&pdma0 12
 424                         &pdma0 11>;
 425                 dma-names = "tx", "rx";
 426                 clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
 427                 clock-names = "iis", "i2s_opclk0";
 428                 pinctrl-names = "default";
 429                 pinctrl-0 = <&i2s2_bus>;
 430                 status = "disabled";
 431         };
 432
 433         spi_0: spi@12d20000 {
 434                 compatible = "samsung,exynos4210-spi";
 435                 reg = <0x12d20000 0x100>;
 436                 interrupts = <0 68 0>;
 437                 dmas = <&pdma0 5
 438                         &pdma0 4>;
 439                 dma-names = "tx", "rx";
 440                 #address-cells = <1>;
 441                 #size-cells = <0>;
 442                 pinctrl-names = "default";
 443                 pinctrl-0 = <&spi0_bus>;
 444                 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
 445                 clock-names = "spi", "spi_busclk0";
 446                 status = "disabled";
 447         };
 448
 449         spi_1: spi@12d30000 {
 450                 compatible = "samsung,exynos4210-spi";
 451                 reg = <0x12d30000 0x100>;
 452                 interrupts = <0 69 0>;
 453                 dmas = <&pdma1 5
 454                         &pdma1 4>;
 455                 dma-names = "tx", "rx";
 456                 #address-cells = <1>;
 457                 #size-cells = <0>;
 458                 pinctrl-names = "default";
 459                 pinctrl-0 = <&spi1_bus>;
 460                 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
 461                 clock-names = "spi", "spi_busclk0";
 462                 status = "disabled";
 463         };
 464
 465         spi_2: spi@12d40000 {
 466                 compatible = "samsung,exynos4210-spi";
 467                 reg = <0x12d40000 0x100>;
 468                 interrupts = <0 70 0>;
 469                 dmas = <&pdma0 7
 470                         &pdma0 6>;
 471                 dma-names = "tx", "rx";
 472                 #address-cells = <1>;
 473                 #size-cells = <0>;
 474                 pinctrl-names = "default";
 475                 pinctrl-0 = <&spi2_bus>;
 476                 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
 477                 clock-names = "spi", "spi_busclk0";
 478                 status = "disabled";
 479         };
 480
 481         uart_0: serial@12C00000 {
 482                 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
 483                 clock-names = "uart", "clk_uart_baud0";
 484         };
 485
 486         uart_1: serial@12C10000 {
 487                 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
 488                 clock-names = "uart", "clk_uart_baud0";
 489         };
 490
 491         uart_2: serial@12C20000 {
 492                 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
 493                 clock-names = "uart", "clk_uart_baud0";
 494         };
 495
 496         uart_3: serial@12C30000 {
 497                 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
 498                 clock-names = "uart", "clk_uart_baud0";
 499         };
 500
 501         pwm: pwm@12dd0000 {
 502                 compatible = "samsung,exynos4210-pwm";
 503                 reg = <0x12dd0000 0x100>;
 504                 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
 505                 #pwm-cells = <3>;
 506                 clocks = <&clock CLK_PWM>;
 507                 clock-names = "timers";
 508         };
 509
 510         dp_phy: video-phy@10040728 {
 511                 compatible = "samsung,exynos5250-dp-video-phy";
 512                 reg = <0x10040728 4>;
 513                 #phy-cells = <0>;
 514         };
 515
 516         dp: dp-controller@145B0000 {
 517                 clocks = <&clock CLK_DP1>;
 518                 clock-names = "dp";
 519                 phys = <&dp_phy>;
 520                 phy-names = "dp";
 521         };
 522
 523         fimd: fimd@14400000 {
 524                 samsung,power-domain = <&disp_pd>;
 525                 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
 526                 clock-names = "sclk_fimd", "fimd";
 527         };
 528
 529         adc: adc@12D10000 {
 530                 compatible = "samsung,exynos-adc-v2";
 531                 reg = <0x12D10000 0x100>, <0x10040720 0x4>;
 532                 interrupts = <0 106 0>;
 533                 clocks = <&clock CLK_TSADC>;
 534                 clock-names = "adc";
 535                 #io-channel-cells = <1>;
 536                 io-channel-ranges;
 537                 status = "disabled";
 538         };
 539
 540         i2c_0: i2c@12C60000 {
 541                 compatible = "samsung,s3c2440-i2c";
 542                 reg = <0x12C60000 0x100>;
 543                 interrupts = <0 56 0>;
 544                 #address-cells = <1>;
 545                 #size-cells = <0>;
 546                 clocks = <&clock CLK_I2C0>;
 547                 clock-names = "i2c";
 548                 pinctrl-names = "default";
 549                 pinctrl-0 = <&i2c0_bus>;
 550                 status = "disabled";
 551         };
 552
 553         i2c_1: i2c@12C70000 {
 554                 compatible = "samsung,s3c2440-i2c";
 555                 reg = <0x12C70000 0x100>;
 556                 interrupts = <0 57 0>;
 557                 #address-cells = <1>;
 558                 #size-cells = <0>;
 559                 clocks = <&clock CLK_I2C1>;
 560                 clock-names = "i2c";
 561                 pinctrl-names = "default";
 562                 pinctrl-0 = <&i2c1_bus>;
 563                 status = "disabled";
 564         };
 565
 566         i2c_2: i2c@12C80000 {
 567                 compatible = "samsung,s3c2440-i2c";
 568                 reg = <0x12C80000 0x100>;
 569                 interrupts = <0 58 0>;
 570                 #address-cells = <1>;
 571                 #size-cells = <0>;
 572                 clocks = <&clock CLK_I2C2>;
 573                 clock-names = "i2c";
 574                 pinctrl-names = "default";
 575                 pinctrl-0 = <&i2c2_bus>;
 576                 status = "disabled";
 577         };
 578
 579         i2c_3: i2c@12C90000 {
 580                 compatible = "samsung,s3c2440-i2c";
 581                 reg = <0x12C90000 0x100>;
 582                 interrupts = <0 59 0>;
 583                 #address-cells = <1>;
 584                 #size-cells = <0>;
 585                 clocks = <&clock CLK_I2C3>;
 586                 clock-names = "i2c";
 587                 pinctrl-names = "default";
 588                 pinctrl-0 = <&i2c3_bus>;
 589                 status = "disabled";
 590         };
 591
 592         hsi2c_4: i2c@12CA0000 {
 593                 compatible = "samsung,exynos5-hsi2c";
 594                 reg = <0x12CA0000 0x1000>;
 595                 interrupts = <0 60 0>;
 596                 #address-cells = <1>;
 597                 #size-cells = <0>;
 598                 pinctrl-names = "default";
 599                 pinctrl-0 = <&i2c4_hs_bus>;
 600                 clocks = <&clock CLK_USI0>;
 601                 clock-names = "hsi2c";
 602                 status = "disabled";
 603         };
 604
 605         hsi2c_5: i2c@12CB0000 {
 606                 compatible = "samsung,exynos5-hsi2c";
 607                 reg = <0x12CB0000 0x1000>;
 608                 interrupts = <0 61 0>;
 609                 #address-cells = <1>;
 610                 #size-cells = <0>;
 611                 pinctrl-names = "default";
 612                 pinctrl-0 = <&i2c5_hs_bus>;
 613                 clocks = <&clock CLK_USI1>;
 614                 clock-names = "hsi2c";
 615                 status = "disabled";
 616         };
 617
 618         hsi2c_6: i2c@12CC0000 {
 619                 compatible = "samsung,exynos5-hsi2c";
 620                 reg = <0x12CC0000 0x1000>;
 621                 interrupts = <0 62 0>;
 622                 #address-cells = <1>;
 623                 #size-cells = <0>;
 624                 pinctrl-names = "default";
 625                 pinctrl-0 = <&i2c6_hs_bus>;
 626                 clocks = <&clock CLK_USI2>;
 627                 clock-names = "hsi2c";
 628                 status = "disabled";
 629         };
 630
 631         hsi2c_7: i2c@12CD0000 {
 632                 compatible = "samsung,exynos5-hsi2c";
 633                 reg = <0x12CD0000 0x1000>;
 634                 interrupts = <0 63 0>;
 635                 #address-cells = <1>;
 636                 #size-cells = <0>;
 637                 pinctrl-names = "default";
 638                 pinctrl-0 = <&i2c7_hs_bus>;
 639                 clocks = <&clock CLK_USI3>;
 640                 clock-names = "hsi2c";
 641                 status = "disabled";
 642         };
 643
 644         hsi2c_8: i2c@12E00000 {
 645                 compatible = "samsung,exynos5-hsi2c";
 646                 reg = <0x12E00000 0x1000>;
 647                 interrupts = <0 87 0>;
 648                 #address-cells = <1>;
 649                 #size-cells = <0>;
 650                 pinctrl-names = "default";
 651                 pinctrl-0 = <&i2c8_hs_bus>;
 652                 clocks = <&clock CLK_USI4>;
 653                 clock-names = "hsi2c";
 654                 status = "disabled";
 655         };
 656
 657         hsi2c_9: i2c@12E10000 {
 658                 compatible = "samsung,exynos5-hsi2c";
 659                 reg = <0x12E10000 0x1000>;
 660                 interrupts = <0 88 0>;
 661                 #address-cells = <1>;
 662                 #size-cells = <0>;
 663                 pinctrl-names = "default";
 664                 pinctrl-0 = <&i2c9_hs_bus>;
 665                 clocks = <&clock CLK_USI5>;
 666                 clock-names = "hsi2c";
 667                 status = "disabled";
 668         };
 669
 670         hsi2c_10: i2c@12E20000 {
 671                 compatible = "samsung,exynos5-hsi2c";
 672                 reg = <0x12E20000 0x1000>;
 673                 interrupts = <0 203 0>;
 674                 #address-cells = <1>;
 675                 #size-cells = <0>;
 676                 pinctrl-names = "default";
 677                 pinctrl-0 = <&i2c10_hs_bus>;
 678                 clocks = <&clock CLK_USI6>;
 679                 clock-names = "hsi2c";
 680                 status = "disabled";
 681         };
 682
 683         hdmi: hdmi@14530000 {
 684                 compatible = "samsung,exynos5420-hdmi";
 685                 reg = <0x14530000 0x70000>;
 686                 interrupts = <0 95 0>;
 687                 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
 688                          <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
 689                          <&clock CLK_MOUT_HDMI>;
 690                 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
 691                         "sclk_hdmiphy", "mout_hdmi";
 692                 phy = <&hdmiphy>;
 693                 samsung,syscon-phandle = <&pmu_system_controller>;
 694                 status = "disabled";
 695         };
 696
 697         hdmiphy: hdmiphy@145D0000 {
 698                 reg = <0x145D0000 0x20>;
 699         };
 700
 701         mixer: mixer@14450000 {
 702                 compatible = "samsung,exynos5420-mixer";
 703                 reg = <0x14450000 0x10000>;
 704                 interrupts = <0 94 0>;
 705                 clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>;
 706                 clock-names = "mixer", "sclk_hdmi";
 707         };
 708
 709         gsc_0: video-scaler@13e00000 {
 710                 compatible = "samsung,exynos5-gsc";
 711                 reg = <0x13e00000 0x1000>;
 712                 interrupts = <0 85 0>;
 713                 clocks = <&clock CLK_GSCL0>;
 714                 clock-names = "gscl";
 715                 samsung,power-domain = <&gsc_pd>;
 716         };
 717
 718         gsc_1: video-scaler@13e10000 {
 719                 compatible = "samsung,exynos5-gsc";
 720                 reg = <0x13e10000 0x1000>;
 721                 interrupts = <0 86 0>;
 722                 clocks = <&clock CLK_GSCL1>;
 723                 clock-names = "gscl";
 724                 samsung,power-domain = <&gsc_pd>;
 725         };
 726
 727         pmu_system_controller: system-controller@10040000 {
 728                 compatible = "samsung,exynos5420-pmu", "syscon";
 729                 reg = <0x10040000 0x5000>;
 730         };
 731
 732         sysreg_system_controller: syscon@10050000 {
 733                 compatible = "samsung,exynos5-sysreg", "syscon";
 734                 reg = <0x10050000 0x5000>;
 735         };
 736
 737         tmu_cpu0: tmu@10060000 {
 738                 compatible = "samsung,exynos5420-tmu";
 739                 reg = <0x10060000 0x100>;
 740                 interrupts = <0 65 0>;
 741                 clocks = <&clock CLK_TMU>;
 742                 clock-names = "tmu_apbif";
 743         };
 744
 745         tmu_cpu1: tmu@10064000 {
 746                 compatible = "samsung,exynos5420-tmu";
 747                 reg = <0x10064000 0x100>;
 748                 interrupts = <0 183 0>;
 749                 clocks = <&clock CLK_TMU>;
 750                 clock-names = "tmu_apbif";
 751         };
 752
 753         tmu_cpu2: tmu@10068000 {
 754                 compatible = "samsung,exynos5420-tmu-ext-triminfo";
 755                 reg = <0x10068000 0x100>, <0x1006c000 0x4>;
 756                 interrupts = <0 184 0>;
 757                 clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
 758                 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 759         };
 760
 761         tmu_cpu3: tmu@1006c000 {
 762                 compatible = "samsung,exynos5420-tmu-ext-triminfo";
 763                 reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
 764                 interrupts = <0 185 0>;
 765                 clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
 766                 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 767         };
 768
 769         tmu_gpu: tmu@100a0000 {
 770                 compatible = "samsung,exynos5420-tmu-ext-triminfo";
 771                 reg = <0x100a0000 0x100>, <0x10068000 0x4>;
 772                 interrupts = <0 215 0>;
 773                 clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
 774                 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 775         };
 776
 777         watchdog: watchdog@101D0000 {
 778                 compatible = "samsung,exynos5420-wdt";
 779                 reg = <0x101D0000 0x100>;
 780                 interrupts = <0 42 0>;
 781                 clocks = <&clock CLK_WDT>;
 782                 clock-names = "watchdog";
 783                 samsung,syscon-phandle = <&pmu_system_controller>;
 784         };
 785
 786         sss: sss@10830000 {
 787                 compatible = "samsung,exynos4210-secss";
 788                 reg = <0x10830000 0x10000>;
 789                 interrupts = <0 112 0>;
 790                 clocks = <&clock CLK_SSS>;
 791                 clock-names = "secss";
 792         };
 793
 794         usbdrd3_0: usb@12000000 {
 795                 compatible = "samsung,exynos5250-dwusb3";
 796                 clocks = <&clock CLK_USBD300>;
 797                 clock-names = "usbdrd30";
 798                 #address-cells = <1>;
 799                 #size-cells = <1>;
 800                 ranges;
 801
 802                 dwc3 {
 803                         compatible = "snps,dwc3";
 804                         reg = <0x12000000 0x10000>;
 805                         interrupts = <0 72 0>;
 806                         phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
 807                         phy-names = "usb2-phy", "usb3-phy";
 808                 };
 809         };
 810
 811         usbdrd_phy0: phy@12100000 {
 812                 compatible = "samsung,exynos5420-usbdrd-phy";
 813                 reg = <0x12100000 0x100>;
 814                 clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
 815                 clock-names = "phy", "ref";
 816                 samsung,pmu-syscon = <&pmu_system_controller>;
 817                 #phy-cells = <1>;
 818         };
 819
 820         usbdrd3_1: usb@12400000 {
 821                 compatible = "samsung,exynos5250-dwusb3";
 822                 clocks = <&clock CLK_USBD301>;
 823                 clock-names = "usbdrd30";
 824                 #address-cells = <1>;
 825                 #size-cells = <1>;
 826                 ranges;
 827
 828                 dwc3 {
 829                         compatible = "snps,dwc3";
 830                         reg = <0x12400000 0x10000>;
 831                         interrupts = <0 73 0>;
 832                         phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>;
 833                         phy-names = "usb2-phy", "usb3-phy";
 834                 };
 835         };
 836
 837         usbdrd_phy1: phy@12500000 {
 838                 compatible = "samsung,exynos5420-usbdrd-phy";
 839                 reg = <0x12500000 0x100>;
 840                 clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
 841                 clock-names = "phy", "ref";
 842                 samsung,pmu-syscon = <&pmu_system_controller>;
 843                 #phy-cells = <1>;
 844         };
 845
 846         usbhost2: usb@12110000 {
 847                 compatible = "samsung,exynos4210-ehci";
 848                 reg = <0x12110000 0x100>;
 849                 interrupts = <0 71 0>;
 850
 851                 clocks = <&clock CLK_USBH20>;
 852                 clock-names = "usbhost";
 853                 #address-cells = <1>;
 854                 #size-cells = <0>;
 855                 port@0 {
 856                         reg = <0>;
 857                         phys = <&usb2_phy 1>;
 858                 };
 859         };
 860
 861         usbhost1: usb@12120000 {
 862                 compatible = "samsung,exynos4210-ohci";
 863                 reg = <0x12120000 0x100>;
 864                 interrupts = <0 71 0>;
 865
 866                 clocks = <&clock CLK_USBH20>;
 867                 clock-names = "usbhost";
 868                 #address-cells = <1>;
 869                 #size-cells = <0>;
 870                 port@0 {
 871                         reg = <0>;
 872                         phys = <&usb2_phy 1>;
 873                 };
 874         };
 875
 876         usb2_phy: phy@12130000 {
 877                 compatible = "samsung,exynos5250-usb2-phy";
 878                 reg = <0x12130000 0x100>;
 879                 clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
 880                 clock-names = "phy", "ref";
 881                 #phy-cells = <1>;
 882                 samsung,sysreg-phandle = <&sysreg_system_controller>;
 883                 samsung,pmureg-phandle = <&pmu_system_controller>;
 884         };
 885 };