arch/arm/boot/dts/exynos5420-arndale-octa.dts

   1 /*
   2  * Samsung's Exynos5420 based Arndale Octa board device tree source
   3  *
   4  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 /dts-v1/;
  13 #include "exynos5420.dtsi"
  14
  15 / {
  16         model = "Insignal Arndale Octa evaluation board based on EXYNOS5420";
  17         compatible = "insignal,arndale-octa", "samsung,exynos5420";
  18
  19         memory {
  20                 reg = <0x20000000 0x80000000>;
  21         };
  22
  23         chosen {
  24                 bootargs = "console=ttySAC3,115200";
  25         };
  26
  27         fixed-rate-clocks {
  28                 oscclk {
  29                         compatible = "samsung,exynos5420-oscclk";
  30                         clock-frequency = <24000000>;
  31                 };
  32         };
  33
  34         mmc@12200000 {
  35                 status = "okay";
  36                 broken-cd;
  37                 supports-highspeed;
  38                 card-detect-delay = <200>;
  39                 samsung,dw-mshc-ciu-div = <3>;
  40                 samsung,dw-mshc-sdr-timing = <0 4>;
  41                 samsung,dw-mshc-ddr-timing = <0 2>;
  42                 pinctrl-names = "default";
  43                 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
  44
  45                 slot@0 {
  46                         reg = <0>;
  47                         bus-width = <8>;
  48                 };
  49         };
  50
  51         mmc@12220000 {
  52                 status = "okay";
  53                 supports-highspeed;
  54                 card-detect-delay = <200>;
  55                 samsung,dw-mshc-ciu-div = <3>;
  56                 samsung,dw-mshc-sdr-timing = <2 3>;
  57                 samsung,dw-mshc-ddr-timing = <1 2>;
  58                 pinctrl-names = "default";
  59                 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
  60
  61                 slot@0 {
  62                         reg = <0>;
  63                         bus-width = <4>;
  64                 };
  65         };
  66 };