arch/arm/boot/dts/exynos5260.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * SAMSUNG EXYNOS5260 SoC device tree source
   4  *
   5  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   6  *              http://www.samsung.com
   7  */
   8
   9 #include <dt-bindings/clock/exynos5260-clk.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/interrupt-controller/irq.h>
  12
  13 / {
  14         compatible = "samsung,exynos5260", "samsung,exynos5";
  15         interrupt-parent = <&gic>;
  16         #address-cells = <1>;
  17         #size-cells = <1>;
  18
  19         aliases {
  20                 pinctrl0 = &pinctrl_0;
  21                 pinctrl1 = &pinctrl_1;
  22                 pinctrl2 = &pinctrl_2;
  23                 serial0 = &uart0;
  24                 serial1 = &uart1;
  25                 serial2 = &uart2;
  26                 serial3 = &uart3;
  27         };
  28
  29         cpus {
  30                 #address-cells = <1>;
  31                 #size-cells = <0>;
  32
  33                 cpu@0 {
  34                         device_type = "cpu";
  35                         compatible = "arm,cortex-a15";
  36                         reg = <0x0>;
  37                         cci-control-port = <&cci_control1>;
  38                 };
  39
  40                 cpu@1 {
  41                         device_type = "cpu";
  42                         compatible = "arm,cortex-a15";
  43                         reg = <0x1>;
  44                         cci-control-port = <&cci_control1>;
  45                 };
  46
  47                 cpu@100 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a7";
  50                         reg = <0x100>;
  51                         cci-control-port = <&cci_control0>;
  52                 };
  53
  54                 cpu@101 {
  55                         device_type = "cpu";
  56                         compatible = "arm,cortex-a7";
  57                         reg = <0x101>;
  58                         cci-control-port = <&cci_control0>;
  59                 };
  60
  61                 cpu@102 {
  62                         device_type = "cpu";
  63                         compatible = "arm,cortex-a7";
  64                         reg = <0x102>;
  65                         cci-control-port = <&cci_control0>;
  66                 };
  67
  68                 cpu@103 {
  69                         device_type = "cpu";
  70                         compatible = "arm,cortex-a7";
  71                         reg = <0x103>;
  72                         cci-control-port = <&cci_control0>;
  73                 };
  74         };
  75
  76         soc: soc {
  77                 compatible = "simple-bus";
  78                 #address-cells = <1>;
  79                 #size-cells = <1>;
  80                 ranges;
  81
  82                 clock_top: clock-controller@10010000 {
  83                         compatible = "samsung,exynos5260-clock-top";
  84                         reg = <0x10010000 0x10000>;
  85                         #clock-cells = <1>;
  86                 };
  87
  88                 clock_peri: clock-controller@10200000 {
  89                         compatible = "samsung,exynos5260-clock-peri";
  90                         reg = <0x10200000 0x10000>;
  91                         #clock-cells = <1>;
  92                 };
  93
  94                 clock_egl: clock-controller@10600000 {
  95                         compatible = "samsung,exynos5260-clock-egl";
  96                         reg = <0x10600000 0x10000>;
  97                         #clock-cells = <1>;
  98                 };
  99
 100                 clock_kfc: clock-controller@10700000 {
 101                         compatible = "samsung,exynos5260-clock-kfc";
 102                         reg = <0x10700000 0x10000>;
 103                         #clock-cells = <1>;
 104                 };
 105
 106                 clock_g2d: clock-controller@10a00000 {
 107                         compatible = "samsung,exynos5260-clock-g2d";
 108                         reg = <0x10A00000 0x10000>;
 109                         #clock-cells = <1>;
 110                 };
 111
 112                 clock_mif: clock-controller@10ce0000 {
 113                         compatible = "samsung,exynos5260-clock-mif";
 114                         reg = <0x10CE0000 0x10000>;
 115                         #clock-cells = <1>;
 116                 };
 117
 118                 clock_mfc: clock-controller@11090000 {
 119                         compatible = "samsung,exynos5260-clock-mfc";
 120                         reg = <0x11090000 0x10000>;
 121                         #clock-cells = <1>;
 122                 };
 123
 124                 clock_g3d: clock-controller@11830000 {
 125                         compatible = "samsung,exynos5260-clock-g3d";
 126                         reg = <0x11830000 0x10000>;
 127                         #clock-cells = <1>;
 128                 };
 129
 130                 clock_fsys: clock-controller@122e0000 {
 131                         compatible = "samsung,exynos5260-clock-fsys";
 132                         reg = <0x122E0000 0x10000>;
 133                         #clock-cells = <1>;
 134                 };
 135
 136                 clock_aud: clock-controller@128c0000 {
 137                         compatible = "samsung,exynos5260-clock-aud";
 138                         reg = <0x128C0000 0x10000>;
 139                         #clock-cells = <1>;
 140                 };
 141
 142                 clock_isp: clock-controller@133c0000 {
 143                         compatible = "samsung,exynos5260-clock-isp";
 144                         reg = <0x133C0000 0x10000>;
 145                         #clock-cells = <1>;
 146                 };
 147
 148                 clock_gscl: clock-controller@13f00000 {
 149                         compatible = "samsung,exynos5260-clock-gscl";
 150                         reg = <0x13F00000 0x10000>;
 151                         #clock-cells = <1>;
 152                 };
 153
 154                 clock_disp: clock-controller@14550000 {
 155                         compatible = "samsung,exynos5260-clock-disp";
 156                         reg = <0x14550000 0x10000>;
 157                         #clock-cells = <1>;
 158                 };
 159
 160                 gic: interrupt-controller@10481000 {
 161                         compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
 162                         #interrupt-cells = <3>;
 163                         #address-cells = <0>;
 164                         #size-cells = <0>;
 165                         interrupt-controller;
 166                         reg = <0x10481000 0x1000>,
 167                                 <0x10482000 0x2000>,
 168                                 <0x10484000 0x2000>,
 169                                 <0x10486000 0x2000>;
 170                         interrupts = <GIC_PPI 9
 171                                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 172                 };
 173
 174                 chipid: chipid@10000000 {
 175                         compatible = "samsung,exynos4210-chipid";
 176                         reg = <0x10000000 0x100>;
 177                 };
 178
 179                 mct: mct@100b0000 {
 180                         compatible = "samsung,exynos4210-mct";
 181                         reg = <0x100B0000 0x1000>;
 182                         clocks = <&fin_pll>, <&clock_peri PERI_CLK_MCT>;
 183                         clock-names = "fin_pll", "mct";
 184                         interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 185                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 186                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 187                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 188                                      <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 189                                      <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 190                                      <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
 191                                      <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
 192                                      <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
 193                                      <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
 194                                      <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 195                                      <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
 196                 };
 197
 198                 cci: cci@10f00000 {
 199                         compatible = "arm,cci-400";
 200                         #address-cells = <1>;
 201                         #size-cells = <1>;
 202                         reg = <0x10F00000 0x1000>;
 203                         ranges = <0x0 0x10F00000 0x6000>;
 204
 205                         cci_control0: slave-if@4000 {
 206                                 compatible = "arm,cci-400-ctrl-if";
 207                                 interface-type = "ace";
 208                                 reg = <0x4000 0x1000>;
 209                         };
 210
 211                         cci_control1: slave-if@5000 {
 212                                 compatible = "arm,cci-400-ctrl-if";
 213                                 interface-type = "ace";
 214                                 reg = <0x5000 0x1000>;
 215                         };
 216                 };
 217
 218                 pinctrl_0: pinctrl@11600000 {
 219                         compatible = "samsung,exynos5260-pinctrl";
 220                         reg = <0x11600000 0x1000>;
 221                         interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 222
 223                         wakeup-interrupt-controller {
 224                                 compatible = "samsung,exynos4210-wakeup-eint";
 225                                 interrupt-parent = <&gic>;
 226                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 227                         };
 228                 };
 229
 230                 pinctrl_1: pinctrl@12290000 {
 231                         compatible = "samsung,exynos5260-pinctrl";
 232                         reg = <0x12290000 0x1000>;
 233                         interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
 234                 };
 235
 236                 pinctrl_2: pinctrl@128b0000 {
 237                         compatible = "samsung,exynos5260-pinctrl";
 238                         reg = <0x128B0000 0x1000>;
 239                         interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
 240                 };
 241
 242                 pmu_system_controller: system-controller@10d50000 {
 243                         compatible = "samsung,exynos5260-pmu", "syscon";
 244                         reg = <0x10D50000 0x10000>;
 245                 };
 246
 247                 uart0: serial@12c00000 {
 248                         compatible = "samsung,exynos4210-uart";
 249                         reg = <0x12C00000 0x100>;
 250                         interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
 251                         clocks = <&clock_peri PERI_CLK_UART0>, <&clock_peri PERI_SCLK_UART0>;
 252                         clock-names = "uart", "clk_uart_baud0";
 253                         status = "disabled";
 254                 };
 255
 256                 uart1: serial@12c10000 {
 257                         compatible = "samsung,exynos4210-uart";
 258                         reg = <0x12C10000 0x100>;
 259                         interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
 260                         clocks = <&clock_peri PERI_CLK_UART1>, <&clock_peri PERI_SCLK_UART1>;
 261                         clock-names = "uart", "clk_uart_baud0";
 262                         status = "disabled";
 263                 };
 264
 265                 uart2: serial@12c20000 {
 266                         compatible = "samsung,exynos4210-uart";
 267                         reg = <0x12C20000 0x100>;
 268                         interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
 269                         clocks = <&clock_peri PERI_CLK_UART2>, <&clock_peri PERI_SCLK_UART2>;
 270                         clock-names = "uart", "clk_uart_baud0";
 271                         status = "disabled";
 272                 };
 273
 274                 uart3: serial@12860000 {
 275                         compatible = "samsung,exynos4210-uart";
 276                         reg = <0x12860000 0x100>;
 277                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 278                         clocks = <&clock_aud AUD_CLK_AUD_UART>, <&clock_aud AUD_SCLK_AUD_UART>;
 279                         clock-names = "uart", "clk_uart_baud0";
 280                         status = "disabled";
 281                 };
 282
 283                 mmc_0: mmc@12140000 {
 284                         compatible = "samsung,exynos5250-dw-mshc";
 285                         reg = <0x12140000 0x2000>;
 286                         interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
 287                         #address-cells = <1>;
 288                         #size-cells = <0>;
 289                         clocks = <&clock_fsys FSYS_CLK_MMC0>, <&clock_top TOP_SCLK_MMC0>;
 290                         clock-names = "biu", "ciu";
 291                         fifo-depth = <64>;
 292                         status = "disabled";
 293                 };
 294
 295                 mmc_1: mmc@12150000 {
 296                         compatible = "samsung,exynos5250-dw-mshc";
 297                         reg = <0x12150000 0x2000>;
 298                         interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
 299                         #address-cells = <1>;
 300                         #size-cells = <0>;
 301                         clocks = <&clock_fsys FSYS_CLK_MMC1>, <&clock_top TOP_SCLK_MMC1>;
 302                         clock-names = "biu", "ciu";
 303                         fifo-depth = <64>;
 304                         status = "disabled";
 305                 };
 306
 307                 mmc_2: mmc@12160000 {
 308                         compatible = "samsung,exynos5250-dw-mshc";
 309                         reg = <0x12160000 0x2000>;
 310                         interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
 311                         #address-cells = <1>;
 312                         #size-cells = <0>;
 313                         clocks = <&clock_fsys FSYS_CLK_MMC2>, <&clock_top TOP_SCLK_MMC2>;
 314                         clock-names = "biu", "ciu";
 315                         fifo-depth = <64>;
 316                         status = "disabled";
 317                 };
 318         };
 319 };
 320
 321 #include "exynos5260-pinctrl.dtsi"