arch/arm/boot/dts/exynos4210.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Samsung's Exynos4210 SoC device tree source
   4  *
   5  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   6  *              http://www.samsung.com
   7  * Copyright (c) 2010-2011 Linaro Ltd.
   8  *              www.linaro.org
   9  *
  10  * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
  11  * based board files can include this file and provide values for board specfic
  12  * bindings.
  13  *
  14  * Note: This file does not include device nodes for all the controllers in
  15  * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
  16  * nodes can be added to this file.
  17  */
  18
  19 #include "exynos4.dtsi"
  20 #include "exynos4-cpu-thermal.dtsi"
  21
  22 / {
  23         compatible = "samsung,exynos4210", "samsung,exynos4";
  24
  25         aliases {
  26                 pinctrl0 = &pinctrl_0;
  27                 pinctrl1 = &pinctrl_1;
  28                 pinctrl2 = &pinctrl_2;
  29         };
  30
  31         cpus {
  32                 #address-cells = <1>;
  33                 #size-cells = <0>;
  34
  35                 cpu0: cpu@900 {
  36                         device_type = "cpu";
  37                         compatible = "arm,cortex-a9";
  38                         reg = <0x900>;
  39                         clocks = <&clock CLK_ARM_CLK>;
  40                         clock-names = "cpu";
  41                         clock-latency = <160000>;
  42
  43                         operating-points = <
  44                                 1200000 1250000
  45                                 1000000 1150000
  46                                 800000  1075000
  47                                 500000  975000
  48                                 400000  975000
  49                                 200000  950000
  50                         >;
  51                         #cooling-cells = <2>; /* min followed by max */
  52                 };
  53
  54                 cpu@901 {
  55                         device_type = "cpu";
  56                         compatible = "arm,cortex-a9";
  57                         reg = <0x901>;
  58                 };
  59         };
  60
  61         soc: soc {
  62                 sysram: sysram@2020000 {
  63                         compatible = "mmio-sram";
  64                         reg = <0x02020000 0x20000>;
  65                         #address-cells = <1>;
  66                         #size-cells = <1>;
  67                         ranges = <0 0x02020000 0x20000>;
  68
  69                         smp-sysram@0 {
  70                                 compatible = "samsung,exynos4210-sysram";
  71                                 reg = <0x0 0x1000>;
  72                         };
  73
  74                         smp-sysram@1f000 {
  75                                 compatible = "samsung,exynos4210-sysram-ns";
  76                                 reg = <0x1f000 0x1000>;
  77                         };
  78                 };
  79
  80                 pd_lcd1: lcd1-power-domain@10023ca0 {
  81                         compatible = "samsung,exynos4210-pd";
  82                         reg = <0x10023CA0 0x20>;
  83                         #power-domain-cells = <0>;
  84                         label = "LCD1";
  85                 };
  86
  87                 l2c: l2-cache-controller@10502000 {
  88                         compatible = "arm,pl310-cache";
  89                         reg = <0x10502000 0x1000>;
  90                         cache-unified;
  91                         cache-level = <2>;
  92                         arm,tag-latency = <2 2 1>;
  93                         arm,data-latency = <2 2 1>;
  94                 };
  95
  96                 mct: mct@10050000 {
  97                         compatible = "samsung,exynos4210-mct";
  98                         reg = <0x10050000 0x800>;
  99                         interrupt-parent = <&mct_map>;
 100                         interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
 101                         clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
 102                         clock-names = "fin_pll", "mct";
 103
 104                         mct_map: mct-map {
 105                                 #interrupt-cells = <1>;
 106                                 #address-cells = <0>;
 107                                 #size-cells = <0>;
 108                                 interrupt-map =
 109                                         <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>,
 110                                         <1 &gic 0 69 IRQ_TYPE_LEVEL_HIGH>,
 111                                         <2 &combiner 12 6>,
 112                                         <3 &combiner 12 7>,
 113                                         <4 &gic 0 42 IRQ_TYPE_LEVEL_HIGH>,
 114                                         <5 &gic 0 48 IRQ_TYPE_LEVEL_HIGH>;
 115                         };
 116                 };
 117
 118                 watchdog: watchdog@10060000 {
 119                         compatible = "samsung,s3c6410-wdt";
 120                         reg = <0x10060000 0x100>;
 121                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 122                         clocks = <&clock CLK_WDT>;
 123                         clock-names = "watchdog";
 124                 };
 125
 126                 clock: clock-controller@10030000 {
 127                         compatible = "samsung,exynos4210-clock";
 128                         reg = <0x10030000 0x20000>;
 129                         #clock-cells = <1>;
 130                 };
 131
 132                 pinctrl_0: pinctrl@11400000 {
 133                         compatible = "samsung,exynos4210-pinctrl";
 134                         reg = <0x11400000 0x1000>;
 135                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 136                 };
 137
 138                 pinctrl_1: pinctrl@11000000 {
 139                         compatible = "samsung,exynos4210-pinctrl";
 140                         reg = <0x11000000 0x1000>;
 141                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 142
 143                         wakup_eint: wakeup-interrupt-controller {
 144                                 compatible = "samsung,exynos4210-wakeup-eint";
 145                                 interrupt-parent = <&gic>;
 146                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 147                         };
 148                 };
 149
 150                 pinctrl_2: pinctrl@3860000 {
 151                         compatible = "samsung,exynos4210-pinctrl";
 152                         reg = <0x03860000 0x1000>;
 153                 };
 154
 155                 g2d: g2d@12800000 {
 156                         compatible = "samsung,s5pv210-g2d";
 157                         reg = <0x12800000 0x1000>;
 158                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 159                         clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
 160                         clock-names = "sclk_fimg2d", "fimg2d";
 161                         power-domains = <&pd_lcd0>;
 162                         iommus = <&sysmmu_g2d>;
 163                 };
 164
 165                 ppmu_acp: ppmu_acp@10ae0000 {
 166                         compatible = "samsung,exynos-ppmu";
 167                         reg = <0x10ae0000 0x2000>;
 168                         status = "disabled";
 169                 };
 170
 171                 ppmu_lcd1: ppmu_lcd1@12240000 {
 172                         compatible = "samsung,exynos-ppmu";
 173                         reg = <0x12240000 0x2000>;
 174                         clocks = <&clock CLK_PPMULCD1>;
 175                         clock-names = "ppmu";
 176                         status = "disabled";
 177                 };
 178
 179                 sysmmu_g2d: sysmmu@12a20000 {
 180                         compatible = "samsung,exynos-sysmmu";
 181                         reg = <0x12A20000 0x1000>;
 182                         interrupt-parent = <&combiner>;
 183                         interrupts = <4 7>;
 184                         clock-names = "sysmmu", "master";
 185                         clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
 186                         power-domains = <&pd_lcd0>;
 187                         #iommu-cells = <0>;
 188                 };
 189
 190                 sysmmu_fimd1: sysmmu@12220000 {
 191                         compatible = "samsung,exynos-sysmmu";
 192                         interrupt-parent = <&combiner>;
 193                         reg = <0x12220000 0x1000>;
 194                         interrupts = <5 3>;
 195                         clock-names = "sysmmu", "master";
 196                         clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
 197                         power-domains = <&pd_lcd1>;
 198                         #iommu-cells = <0>;
 199                 };
 200
 201                 bus_dmc: bus_dmc {
 202                         compatible = "samsung,exynos-bus";
 203                         clocks = <&clock CLK_DIV_DMC>;
 204                         clock-names = "bus";
 205                         operating-points-v2 = <&bus_dmc_opp_table>;
 206                         status = "disabled";
 207                 };
 208
 209                 bus_acp: bus_acp {
 210                         compatible = "samsung,exynos-bus";
 211                         clocks = <&clock CLK_DIV_ACP>;
 212                         clock-names = "bus";
 213                         operating-points-v2 = <&bus_acp_opp_table>;
 214                         status = "disabled";
 215                 };
 216
 217                 bus_peri: bus_peri {
 218                         compatible = "samsung,exynos-bus";
 219                         clocks = <&clock CLK_ACLK100>;
 220                         clock-names = "bus";
 221                         operating-points-v2 = <&bus_peri_opp_table>;
 222                         status = "disabled";
 223                 };
 224
 225                 bus_fsys: bus_fsys {
 226                         compatible = "samsung,exynos-bus";
 227                         clocks = <&clock CLK_ACLK133>;
 228                         clock-names = "bus";
 229                         operating-points-v2 = <&bus_fsys_opp_table>;
 230                         status = "disabled";
 231                 };
 232
 233                 bus_display: bus_display {
 234                         compatible = "samsung,exynos-bus";
 235                         clocks = <&clock CLK_ACLK160>;
 236                         clock-names = "bus";
 237                         operating-points-v2 = <&bus_display_opp_table>;
 238                         status = "disabled";
 239                 };
 240
 241                 bus_lcd0: bus_lcd0 {
 242                         compatible = "samsung,exynos-bus";
 243                         clocks = <&clock CLK_ACLK200>;
 244                         clock-names = "bus";
 245                         operating-points-v2 = <&bus_leftbus_opp_table>;
 246                         status = "disabled";
 247                 };
 248
 249                 bus_leftbus: bus_leftbus {
 250                         compatible = "samsung,exynos-bus";
 251                         clocks = <&clock CLK_DIV_GDL>;
 252                         clock-names = "bus";
 253                         operating-points-v2 = <&bus_leftbus_opp_table>;
 254                         status = "disabled";
 255                 };
 256
 257                 bus_rightbus: bus_rightbus {
 258                         compatible = "samsung,exynos-bus";
 259                         clocks = <&clock CLK_DIV_GDR>;
 260                         clock-names = "bus";
 261                         operating-points-v2 = <&bus_leftbus_opp_table>;
 262                         status = "disabled";
 263                 };
 264
 265                 bus_mfc: bus_mfc {
 266                         compatible = "samsung,exynos-bus";
 267                         clocks = <&clock CLK_SCLK_MFC>;
 268                         clock-names = "bus";
 269                         operating-points-v2 = <&bus_leftbus_opp_table>;
 270                         status = "disabled";
 271                 };
 272
 273                 bus_dmc_opp_table: opp_table1 {
 274                         compatible = "operating-points-v2";
 275                         opp-shared;
 276
 277                         opp-134000000 {
 278                                 opp-hz = /bits/ 64 <134000000>;
 279                                 opp-microvolt = <1025000>;
 280                         };
 281                         opp-267000000 {
 282                                 opp-hz = /bits/ 64 <267000000>;
 283                                 opp-microvolt = <1050000>;
 284                         };
 285                         opp-400000000 {
 286                                 opp-hz = /bits/ 64 <400000000>;
 287                                 opp-microvolt = <1150000>;
 288                         };
 289                 };
 290
 291                 bus_acp_opp_table: opp_table2 {
 292                         compatible = "operating-points-v2";
 293                         opp-shared;
 294
 295                         opp-134000000 {
 296                                 opp-hz = /bits/ 64 <134000000>;
 297                         };
 298                         opp-160000000 {
 299                                 opp-hz = /bits/ 64 <160000000>;
 300                         };
 301                         opp-200000000 {
 302                                 opp-hz = /bits/ 64 <200000000>;
 303                         };
 304                 };
 305
 306                 bus_peri_opp_table: opp_table3 {
 307                         compatible = "operating-points-v2";
 308                         opp-shared;
 309
 310                         opp-5000000 {
 311                                 opp-hz = /bits/ 64 <5000000>;
 312                         };
 313                         opp-100000000 {
 314                                 opp-hz = /bits/ 64 <100000000>;
 315                         };
 316                 };
 317
 318                 bus_fsys_opp_table: opp_table4 {
 319                         compatible = "operating-points-v2";
 320                         opp-shared;
 321
 322                         opp-10000000 {
 323                                 opp-hz = /bits/ 64 <10000000>;
 324                         };
 325                         opp-134000000 {
 326                                 opp-hz = /bits/ 64 <134000000>;
 327                         };
 328                 };
 329
 330                 bus_display_opp_table: opp_table5 {
 331                         compatible = "operating-points-v2";
 332                         opp-shared;
 333
 334                         opp-100000000 {
 335                                 opp-hz = /bits/ 64 <100000000>;
 336                         };
 337                         opp-134000000 {
 338                                 opp-hz = /bits/ 64 <134000000>;
 339                         };
 340                         opp-160000000 {
 341                                 opp-hz = /bits/ 64 <160000000>;
 342                         };
 343                 };
 344
 345                 bus_leftbus_opp_table: opp_table6 {
 346                         compatible = "operating-points-v2";
 347                         opp-shared;
 348
 349                         opp-100000000 {
 350                                 opp-hz = /bits/ 64 <100000000>;
 351                         };
 352                         opp-160000000 {
 353                                 opp-hz = /bits/ 64 <160000000>;
 354                         };
 355                         opp-200000000 {
 356                                 opp-hz = /bits/ 64 <200000000>;
 357                         };
 358                 };
 359         };
 360
 361         thermal-zones {
 362                 cpu_thermal: cpu-thermal {
 363                         polling-delay-passive = <0>;
 364                         polling-delay = <0>;
 365                         thermal-sensors = <&tmu 0>;
 366
 367                         trips {
 368                                 cpu_alert0: cpu-alert-0 {
 369                                 temperature = <85000>; /* millicelsius */
 370                                 };
 371                                 cpu_alert1: cpu-alert-1 {
 372                                 temperature = <100000>; /* millicelsius */
 373                                 };
 374                                 cpu_alert2: cpu-alert-2 {
 375                                 temperature = <110000>; /* millicelsius */
 376                                 };
 377                         };
 378                 };
 379         };
 380 };
 381
 382 &gic {
 383         cpu-offset = <0x8000>;
 384 };
 385
 386 &camera {
 387         clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
 388                  <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
 389         clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
 390 };
 391
 392 &combiner {
 393         samsung,combiner-nr = <16>;
 394         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 395                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 396                      <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 397                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 398                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 399                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 400                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 401                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 402                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 403                      <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 404                      <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
 405                      <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 406                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 407                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 408                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 409                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 410 };
 411
 412 &fimc_0 {
 413         samsung,pix-limits = <4224 8192 1920 4224>;
 414         samsung,mainscaler-ext;
 415         samsung,cam-if;
 416 };
 417
 418 &fimc_1 {
 419         samsung,pix-limits = <4224 8192 1920 4224>;
 420         samsung,mainscaler-ext;
 421         samsung,cam-if;
 422 };
 423
 424 &fimc_2 {
 425         samsung,pix-limits = <4224 8192 1920 4224>;
 426         samsung,mainscaler-ext;
 427         samsung,lcd-wb;
 428 };
 429
 430 &fimc_3 {
 431         samsung,pix-limits = <1920 8192 1366 1920>;
 432         samsung,rotators = <0>;
 433         samsung,mainscaler-ext;
 434         samsung,lcd-wb;
 435 };
 436
 437 &mdma1 {
 438         power-domains = <&pd_lcd0>;
 439 };
 440
 441 &mixer {
 442         clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer",
 443                       "sclk_mixer";
 444         clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
 445                  <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>,
 446                  <&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>;
 447 };
 448
 449 &pmu_system_controller {
 450         clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
 451                         "clkout4", "clkout8", "clkout9";
 452         clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
 453                 <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
 454                 <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>;
 455         #clock-cells = <1>;
 456 };
 457
 458 &rotator {
 459         power-domains = <&pd_lcd0>;
 460 };
 461
 462 &sysmmu_rotator {
 463         power-domains = <&pd_lcd0>;
 464 };
 465
 466 &tmu {
 467         compatible = "samsung,exynos4210-tmu";
 468         clocks = <&clock CLK_TMU_APBIF>;
 469         clock-names = "tmu_apbif";
 470         samsung,tmu_gain = <15>;
 471         samsung,tmu_reference_voltage = <7>;
 472 };
 473
 474 #include "exynos4210-pinctrl.dtsi"