arch/arm/boot/dts/exynos4.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Samsung's Exynos4 SoC series common device tree source
   4  *
   5  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   6  *              http://www.samsung.com
   7  * Copyright (c) 2010-2011 Linaro Ltd.
   8  *              www.linaro.org
   9  *
  10  * Samsung's Exynos4 SoC series device nodes are listed in this file.  Particular
  11  * SoCs from Exynos4 series can include this file and provide values for SoCs
  12  * specfic bindings.
  13  *
  14  * Note: This file does not include device nodes for all the controllers in
  15  * Exynos4 SoCs. As device tree coverage for Exynos4 increases, additional
  16  * nodes can be added to this file.
  17  */
  18
  19 #include <dt-bindings/clock/exynos4.h>
  20 #include <dt-bindings/clock/exynos-audss-clk.h>
  21 #include <dt-bindings/interrupt-controller/arm-gic.h>
  22 #include <dt-bindings/interrupt-controller/irq.h>
  23
  24 / {
  25         interrupt-parent = <&gic>;
  26         #address-cells = <1>;
  27         #size-cells = <1>;
  28
  29         aliases {
  30                 spi0 = &spi_0;
  31                 spi1 = &spi_1;
  32                 spi2 = &spi_2;
  33                 i2c0 = &i2c_0;
  34                 i2c1 = &i2c_1;
  35                 i2c2 = &i2c_2;
  36                 i2c3 = &i2c_3;
  37                 i2c4 = &i2c_4;
  38                 i2c5 = &i2c_5;
  39                 i2c6 = &i2c_6;
  40                 i2c7 = &i2c_7;
  41                 i2c8 = &i2c_8;
  42                 csis0 = &csis_0;
  43                 csis1 = &csis_1;
  44                 fimc0 = &fimc_0;
  45                 fimc1 = &fimc_1;
  46                 fimc2 = &fimc_2;
  47                 fimc3 = &fimc_3;
  48                 serial0 = &serial_0;
  49                 serial1 = &serial_1;
  50                 serial2 = &serial_2;
  51                 serial3 = &serial_3;
  52         };
  53
  54         soc: soc {
  55                 compatible = "simple-bus";
  56                 #address-cells = <1>;
  57                 #size-cells = <1>;
  58                 ranges;
  59
  60                 clock_audss: clock-controller@3810000 {
  61                         compatible = "samsung,exynos4210-audss-clock";
  62                         reg = <0x03810000 0x0C>;
  63                         #clock-cells = <1>;
  64                         clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
  65                                  <&clock CLK_SCLK_AUDIO0>,
  66                                  <&clock CLK_SCLK_AUDIO0>;
  67                         clock-names = "pll_ref", "pll_in", "sclk_audio",
  68                                       "sclk_pcm_in";
  69                 };
  70
  71                 i2s0: i2s@3830000 {
  72                         compatible = "samsung,s5pv210-i2s";
  73                         reg = <0x03830000 0x100>;
  74                         clocks = <&clock_audss EXYNOS_I2S_BUS>,
  75                                  <&clock_audss EXYNOS_DOUT_AUD_BUS>,
  76                                  <&clock_audss EXYNOS_SCLK_I2S>;
  77                         clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
  78                         #clock-cells = <1>;
  79                         clock-output-names = "i2s_cdclk0";
  80                         dmas = <&pdma0 12>, <&pdma0 11>, <&pdma0 10>;
  81                         dma-names = "tx", "rx", "tx-sec";
  82                         samsung,idma-addr = <0x03000000>;
  83                         #sound-dai-cells = <1>;
  84                         status = "disabled";
  85                 };
  86
  87                 chipid@10000000 {
  88                         compatible = "samsung,exynos4210-chipid";
  89                         reg = <0x10000000 0x100>;
  90                 };
  91
  92                 scu: snoop-control-unit@10500000 {
  93                         compatible = "arm,cortex-a9-scu";
  94                         reg = <0x10500000 0x2000>;
  95                 };
  96
  97                 memory-controller@12570000 {
  98                         compatible = "samsung,exynos4210-srom";
  99                         reg = <0x12570000 0x14>;
 100                 };
 101
 102                 mipi_phy: video-phy {
 103                         compatible = "samsung,s5pv210-mipi-video-phy";
 104                         #phy-cells = <1>;
 105                         syscon = <&pmu_system_controller>;
 106                 };
 107
 108                 pd_mfc: mfc-power-domain@10023c40 {
 109                         compatible = "samsung,exynos4210-pd";
 110                         reg = <0x10023C40 0x20>;
 111                         #power-domain-cells = <0>;
 112                         label = "MFC";
 113                 };
 114
 115                 pd_g3d: g3d-power-domain@10023c60 {
 116                         compatible = "samsung,exynos4210-pd";
 117                         reg = <0x10023C60 0x20>;
 118                         #power-domain-cells = <0>;
 119                         label = "G3D";
 120                 };
 121
 122                 pd_lcd0: lcd0-power-domain@10023c80 {
 123                         compatible = "samsung,exynos4210-pd";
 124                         reg = <0x10023C80 0x20>;
 125                         #power-domain-cells = <0>;
 126                         label = "LCD0";
 127                 };
 128
 129                 pd_tv: tv-power-domain@10023c20 {
 130                         compatible = "samsung,exynos4210-pd";
 131                         reg = <0x10023C20 0x20>;
 132                         #power-domain-cells = <0>;
 133                         power-domains = <&pd_lcd0>;
 134                         label = "TV";
 135                 };
 136
 137                 pd_cam: cam-power-domain@10023c00 {
 138                         compatible = "samsung,exynos4210-pd";
 139                         reg = <0x10023C00 0x20>;
 140                         #power-domain-cells = <0>;
 141                         label = "CAM";
 142                 };
 143
 144                 pd_gps: gps-power-domain@10023ce0 {
 145                         compatible = "samsung,exynos4210-pd";
 146                         reg = <0x10023CE0 0x20>;
 147                         #power-domain-cells = <0>;
 148                         label = "GPS";
 149                 };
 150
 151                 pd_gps_alive: gps-alive-power-domain@10023d00 {
 152                         compatible = "samsung,exynos4210-pd";
 153                         reg = <0x10023D00 0x20>;
 154                         #power-domain-cells = <0>;
 155                         label = "GPS alive";
 156                 };
 157
 158                 gic: interrupt-controller@10490000 {
 159                         compatible = "arm,cortex-a9-gic";
 160                         #interrupt-cells = <3>;
 161                         interrupt-controller;
 162                         reg = <0x10490000 0x10000>, <0x10480000 0x10000>;
 163                 };
 164
 165                 combiner: interrupt-controller@10440000 {
 166                         compatible = "samsung,exynos4210-combiner";
 167                         #interrupt-cells = <2>;
 168                         interrupt-controller;
 169                         reg = <0x10440000 0x1000>;
 170                 };
 171
 172                 pmu: pmu {
 173                         compatible = "arm,cortex-a9-pmu";
 174                         interrupt-parent = <&combiner>;
 175                         interrupts = <2 2>, <3 2>;
 176                 };
 177
 178                 sys_reg: syscon@10010000 {
 179                         compatible = "samsung,exynos4-sysreg", "syscon";
 180                         reg = <0x10010000 0x400>;
 181                 };
 182
 183                 pmu_system_controller: system-controller@10020000 {
 184                         compatible = "samsung,exynos4210-pmu", "syscon";
 185                         reg = <0x10020000 0x4000>;
 186                         interrupt-controller;
 187                         #interrupt-cells = <3>;
 188                         interrupt-parent = <&gic>;
 189                 };
 190
 191                 dsi_0: dsi@11c80000 {
 192                         compatible = "samsung,exynos4210-mipi-dsi";
 193                         reg = <0x11C80000 0x10000>;
 194                         interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 195                         power-domains = <&pd_lcd0>;
 196                         phys = <&mipi_phy 1>;
 197                         phy-names = "dsim";
 198                         clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>;
 199                         clock-names = "bus_clk", "sclk_mipi";
 200                         status = "disabled";
 201                         #address-cells = <1>;
 202                         #size-cells = <0>;
 203                 };
 204
 205                 camera: camera {
 206                         compatible = "samsung,fimc", "simple-bus";
 207                         status = "disabled";
 208                         #address-cells = <1>;
 209                         #size-cells = <1>;
 210                         #clock-cells = <1>;
 211                         clock-output-names = "cam_a_clkout", "cam_b_clkout";
 212                         ranges;
 213
 214                         fimc_0: fimc@11800000 {
 215                                 compatible = "samsung,exynos4210-fimc";
 216                                 reg = <0x11800000 0x1000>;
 217                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 218                                 clocks = <&clock CLK_FIMC0>,
 219                                          <&clock CLK_SCLK_FIMC0>;
 220                                 clock-names = "fimc", "sclk_fimc";
 221                                 power-domains = <&pd_cam>;
 222                                 samsung,sysreg = <&sys_reg>;
 223                                 iommus = <&sysmmu_fimc0>;
 224                                 status = "disabled";
 225                         };
 226
 227                         fimc_1: fimc@11810000 {
 228                                 compatible = "samsung,exynos4210-fimc";
 229                                 reg = <0x11810000 0x1000>;
 230                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 231                                 clocks = <&clock CLK_FIMC1>,
 232                                          <&clock CLK_SCLK_FIMC1>;
 233                                 clock-names = "fimc", "sclk_fimc";
 234                                 power-domains = <&pd_cam>;
 235                                 samsung,sysreg = <&sys_reg>;
 236                                 iommus = <&sysmmu_fimc1>;
 237                                 status = "disabled";
 238                         };
 239
 240                         fimc_2: fimc@11820000 {
 241                                 compatible = "samsung,exynos4210-fimc";
 242                                 reg = <0x11820000 0x1000>;
 243                                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 244                                 clocks = <&clock CLK_FIMC2>,
 245                                          <&clock CLK_SCLK_FIMC2>;
 246                                 clock-names = "fimc", "sclk_fimc";
 247                                 power-domains = <&pd_cam>;
 248                                 samsung,sysreg = <&sys_reg>;
 249                                 iommus = <&sysmmu_fimc2>;
 250                                 status = "disabled";
 251                         };
 252
 253                         fimc_3: fimc@11830000 {
 254                                 compatible = "samsung,exynos4210-fimc";
 255                                 reg = <0x11830000 0x1000>;
 256                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 257                                 clocks = <&clock CLK_FIMC3>,
 258                                          <&clock CLK_SCLK_FIMC3>;
 259                                 clock-names = "fimc", "sclk_fimc";
 260                                 power-domains = <&pd_cam>;
 261                                 samsung,sysreg = <&sys_reg>;
 262                                 iommus = <&sysmmu_fimc3>;
 263                                 status = "disabled";
 264                         };
 265
 266                         csis_0: csis@11880000 {
 267                                 compatible = "samsung,exynos4210-csis";
 268                                 reg = <0x11880000 0x4000>;
 269                                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 270                                 clocks = <&clock CLK_CSIS0>,
 271                                          <&clock CLK_SCLK_CSIS0>;
 272                                 clock-names = "csis", "sclk_csis";
 273                                 bus-width = <4>;
 274                                 power-domains = <&pd_cam>;
 275                                 phys = <&mipi_phy 0>;
 276                                 phy-names = "csis";
 277                                 status = "disabled";
 278                                 #address-cells = <1>;
 279                                 #size-cells = <0>;
 280                         };
 281
 282                         csis_1: csis@11890000 {
 283                                 compatible = "samsung,exynos4210-csis";
 284                                 reg = <0x11890000 0x4000>;
 285                                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 286                                 clocks = <&clock CLK_CSIS1>,
 287                                          <&clock CLK_SCLK_CSIS1>;
 288                                 clock-names = "csis", "sclk_csis";
 289                                 bus-width = <2>;
 290                                 power-domains = <&pd_cam>;
 291                                 phys = <&mipi_phy 2>;
 292                                 phy-names = "csis";
 293                                 status = "disabled";
 294                                 #address-cells = <1>;
 295                                 #size-cells = <0>;
 296                         };
 297                 };
 298
 299                 rtc: rtc@10070000 {
 300                         compatible = "samsung,s3c6410-rtc";
 301                         reg = <0x10070000 0x100>;
 302                         interrupt-parent = <&pmu_system_controller>;
 303                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
 304                                      <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 305                         clocks = <&clock CLK_RTC>;
 306                         clock-names = "rtc";
 307                         status = "disabled";
 308                 };
 309
 310                 keypad: keypad@100a0000 {
 311                         compatible = "samsung,s5pv210-keypad";
 312                         reg = <0x100A0000 0x100>;
 313                         interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 314                         clocks = <&clock CLK_KEYIF>;
 315                         clock-names = "keypad";
 316                         status = "disabled";
 317                 };
 318
 319                 sdhci_0: sdhci@12510000 {
 320                         compatible = "samsung,exynos4210-sdhci";
 321                         reg = <0x12510000 0x100>;
 322                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 323                         clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
 324                         clock-names = "hsmmc", "mmc_busclk.2";
 325                         status = "disabled";
 326                 };
 327
 328                 sdhci_1: sdhci@12520000 {
 329                         compatible = "samsung,exynos4210-sdhci";
 330                         reg = <0x12520000 0x100>;
 331                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 332                         clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
 333                         clock-names = "hsmmc", "mmc_busclk.2";
 334                         status = "disabled";
 335                 };
 336
 337                 sdhci_2: sdhci@12530000 {
 338                         compatible = "samsung,exynos4210-sdhci";
 339                         reg = <0x12530000 0x100>;
 340                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 341                         clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
 342                         clock-names = "hsmmc", "mmc_busclk.2";
 343                         status = "disabled";
 344                 };
 345
 346                 sdhci_3: sdhci@12540000 {
 347                         compatible = "samsung,exynos4210-sdhci";
 348                         reg = <0x12540000 0x100>;
 349                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 350                         clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
 351                         clock-names = "hsmmc", "mmc_busclk.2";
 352                         status = "disabled";
 353                 };
 354
 355                 exynos_usbphy: exynos-usbphy@125b0000 {
 356                         compatible = "samsung,exynos4210-usb2-phy";
 357                         reg = <0x125B0000 0x100>;
 358                         samsung,pmureg-phandle = <&pmu_system_controller>;
 359                         clocks = <&clock CLK_USB_DEVICE>, <&clock CLK_XUSBXTI>;
 360                         clock-names = "phy", "ref";
 361                         #phy-cells = <1>;
 362                         status = "disabled";
 363                 };
 364
 365                 hsotg: hsotg@12480000 {
 366                         compatible = "samsung,s3c6400-hsotg";
 367                         reg = <0x12480000 0x20000>;
 368                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 369                         clocks = <&clock CLK_USB_DEVICE>;
 370                         clock-names = "otg";
 371                         phys = <&exynos_usbphy 0>;
 372                         phy-names = "usb2-phy";
 373                         status = "disabled";
 374                 };
 375
 376                 ehci: ehci@12580000 {
 377                         compatible = "samsung,exynos4210-ehci";
 378                         reg = <0x12580000 0x100>;
 379                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 380                         clocks = <&clock CLK_USB_HOST>;
 381                         clock-names = "usbhost";
 382                         status = "disabled";
 383                         #address-cells = <1>;
 384                         #size-cells = <0>;
 385                         port@0 {
 386                                 reg = <0>;
 387                                 phys = <&exynos_usbphy 1>;
 388                                 status = "disabled";
 389                         };
 390                         port@1 {
 391                                 reg = <1>;
 392                                 phys = <&exynos_usbphy 2>;
 393                                 status = "disabled";
 394                         };
 395                         port@2 {
 396                                 reg = <2>;
 397                                 phys = <&exynos_usbphy 3>;
 398                                 status = "disabled";
 399                         };
 400                 };
 401
 402                 ohci: ohci@12590000 {
 403                         compatible = "samsung,exynos4210-ohci";
 404                         reg = <0x12590000 0x100>;
 405                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 406                         clocks = <&clock CLK_USB_HOST>;
 407                         clock-names = "usbhost";
 408                         status = "disabled";
 409                         #address-cells = <1>;
 410                         #size-cells = <0>;
 411                         port@0 {
 412                                 reg = <0>;
 413                                 phys = <&exynos_usbphy 1>;
 414                                 status = "disabled";
 415                         };
 416                 };
 417
 418                 i2s1: i2s@13960000 {
 419                         compatible = "samsung,s3c6410-i2s";
 420                         reg = <0x13960000 0x100>;
 421                         clocks = <&clock CLK_I2S1>;
 422                         clock-names = "iis";
 423                         #clock-cells = <1>;
 424                         clock-output-names = "i2s_cdclk1";
 425                         dmas = <&pdma1 12>, <&pdma1 11>;
 426                         dma-names = "tx", "rx";
 427                         #sound-dai-cells = <1>;
 428                         status = "disabled";
 429                 };
 430
 431                 i2s2: i2s@13970000 {
 432                         compatible = "samsung,s3c6410-i2s";
 433                         reg = <0x13970000 0x100>;
 434                         clocks = <&clock CLK_I2S2>;
 435                         clock-names = "iis";
 436                         #clock-cells = <1>;
 437                         clock-output-names = "i2s_cdclk2";
 438                         dmas = <&pdma0 14>, <&pdma0 13>;
 439                         dma-names = "tx", "rx";
 440                         #sound-dai-cells = <1>;
 441                         status = "disabled";
 442                 };
 443
 444                 mfc: codec@13400000 {
 445                         compatible = "samsung,mfc-v5";
 446                         reg = <0x13400000 0x10000>;
 447                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 448                         power-domains = <&pd_mfc>;
 449                         clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>;
 450                         clock-names = "mfc", "sclk_mfc";
 451                         iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
 452                         iommu-names = "left", "right";
 453                 };
 454
 455                 serial_0: serial@13800000 {
 456                         compatible = "samsung,exynos4210-uart";
 457                         reg = <0x13800000 0x100>;
 458                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 459                         clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
 460                         clock-names = "uart", "clk_uart_baud0";
 461                         dmas = <&pdma0 15>, <&pdma0 16>;
 462                         dma-names = "rx", "tx";
 463                         status = "disabled";
 464                 };
 465
 466                 serial_1: serial@13810000 {
 467                         compatible = "samsung,exynos4210-uart";
 468                         reg = <0x13810000 0x100>;
 469                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 470                         clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
 471                         clock-names = "uart", "clk_uart_baud0";
 472                         dmas = <&pdma1 15>, <&pdma1 16>;
 473                         dma-names = "rx", "tx";
 474                         status = "disabled";
 475                 };
 476
 477                 serial_2: serial@13820000 {
 478                         compatible = "samsung,exynos4210-uart";
 479                         reg = <0x13820000 0x100>;
 480                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 481                         clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
 482                         clock-names = "uart", "clk_uart_baud0";
 483                         dmas = <&pdma0 17>, <&pdma0 18>;
 484                         dma-names = "rx", "tx";
 485                         status = "disabled";
 486                 };
 487
 488                 serial_3: serial@13830000 {
 489                         compatible = "samsung,exynos4210-uart";
 490                         reg = <0x13830000 0x100>;
 491                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 492                         clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
 493                         clock-names = "uart", "clk_uart_baud0";
 494                         dmas = <&pdma1 17>, <&pdma1 18>;
 495                         dma-names = "rx", "tx";
 496                         status = "disabled";
 497                 };
 498
 499                 i2c_0: i2c@13860000 {
 500                         #address-cells = <1>;
 501                         #size-cells = <0>;
 502                         compatible = "samsung,s3c2440-i2c";
 503                         reg = <0x13860000 0x100>;
 504                         interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 505                         clocks = <&clock CLK_I2C0>;
 506                         clock-names = "i2c";
 507                         pinctrl-names = "default";
 508                         pinctrl-0 = <&i2c0_bus>;
 509                         status = "disabled";
 510                 };
 511
 512                 i2c_1: i2c@13870000 {
 513                         #address-cells = <1>;
 514                         #size-cells = <0>;
 515                         compatible = "samsung,s3c2440-i2c";
 516                         reg = <0x13870000 0x100>;
 517                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 518                         clocks = <&clock CLK_I2C1>;
 519                         clock-names = "i2c";
 520                         pinctrl-names = "default";
 521                         pinctrl-0 = <&i2c1_bus>;
 522                         status = "disabled";
 523                 };
 524
 525                 i2c_2: i2c@13880000 {
 526                         #address-cells = <1>;
 527                         #size-cells = <0>;
 528                         compatible = "samsung,s3c2440-i2c";
 529                         reg = <0x13880000 0x100>;
 530                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 531                         clocks = <&clock CLK_I2C2>;
 532                         clock-names = "i2c";
 533                         pinctrl-names = "default";
 534                         pinctrl-0 = <&i2c2_bus>;
 535                         status = "disabled";
 536                 };
 537
 538                 i2c_3: i2c@13890000 {
 539                         #address-cells = <1>;
 540                         #size-cells = <0>;
 541                         compatible = "samsung,s3c2440-i2c";
 542                         reg = <0x13890000 0x100>;
 543                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 544                         clocks = <&clock CLK_I2C3>;
 545                         clock-names = "i2c";
 546                         pinctrl-names = "default";
 547                         pinctrl-0 = <&i2c3_bus>;
 548                         status = "disabled";
 549                 };
 550
 551                 i2c_4: i2c@138a0000 {
 552                         #address-cells = <1>;
 553                         #size-cells = <0>;
 554                         compatible = "samsung,s3c2440-i2c";
 555                         reg = <0x138A0000 0x100>;
 556                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 557                         clocks = <&clock CLK_I2C4>;
 558                         clock-names = "i2c";
 559                         pinctrl-names = "default";
 560                         pinctrl-0 = <&i2c4_bus>;
 561                         status = "disabled";
 562                 };
 563
 564                 i2c_5: i2c@138b0000 {
 565                         #address-cells = <1>;
 566                         #size-cells = <0>;
 567                         compatible = "samsung,s3c2440-i2c";
 568                         reg = <0x138B0000 0x100>;
 569                         interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 570                         clocks = <&clock CLK_I2C5>;
 571                         clock-names = "i2c";
 572                         pinctrl-names = "default";
 573                         pinctrl-0 = <&i2c5_bus>;
 574                         status = "disabled";
 575                 };
 576
 577                 i2c_6: i2c@138c0000 {
 578                         #address-cells = <1>;
 579                         #size-cells = <0>;
 580                         compatible = "samsung,s3c2440-i2c";
 581                         reg = <0x138C0000 0x100>;
 582                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 583                         clocks = <&clock CLK_I2C6>;
 584                         clock-names = "i2c";
 585                         pinctrl-names = "default";
 586                         pinctrl-0 = <&i2c6_bus>;
 587                         status = "disabled";
 588                 };
 589
 590                 i2c_7: i2c@138d0000 {
 591                         #address-cells = <1>;
 592                         #size-cells = <0>;
 593                         compatible = "samsung,s3c2440-i2c";
 594                         reg = <0x138D0000 0x100>;
 595                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 596                         clocks = <&clock CLK_I2C7>;
 597                         clock-names = "i2c";
 598                         pinctrl-names = "default";
 599                         pinctrl-0 = <&i2c7_bus>;
 600                         status = "disabled";
 601                 };
 602
 603                 i2c_8: i2c@138e0000 {
 604                         #address-cells = <1>;
 605                         #size-cells = <0>;
 606                         compatible = "samsung,s3c2440-hdmiphy-i2c";
 607                         reg = <0x138E0000 0x100>;
 608                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 609                         clocks = <&clock CLK_I2C_HDMI>;
 610                         clock-names = "i2c";
 611                         status = "disabled";
 612
 613                         hdmi_i2c_phy: hdmiphy@38 {
 614                                 compatible = "exynos4210-hdmiphy";
 615                                 reg = <0x38>;
 616                         };
 617                 };
 618
 619                 spi_0: spi@13920000 {
 620                         compatible = "samsung,exynos4210-spi";
 621                         reg = <0x13920000 0x100>;
 622                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 623                         dmas = <&pdma0 7>, <&pdma0 6>;
 624                         dma-names = "tx", "rx";
 625                         #address-cells = <1>;
 626                         #size-cells = <0>;
 627                         clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
 628                         clock-names = "spi", "spi_busclk0";
 629                         pinctrl-names = "default";
 630                         pinctrl-0 = <&spi0_bus>;
 631                         status = "disabled";
 632                 };
 633
 634                 spi_1: spi@13930000 {
 635                         compatible = "samsung,exynos4210-spi";
 636                         reg = <0x13930000 0x100>;
 637                         interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 638                         dmas = <&pdma1 7>, <&pdma1 6>;
 639                         dma-names = "tx", "rx";
 640                         #address-cells = <1>;
 641                         #size-cells = <0>;
 642                         clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
 643                         clock-names = "spi", "spi_busclk0";
 644                         pinctrl-names = "default";
 645                         pinctrl-0 = <&spi1_bus>;
 646                         status = "disabled";
 647                 };
 648
 649                 spi_2: spi@13940000 {
 650                         compatible = "samsung,exynos4210-spi";
 651                         reg = <0x13940000 0x100>;
 652                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 653                         dmas = <&pdma0 9>, <&pdma0 8>;
 654                         dma-names = "tx", "rx";
 655                         #address-cells = <1>;
 656                         #size-cells = <0>;
 657                         clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
 658                         clock-names = "spi", "spi_busclk0";
 659                         pinctrl-names = "default";
 660                         pinctrl-0 = <&spi2_bus>;
 661                         status = "disabled";
 662                 };
 663
 664                 pwm: pwm@139d0000 {
 665                         compatible = "samsung,exynos4210-pwm";
 666                         reg = <0x139D0000 0x1000>;
 667                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
 668                                      <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
 669                                      <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
 670                                      <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 671                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 672                         clocks = <&clock CLK_PWM>;
 673                         clock-names = "timers";
 674                         #pwm-cells = <3>;
 675                         status = "disabled";
 676                 };
 677
 678                 amba {
 679                         #address-cells = <1>;
 680                         #size-cells = <1>;
 681                         compatible = "simple-bus";
 682                         interrupt-parent = <&gic>;
 683                         ranges;
 684
 685                         pdma0: pdma@12680000 {
 686                                 compatible = "arm,pl330", "arm,primecell";
 687                                 reg = <0x12680000 0x1000>;
 688                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 689                                 clocks = <&clock CLK_PDMA0>;
 690                                 clock-names = "apb_pclk";
 691                                 #dma-cells = <1>;
 692                                 #dma-channels = <8>;
 693                                 #dma-requests = <32>;
 694                         };
 695
 696                         pdma1: pdma@12690000 {
 697                                 compatible = "arm,pl330", "arm,primecell";
 698                                 reg = <0x12690000 0x1000>;
 699                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 700                                 clocks = <&clock CLK_PDMA1>;
 701                                 clock-names = "apb_pclk";
 702                                 #dma-cells = <1>;
 703                                 #dma-channels = <8>;
 704                                 #dma-requests = <32>;
 705                         };
 706
 707                         mdma1: mdma@12850000 {
 708                                 compatible = "arm,pl330", "arm,primecell";
 709                                 reg = <0x12850000 0x1000>;
 710                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 711                                 clocks = <&clock CLK_MDMA>;
 712                                 clock-names = "apb_pclk";
 713                                 #dma-cells = <1>;
 714                                 #dma-channels = <8>;
 715                                 #dma-requests = <1>;
 716                         };
 717                 };
 718
 719                 fimd: fimd@11c00000 {
 720                         compatible = "samsung,exynos4210-fimd";
 721                         interrupt-parent = <&combiner>;
 722                         reg = <0x11c00000 0x20000>;
 723                         interrupt-names = "fifo", "vsync", "lcd_sys";
 724                         interrupts = <11 0>, <11 1>, <11 2>;
 725                         clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>;
 726                         clock-names = "sclk_fimd", "fimd";
 727                         power-domains = <&pd_lcd0>;
 728                         iommus = <&sysmmu_fimd0>;
 729                         samsung,sysreg = <&sys_reg>;
 730                         status = "disabled";
 731                 };
 732
 733                 tmu: tmu@100c0000 {
 734                         interrupt-parent = <&combiner>;
 735                         reg = <0x100C0000 0x100>;
 736                         interrupts = <2 4>;
 737                         status = "disabled";
 738                         #include "exynos4412-tmu-sensor-conf.dtsi"
 739                 };
 740
 741                 jpeg_codec: jpeg-codec@11840000 {
 742                         compatible = "samsung,exynos4210-jpeg";
 743                         reg = <0x11840000 0x1000>;
 744                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 745                         clocks = <&clock CLK_JPEG>;
 746                         clock-names = "jpeg";
 747                         power-domains = <&pd_cam>;
 748                         iommus = <&sysmmu_jpeg>;
 749                 };
 750
 751                 rotator: rotator@12810000 {
 752                         compatible = "samsung,exynos4210-rotator";
 753                         reg = <0x12810000 0x64>;
 754                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 755                         clocks = <&clock CLK_ROTATOR>;
 756                         clock-names = "rotator";
 757                         iommus = <&sysmmu_rotator>;
 758                 };
 759
 760                 hdmi: hdmi@12d00000 {
 761                         compatible = "samsung,exynos4210-hdmi";
 762                         reg = <0x12D00000 0x70000>;
 763                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 764                         clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
 765                                       "sclk_hdmiphy", "mout_hdmi";
 766                         clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
 767                                  <&clock CLK_SCLK_PIXEL>,
 768                                  <&clock CLK_SCLK_HDMIPHY>,
 769                                  <&clock CLK_MOUT_HDMI>;
 770                         phy = <&hdmi_i2c_phy>;
 771                         power-domains = <&pd_tv>;
 772                         samsung,syscon-phandle = <&pmu_system_controller>;
 773                         #sound-dai-cells = <0>;
 774                         status = "disabled";
 775                 };
 776
 777                 hdmicec: cec@100b0000 {
 778                         compatible = "samsung,s5p-cec";
 779                         reg = <0x100B0000 0x200>;
 780                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 781                         clocks = <&clock CLK_HDMI_CEC>;
 782                         clock-names = "hdmicec";
 783                         samsung,syscon-phandle = <&pmu_system_controller>;
 784                         hdmi-phandle = <&hdmi>;
 785                         pinctrl-names = "default";
 786                         pinctrl-0 = <&hdmi_cec>;
 787                         status = "disabled";
 788                 };
 789
 790                 mixer: mixer@12c10000 {
 791                         compatible = "samsung,exynos4210-mixer";
 792                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 793                         reg = <0x12C10000 0x2100>, <0x12c00000 0x300>;
 794                         power-domains = <&pd_tv>;
 795                         iommus = <&sysmmu_tv>;
 796                         status = "disabled";
 797                 };
 798
 799                 ppmu_dmc0: ppmu_dmc0@106a0000 {
 800                         compatible = "samsung,exynos-ppmu";
 801                         reg = <0x106a0000 0x2000>;
 802                         clocks = <&clock CLK_PPMUDMC0>;
 803                         clock-names = "ppmu";
 804                         status = "disabled";
 805                 };
 806
 807                 ppmu_dmc1: ppmu_dmc1@106b0000 {
 808                         compatible = "samsung,exynos-ppmu";
 809                         reg = <0x106b0000 0x2000>;
 810                         clocks = <&clock CLK_PPMUDMC1>;
 811                         clock-names = "ppmu";
 812                         status = "disabled";
 813                 };
 814
 815                 ppmu_cpu: ppmu_cpu@106c0000 {
 816                         compatible = "samsung,exynos-ppmu";
 817                         reg = <0x106c0000 0x2000>;
 818                         clocks = <&clock CLK_PPMUCPU>;
 819                         clock-names = "ppmu";
 820                         status = "disabled";
 821                 };
 822
 823                 ppmu_rightbus: ppmu_rightbus@112a0000 {
 824                         compatible = "samsung,exynos-ppmu";
 825                         reg = <0x112a0000 0x2000>;
 826                         clocks = <&clock CLK_PPMURIGHT>;
 827                         clock-names = "ppmu";
 828                         status = "disabled";
 829                 };
 830
 831                 ppmu_leftbus: ppmu_leftbus0@116a0000 {
 832                         compatible = "samsung,exynos-ppmu";
 833                         reg = <0x116a0000 0x2000>;
 834                         clocks = <&clock CLK_PPMULEFT>;
 835                         clock-names = "ppmu";
 836                         status = "disabled";
 837                 };
 838
 839                 ppmu_camif: ppmu_camif@11ac0000 {
 840                         compatible = "samsung,exynos-ppmu";
 841                         reg = <0x11ac0000 0x2000>;
 842                         clocks = <&clock CLK_PPMUCAMIF>;
 843                         clock-names = "ppmu";
 844                         status = "disabled";
 845                 };
 846
 847                 ppmu_lcd0: ppmu_lcd0@11e40000 {
 848                         compatible = "samsung,exynos-ppmu";
 849                         reg = <0x11e40000 0x2000>;
 850                         clocks = <&clock CLK_PPMULCD0>;
 851                         clock-names = "ppmu";
 852                         status = "disabled";
 853                 };
 854
 855                 ppmu_fsys: ppmu_g3d@12630000 {
 856                         compatible = "samsung,exynos-ppmu";
 857                         reg = <0x12630000 0x2000>;
 858                         status = "disabled";
 859                 };
 860
 861                 ppmu_image: ppmu_image@12aa0000 {
 862                         compatible = "samsung,exynos-ppmu";
 863                         reg = <0x12aa0000 0x2000>;
 864                         clocks = <&clock CLK_PPMUIMAGE>;
 865                         clock-names = "ppmu";
 866                         status = "disabled";
 867                 };
 868
 869                 ppmu_tv: ppmu_tv@12e40000 {
 870                         compatible = "samsung,exynos-ppmu";
 871                         reg = <0x12e40000 0x2000>;
 872                         clocks = <&clock CLK_PPMUTV>;
 873                         clock-names = "ppmu";
 874                         status = "disabled";
 875                 };
 876
 877                 ppmu_g3d: ppmu_g3d@13220000 {
 878                         compatible = "samsung,exynos-ppmu";
 879                         reg = <0x13220000 0x2000>;
 880                         clocks = <&clock CLK_PPMUG3D>;
 881                         clock-names = "ppmu";
 882                         status = "disabled";
 883                 };
 884
 885                 ppmu_mfc_left: ppmu_mfc_left@13660000 {
 886                         compatible = "samsung,exynos-ppmu";
 887                         reg = <0x13660000 0x2000>;
 888                         clocks = <&clock CLK_PPMUMFC_L>;
 889                         clock-names = "ppmu";
 890                         status = "disabled";
 891                 };
 892
 893                 ppmu_mfc_right: ppmu_mfc_right@13670000 {
 894                         compatible = "samsung,exynos-ppmu";
 895                         reg = <0x13670000 0x2000>;
 896                         clocks = <&clock CLK_PPMUMFC_R>;
 897                         clock-names = "ppmu";
 898                         status = "disabled";
 899                 };
 900
 901                 sysmmu_mfc_l: sysmmu@13620000 {
 902                         compatible = "samsung,exynos-sysmmu";
 903                         reg = <0x13620000 0x1000>;
 904                         interrupt-parent = <&combiner>;
 905                         interrupts = <5 5>;
 906                         clock-names = "sysmmu", "master";
 907                         clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
 908                         power-domains = <&pd_mfc>;
 909                         #iommu-cells = <0>;
 910                 };
 911
 912                 sysmmu_mfc_r: sysmmu@13630000 {
 913                         compatible = "samsung,exynos-sysmmu";
 914                         reg = <0x13630000 0x1000>;
 915                         interrupt-parent = <&combiner>;
 916                         interrupts = <5 6>;
 917                         clock-names = "sysmmu", "master";
 918                         clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
 919                         power-domains = <&pd_mfc>;
 920                         #iommu-cells = <0>;
 921                 };
 922
 923                 sysmmu_tv: sysmmu@12e20000 {
 924                         compatible = "samsung,exynos-sysmmu";
 925                         reg = <0x12E20000 0x1000>;
 926                         interrupt-parent = <&combiner>;
 927                         interrupts = <5 4>;
 928                         clock-names = "sysmmu", "master";
 929                         clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
 930                         power-domains = <&pd_tv>;
 931                         #iommu-cells = <0>;
 932                 };
 933
 934                 sysmmu_fimc0: sysmmu@11a20000 {
 935                         compatible = "samsung,exynos-sysmmu";
 936                         reg = <0x11A20000 0x1000>;
 937                         interrupt-parent = <&combiner>;
 938                         interrupts = <4 2>;
 939                         clock-names = "sysmmu", "master";
 940                         clocks = <&clock CLK_SMMU_FIMC0>, <&clock CLK_FIMC0>;
 941                         power-domains = <&pd_cam>;
 942                         #iommu-cells = <0>;
 943                 };
 944
 945                 sysmmu_fimc1: sysmmu@11a30000 {
 946                         compatible = "samsung,exynos-sysmmu";
 947                         reg = <0x11A30000 0x1000>;
 948                         interrupt-parent = <&combiner>;
 949                         interrupts = <4 3>;
 950                         clock-names = "sysmmu", "master";
 951                         clocks = <&clock CLK_SMMU_FIMC1>, <&clock CLK_FIMC1>;
 952                         power-domains = <&pd_cam>;
 953                         #iommu-cells = <0>;
 954                 };
 955
 956                 sysmmu_fimc2: sysmmu@11a40000 {
 957                         compatible = "samsung,exynos-sysmmu";
 958                         reg = <0x11A40000 0x1000>;
 959                         interrupt-parent = <&combiner>;
 960                         interrupts = <4 4>;
 961                         clock-names = "sysmmu", "master";
 962                         clocks = <&clock CLK_SMMU_FIMC2>, <&clock CLK_FIMC2>;
 963                         power-domains = <&pd_cam>;
 964                         #iommu-cells = <0>;
 965                 };
 966
 967                 sysmmu_fimc3: sysmmu@11a50000 {
 968                         compatible = "samsung,exynos-sysmmu";
 969                         reg = <0x11A50000 0x1000>;
 970                         interrupt-parent = <&combiner>;
 971                         interrupts = <4 5>;
 972                         clock-names = "sysmmu", "master";
 973                         clocks = <&clock CLK_SMMU_FIMC3>, <&clock CLK_FIMC3>;
 974                         power-domains = <&pd_cam>;
 975                         #iommu-cells = <0>;
 976                 };
 977
 978                 sysmmu_jpeg: sysmmu@11a60000 {
 979                         compatible = "samsung,exynos-sysmmu";
 980                         reg = <0x11A60000 0x1000>;
 981                         interrupt-parent = <&combiner>;
 982                         interrupts = <4 6>;
 983                         clock-names = "sysmmu", "master";
 984                         clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
 985                         power-domains = <&pd_cam>;
 986                         #iommu-cells = <0>;
 987                 };
 988
 989                 sysmmu_rotator: sysmmu@12a30000 {
 990                         compatible = "samsung,exynos-sysmmu";
 991                         reg = <0x12A30000 0x1000>;
 992                         interrupt-parent = <&combiner>;
 993                         interrupts = <5 0>;
 994                         clock-names = "sysmmu", "master";
 995                         clocks = <&clock CLK_SMMU_ROTATOR>,
 996                                  <&clock CLK_ROTATOR>;
 997                         #iommu-cells = <0>;
 998                 };
 999
1000                 sysmmu_fimd0: sysmmu@11e20000 {
1001                         compatible = "samsung,exynos-sysmmu";
1002                         reg = <0x11E20000 0x1000>;
1003                         interrupt-parent = <&combiner>;
1004                         interrupts = <5 2>;
1005                         clock-names = "sysmmu", "master";
1006                         clocks = <&clock CLK_SMMU_FIMD0>, <&clock CLK_FIMD0>;
1007                         power-domains = <&pd_lcd0>;
1008                         #iommu-cells = <0>;
1009                 };
1010
1011                 sss: sss@10830000 {
1012                         compatible = "samsung,exynos4210-secss";
1013                         reg = <0x10830000 0x300>;
1014                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1015                         clocks = <&clock CLK_SSS>;
1016                         clock-names = "secss";
1017                 };
1018
1019                 prng: rng@10830400 {
1020                         compatible = "samsung,exynos4-rng";
1021                         reg = <0x10830400 0x200>;
1022                         clocks = <&clock CLK_SSS>;
1023                         clock-names = "secss";
1024                 };
1025         };
1026 };
1027
1028 #include "exynos-syscon-restart.dtsi"