Merge tag 'scsi-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi
[sfrench/cifs-2.6.git] / arch / arm / boot / dts / dra72-evm.dts
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
4  */
5 #include "dra72-evm-common.dtsi"
6 #include "dra72x-mmc-iodelay.dtsi"
7 / {
8         model = "TI DRA722";
9
10         memory@0 {
11                 device_type = "memory";
12                 reg = <0x0 0x80000000 0x0 0x40000000>; /* 1024 MB */
13         };
14
15         evm_1v8_sw: fixedregulator-evm_1v8 {
16                 compatible = "regulator-fixed";
17                 regulator-name = "evm_1v8";
18                 regulator-min-microvolt = <1800000>;
19                 regulator-max-microvolt = <1800000>;
20                 vin-supply = <&smps4_reg>;
21                 regulator-always-on;
22                 regulator-boot-on;
23         };
24 };
25
26 &i2c1 {
27         tps65917: tps65917@58 {
28                 reg = <0x58>;
29
30                 interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>;  /* IRQ_SYS_1N */
31         };
32 };
33
34 #include "dra72-evm-tps65917.dtsi"
35
36 &hdmi {
37         vdda-supply = <&ldo3_reg>;
38 };
39
40 &pcf_gpio_21 {
41         interrupt-parent = <&gpio6>;
42         interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
43 };
44
45 &mac {
46         slaves = <1>;
47         mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_HIGH>;
48 };
49
50 &cpsw_emac0 {
51         phy-handle = <&ethphy0>;
52         phy-mode = "rgmii";
53 };
54
55 &davinci_mdio {
56         ethphy0: ethernet-phy@3 {
57                 reg = <3>;
58         };
59 };
60
61 &mmc1 {
62         pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
63         pinctrl-0 = <&mmc1_pins_default>;
64         pinctrl-1 = <&mmc1_pins_hs>;
65         pinctrl-2 = <&mmc1_pins_sdr12>;
66         pinctrl-3 = <&mmc1_pins_sdr25>;
67         pinctrl-4 = <&mmc1_pins_sdr50>;
68         pinctrl-5 = <&mmc1_pins_ddr50_rev10>;
69         pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev10_conf>;
70         vqmmc-supply = <&ldo1_reg>;
71 };
72
73 &mmc2 {
74         pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
75         pinctrl-0 = <&mmc2_pins_default>;
76         pinctrl-1 = <&mmc2_pins_hs>;
77         pinctrl-2 = <&mmc2_pins_ddr_rev10>;
78         pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev10_conf>;
79         vmmc-supply = <&evm_1v8_sw>;
80 };