arch/arm/boot/dts/dra7.dtsi

   1 /*
   2  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  * Based on "omap4.dtsi"
   8  */
   9
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/pinctrl/dra.h>
  12
  13 #include "skeleton.dtsi"
  14
  15 #define MAX_SOURCES 400
  16 #define DIRECT_IRQ(irq) (MAX_SOURCES + irq)
  17
  18 / {
  19         #address-cells = <1>;
  20         #size-cells = <1>;
  21
  22         compatible = "ti,dra7xx";
  23         interrupt-parent = <&gic>;
  24
  25         aliases {
  26                 i2c0 = &i2c1;
  27                 i2c1 = &i2c2;
  28                 i2c2 = &i2c3;
  29                 i2c3 = &i2c4;
  30                 i2c4 = &i2c5;
  31                 serial0 = &uart1;
  32                 serial1 = &uart2;
  33                 serial2 = &uart3;
  34                 serial3 = &uart4;
  35                 serial4 = &uart5;
  36                 serial5 = &uart6;
  37         };
  38
  39         timer {
  40                 compatible = "arm,armv7-timer";
  41                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  42                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  43                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  44                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
  45         };
  46
  47         gic: interrupt-controller@48211000 {
  48                 compatible = "arm,cortex-a15-gic";
  49                 interrupt-controller;
  50                 #interrupt-cells = <3>;
  51                 arm,routable-irqs = <192>;
  52                 reg = <0x48211000 0x1000>,
  53                       <0x48212000 0x1000>,
  54                       <0x48214000 0x2000>,
  55                       <0x48216000 0x2000>;
  56                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  57         };
  58
  59         /*
  60          * The soc node represents the soc top level view. It is used for IPs
  61          * that are not memory mapped in the MPU view or for the MPU itself.
  62          */
  63         soc {
  64                 compatible = "ti,omap-infra";
  65                 mpu {
  66                         compatible = "ti,omap5-mpu";
  67                         ti,hwmods = "mpu";
  68                 };
  69         };
  70
  71         /*
  72          * XXX: Use a flat representation of the SOC interconnect.
  73          * The real OMAP interconnect network is quite complex.
  74          * Since it will not bring real advantage to represent that in DT for
  75          * the moment, just use a fake OCP bus entry to represent the whole bus
  76          * hierarchy.
  77          */
  78         ocp {
  79                 compatible = "ti,dra7-l3-noc", "simple-bus";
  80                 #address-cells = <1>;
  81                 #size-cells = <1>;
  82                 ranges;
  83                 ti,hwmods = "l3_main_1", "l3_main_2";
  84                 reg = <0x44000000 0x1000000>,
  85                       <0x45000000 0x1000>;
  86                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
  87                              <GIC_SPI DIRECT_IRQ(10) IRQ_TYPE_LEVEL_HIGH>;
  88
  89                 prm: prm@4ae06000 {
  90                         compatible = "ti,dra7-prm";
  91                         reg = <0x4ae06000 0x3000>;
  92                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
  93
  94                         prm_clocks: clocks {
  95                                 #address-cells = <1>;
  96                                 #size-cells = <0>;
  97                         };
  98
  99                         prm_clockdomains: clockdomains {
 100                         };
 101                 };
 102
 103                 axi@0 {
 104                         compatible = "simple-bus";
 105                         #size-cells = <1>;
 106                         #address-cells = <1>;
 107                         ranges = <0x51000000 0x51000000 0x3000
 108                                   0x0        0x20000000 0x10000000>;
 109                         pcie@51000000 {
 110                                 compatible = "ti,dra7-pcie";
 111                                 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
 112                                 reg-names = "rc_dbics", "ti_conf", "config";
 113                                 interrupts = <0 232 0x4>, <0 233 0x4>;
 114                                 #address-cells = <3>;
 115                                 #size-cells = <2>;
 116                                 device_type = "pci";
 117                                 ranges = <0x81000000 0 0          0x03000 0 0x00010000
 118                                           0x82000000 0 0x20013000 0x13000 0 0xffed000>;
 119                                 #interrupt-cells = <1>;
 120                                 num-lanes = <1>;
 121                                 ti,hwmods = "pcie1";
 122                                 phys = <&pcie1_phy>;
 123                                 phy-names = "pcie-phy0";
 124                                 interrupt-map-mask = <0 0 0 7>;
 125                                 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
 126                                                 <0 0 0 2 &pcie1_intc 2>,
 127                                                 <0 0 0 3 &pcie1_intc 3>,
 128                                                 <0 0 0 4 &pcie1_intc 4>;
 129                                 pcie1_intc: interrupt-controller {
 130                                         interrupt-controller;
 131                                         #address-cells = <0>;
 132                                         #interrupt-cells = <1>;
 133                                 };
 134                         };
 135                 };
 136
 137                 axi@1 {
 138                         compatible = "simple-bus";
 139                         #size-cells = <1>;
 140                         #address-cells = <1>;
 141                         ranges = <0x51800000 0x51800000 0x3000
 142                                   0x0        0x30000000 0x10000000>;
 143                         status = "disabled";
 144                         pcie@51000000 {
 145                                 compatible = "ti,dra7-pcie";
 146                                 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
 147                                 reg-names = "rc_dbics", "ti_conf", "config";
 148                                 interrupts = <0 355 0x4>, <0 356 0x4>;
 149                                 #address-cells = <3>;
 150                                 #size-cells = <2>;
 151                                 device_type = "pci";
 152                                 ranges = <0x81000000 0 0          0x03000 0 0x00010000
 153                                           0x82000000 0 0x30013000 0x13000 0 0xffed000>;
 154                                 #interrupt-cells = <1>;
 155                                 num-lanes = <1>;
 156                                 ti,hwmods = "pcie2";
 157                                 phys = <&pcie2_phy>;
 158                                 phy-names = "pcie-phy0";
 159                                 interrupt-map-mask = <0 0 0 7>;
 160                                 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
 161                                                 <0 0 0 2 &pcie2_intc 2>,
 162                                                 <0 0 0 3 &pcie2_intc 3>,
 163                                                 <0 0 0 4 &pcie2_intc 4>;
 164                                 pcie2_intc: interrupt-controller {
 165                                         interrupt-controller;
 166                                         #address-cells = <0>;
 167                                         #interrupt-cells = <1>;
 168                                 };
 169                         };
 170                 };
 171
 172                 cm_core_aon: cm_core_aon@4a005000 {
 173                         compatible = "ti,dra7-cm-core-aon";
 174                         reg = <0x4a005000 0x2000>;
 175
 176                         cm_core_aon_clocks: clocks {
 177                                 #address-cells = <1>;
 178                                 #size-cells = <0>;
 179                         };
 180
 181                         cm_core_aon_clockdomains: clockdomains {
 182                         };
 183                 };
 184
 185                 cm_core: cm_core@4a008000 {
 186                         compatible = "ti,dra7-cm-core";
 187                         reg = <0x4a008000 0x3000>;
 188
 189                         cm_core_clocks: clocks {
 190                                 #address-cells = <1>;
 191                                 #size-cells = <0>;
 192                         };
 193
 194                         cm_core_clockdomains: clockdomains {
 195                         };
 196                 };
 197
 198                 counter32k: counter@4ae04000 {
 199                         compatible = "ti,omap-counter32k";
 200                         reg = <0x4ae04000 0x40>;
 201                         ti,hwmods = "counter_32k";
 202                 };
 203
 204                 dra7_ctrl_general: tisyscon@4a002e00 {
 205                         compatible = "syscon";
 206                         reg = <0x4a002e00 0x7c>;
 207                 };
 208
 209                 pbias_regulator: pbias_regulator {
 210                         compatible = "ti,pbias-omap";
 211                         reg = <0 0x4>;
 212                         syscon = <&dra7_ctrl_general>;
 213                         pbias_mmc_reg: pbias_mmc_omap5 {
 214                                 regulator-name = "pbias_mmc_omap5";
 215                                 regulator-min-microvolt = <1800000>;
 216                                 regulator-max-microvolt = <3000000>;
 217                         };
 218                 };
 219
 220                 dra7_pmx_core: pinmux@4a003400 {
 221                         compatible = "pinctrl-single";
 222                         reg = <0x4a003400 0x0464>;
 223                         #address-cells = <1>;
 224                         #size-cells = <0>;
 225                         pinctrl-single,register-width = <32>;
 226                         pinctrl-single,function-mask = <0x3fffffff>;
 227                 };
 228
 229                 sdma: dma-controller@4a056000 {
 230                         compatible = "ti,omap4430-sdma";
 231                         reg = <0x4a056000 0x1000>;
 232                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 233                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 234                                      <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 235                                      <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 236                         #dma-cells = <1>;
 237                         #dma-channels = <32>;
 238                         #dma-requests = <127>;
 239                 };
 240
 241                 gpio1: gpio@4ae10000 {
 242                         compatible = "ti,omap4-gpio";
 243                         reg = <0x4ae10000 0x200>;
 244                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 245                         ti,hwmods = "gpio1";
 246                         gpio-controller;
 247                         #gpio-cells = <2>;
 248                         interrupt-controller;
 249                         #interrupt-cells = <2>;
 250                 };
 251
 252                 gpio2: gpio@48055000 {
 253                         compatible = "ti,omap4-gpio";
 254                         reg = <0x48055000 0x200>;
 255                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 256                         ti,hwmods = "gpio2";
 257                         gpio-controller;
 258                         #gpio-cells = <2>;
 259                         interrupt-controller;
 260                         #interrupt-cells = <2>;
 261                 };
 262
 263                 gpio3: gpio@48057000 {
 264                         compatible = "ti,omap4-gpio";
 265                         reg = <0x48057000 0x200>;
 266                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 267                         ti,hwmods = "gpio3";
 268                         gpio-controller;
 269                         #gpio-cells = <2>;
 270                         interrupt-controller;
 271                         #interrupt-cells = <2>;
 272                 };
 273
 274                 gpio4: gpio@48059000 {
 275                         compatible = "ti,omap4-gpio";
 276                         reg = <0x48059000 0x200>;
 277                         interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 278                         ti,hwmods = "gpio4";
 279                         gpio-controller;
 280                         #gpio-cells = <2>;
 281                         interrupt-controller;
 282                         #interrupt-cells = <2>;
 283                 };
 284
 285                 gpio5: gpio@4805b000 {
 286                         compatible = "ti,omap4-gpio";
 287                         reg = <0x4805b000 0x200>;
 288                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 289                         ti,hwmods = "gpio5";
 290                         gpio-controller;
 291                         #gpio-cells = <2>;
 292                         interrupt-controller;
 293                         #interrupt-cells = <2>;
 294                 };
 295
 296                 gpio6: gpio@4805d000 {
 297                         compatible = "ti,omap4-gpio";
 298                         reg = <0x4805d000 0x200>;
 299                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 300                         ti,hwmods = "gpio6";
 301                         gpio-controller;
 302                         #gpio-cells = <2>;
 303                         interrupt-controller;
 304                         #interrupt-cells = <2>;
 305                 };
 306
 307                 gpio7: gpio@48051000 {
 308                         compatible = "ti,omap4-gpio";
 309                         reg = <0x48051000 0x200>;
 310                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 311                         ti,hwmods = "gpio7";
 312                         gpio-controller;
 313                         #gpio-cells = <2>;
 314                         interrupt-controller;
 315                         #interrupt-cells = <2>;
 316                 };
 317
 318                 gpio8: gpio@48053000 {
 319                         compatible = "ti,omap4-gpio";
 320                         reg = <0x48053000 0x200>;
 321                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 322                         ti,hwmods = "gpio8";
 323                         gpio-controller;
 324                         #gpio-cells = <2>;
 325                         interrupt-controller;
 326                         #interrupt-cells = <2>;
 327                 };
 328
 329                 uart1: serial@4806a000 {
 330                         compatible = "ti,omap4-uart";
 331                         reg = <0x4806a000 0x100>;
 332                         interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 333                         ti,hwmods = "uart1";
 334                         clock-frequency = <48000000>;
 335                         status = "disabled";
 336                 };
 337
 338                 uart2: serial@4806c000 {
 339                         compatible = "ti,omap4-uart";
 340                         reg = <0x4806c000 0x100>;
 341                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 342                         ti,hwmods = "uart2";
 343                         clock-frequency = <48000000>;
 344                         status = "disabled";
 345                 };
 346
 347                 uart3: serial@48020000 {
 348                         compatible = "ti,omap4-uart";
 349                         reg = <0x48020000 0x100>;
 350                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 351                         ti,hwmods = "uart3";
 352                         clock-frequency = <48000000>;
 353                         status = "disabled";
 354                 };
 355
 356                 uart4: serial@4806e000 {
 357                         compatible = "ti,omap4-uart";
 358                         reg = <0x4806e000 0x100>;
 359                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 360                         ti,hwmods = "uart4";
 361                         clock-frequency = <48000000>;
 362                         status = "disabled";
 363                 };
 364
 365                 uart5: serial@48066000 {
 366                         compatible = "ti,omap4-uart";
 367                         reg = <0x48066000 0x100>;
 368                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 369                         ti,hwmods = "uart5";
 370                         clock-frequency = <48000000>;
 371                         status = "disabled";
 372                 };
 373
 374                 uart6: serial@48068000 {
 375                         compatible = "ti,omap4-uart";
 376                         reg = <0x48068000 0x100>;
 377                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 378                         ti,hwmods = "uart6";
 379                         clock-frequency = <48000000>;
 380                         status = "disabled";
 381                 };
 382
 383                 uart7: serial@48420000 {
 384                         compatible = "ti,omap4-uart";
 385                         reg = <0x48420000 0x100>;
 386                         interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
 387                         ti,hwmods = "uart7";
 388                         clock-frequency = <48000000>;
 389                         status = "disabled";
 390                 };
 391
 392                 uart8: serial@48422000 {
 393                         compatible = "ti,omap4-uart";
 394                         reg = <0x48422000 0x100>;
 395                         interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
 396                         ti,hwmods = "uart8";
 397                         clock-frequency = <48000000>;
 398                         status = "disabled";
 399                 };
 400
 401                 uart9: serial@48424000 {
 402                         compatible = "ti,omap4-uart";
 403                         reg = <0x48424000 0x100>;
 404                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
 405                         ti,hwmods = "uart9";
 406                         clock-frequency = <48000000>;
 407                         status = "disabled";
 408                 };
 409
 410                 uart10: serial@4ae2b000 {
 411                         compatible = "ti,omap4-uart";
 412                         reg = <0x4ae2b000 0x100>;
 413                         interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
 414                         ti,hwmods = "uart10";
 415                         clock-frequency = <48000000>;
 416                         status = "disabled";
 417                 };
 418
 419                 mailbox1: mailbox@4a0f4000 {
 420                         compatible = "ti,omap4-mailbox";
 421                         reg = <0x4a0f4000 0x200>;
 422                         ti,hwmods = "mailbox1";
 423                         ti,mbox-num-users = <3>;
 424                         ti,mbox-num-fifos = <8>;
 425                         status = "disabled";
 426                 };
 427
 428                 mailbox2: mailbox@4883a000 {
 429                         compatible = "ti,omap4-mailbox";
 430                         reg = <0x4883a000 0x200>;
 431                         ti,hwmods = "mailbox2";
 432                         ti,mbox-num-users = <4>;
 433                         ti,mbox-num-fifos = <12>;
 434                         status = "disabled";
 435                 };
 436
 437                 mailbox3: mailbox@4883c000 {
 438                         compatible = "ti,omap4-mailbox";
 439                         reg = <0x4883c000 0x200>;
 440                         ti,hwmods = "mailbox3";
 441                         ti,mbox-num-users = <4>;
 442                         ti,mbox-num-fifos = <12>;
 443                         status = "disabled";
 444                 };
 445
 446                 mailbox4: mailbox@4883e000 {
 447                         compatible = "ti,omap4-mailbox";
 448                         reg = <0x4883e000 0x200>;
 449                         ti,hwmods = "mailbox4";
 450                         ti,mbox-num-users = <4>;
 451                         ti,mbox-num-fifos = <12>;
 452                         status = "disabled";
 453                 };
 454
 455                 mailbox5: mailbox@48840000 {
 456                         compatible = "ti,omap4-mailbox";
 457                         reg = <0x48840000 0x200>;
 458                         ti,hwmods = "mailbox5";
 459                         ti,mbox-num-users = <4>;
 460                         ti,mbox-num-fifos = <12>;
 461                         status = "disabled";
 462                 };
 463
 464                 mailbox6: mailbox@48842000 {
 465                         compatible = "ti,omap4-mailbox";
 466                         reg = <0x48842000 0x200>;
 467                         ti,hwmods = "mailbox6";
 468                         ti,mbox-num-users = <4>;
 469                         ti,mbox-num-fifos = <12>;
 470                         status = "disabled";
 471                 };
 472
 473                 mailbox7: mailbox@48844000 {
 474                         compatible = "ti,omap4-mailbox";
 475                         reg = <0x48844000 0x200>;
 476                         ti,hwmods = "mailbox7";
 477                         ti,mbox-num-users = <4>;
 478                         ti,mbox-num-fifos = <12>;
 479                         status = "disabled";
 480                 };
 481
 482                 mailbox8: mailbox@48846000 {
 483                         compatible = "ti,omap4-mailbox";
 484                         reg = <0x48846000 0x200>;
 485                         ti,hwmods = "mailbox8";
 486                         ti,mbox-num-users = <4>;
 487                         ti,mbox-num-fifos = <12>;
 488                         status = "disabled";
 489                 };
 490
 491                 mailbox9: mailbox@4885e000 {
 492                         compatible = "ti,omap4-mailbox";
 493                         reg = <0x4885e000 0x200>;
 494                         ti,hwmods = "mailbox9";
 495                         ti,mbox-num-users = <4>;
 496                         ti,mbox-num-fifos = <12>;
 497                         status = "disabled";
 498                 };
 499
 500                 mailbox10: mailbox@48860000 {
 501                         compatible = "ti,omap4-mailbox";
 502                         reg = <0x48860000 0x200>;
 503                         ti,hwmods = "mailbox10";
 504                         ti,mbox-num-users = <4>;
 505                         ti,mbox-num-fifos = <12>;
 506                         status = "disabled";
 507                 };
 508
 509                 mailbox11: mailbox@48862000 {
 510                         compatible = "ti,omap4-mailbox";
 511                         reg = <0x48862000 0x200>;
 512                         ti,hwmods = "mailbox11";
 513                         ti,mbox-num-users = <4>;
 514                         ti,mbox-num-fifos = <12>;
 515                         status = "disabled";
 516                 };
 517
 518                 mailbox12: mailbox@48864000 {
 519                         compatible = "ti,omap4-mailbox";
 520                         reg = <0x48864000 0x200>;
 521                         ti,hwmods = "mailbox12";
 522                         ti,mbox-num-users = <4>;
 523                         ti,mbox-num-fifos = <12>;
 524                         status = "disabled";
 525                 };
 526
 527                 mailbox13: mailbox@48802000 {
 528                         compatible = "ti,omap4-mailbox";
 529                         reg = <0x48802000 0x200>;
 530                         ti,hwmods = "mailbox13";
 531                         ti,mbox-num-users = <4>;
 532                         ti,mbox-num-fifos = <12>;
 533                         status = "disabled";
 534                 };
 535
 536                 timer1: timer@4ae18000 {
 537                         compatible = "ti,omap5430-timer";
 538                         reg = <0x4ae18000 0x80>;
 539                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 540                         ti,hwmods = "timer1";
 541                         ti,timer-alwon;
 542                 };
 543
 544                 timer2: timer@48032000 {
 545                         compatible = "ti,omap5430-timer";
 546                         reg = <0x48032000 0x80>;
 547                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 548                         ti,hwmods = "timer2";
 549                 };
 550
 551                 timer3: timer@48034000 {
 552                         compatible = "ti,omap5430-timer";
 553                         reg = <0x48034000 0x80>;
 554                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 555                         ti,hwmods = "timer3";
 556                 };
 557
 558                 timer4: timer@48036000 {
 559                         compatible = "ti,omap5430-timer";
 560                         reg = <0x48036000 0x80>;
 561                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 562                         ti,hwmods = "timer4";
 563                 };
 564
 565                 timer5: timer@48820000 {
 566                         compatible = "ti,omap5430-timer";
 567                         reg = <0x48820000 0x80>;
 568                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 569                         ti,hwmods = "timer5";
 570                         ti,timer-dsp;
 571                 };
 572
 573                 timer6: timer@48822000 {
 574                         compatible = "ti,omap5430-timer";
 575                         reg = <0x48822000 0x80>;
 576                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 577                         ti,hwmods = "timer6";
 578                         ti,timer-dsp;
 579                         ti,timer-pwm;
 580                 };
 581
 582                 timer7: timer@48824000 {
 583                         compatible = "ti,omap5430-timer";
 584                         reg = <0x48824000 0x80>;
 585                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 586                         ti,hwmods = "timer7";
 587                         ti,timer-dsp;
 588                 };
 589
 590                 timer8: timer@48826000 {
 591                         compatible = "ti,omap5430-timer";
 592                         reg = <0x48826000 0x80>;
 593                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 594                         ti,hwmods = "timer8";
 595                         ti,timer-dsp;
 596                         ti,timer-pwm;
 597                 };
 598
 599                 timer9: timer@4803e000 {
 600                         compatible = "ti,omap5430-timer";
 601                         reg = <0x4803e000 0x80>;
 602                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 603                         ti,hwmods = "timer9";
 604                 };
 605
 606                 timer10: timer@48086000 {
 607                         compatible = "ti,omap5430-timer";
 608                         reg = <0x48086000 0x80>;
 609                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 610                         ti,hwmods = "timer10";
 611                 };
 612
 613                 timer11: timer@48088000 {
 614                         compatible = "ti,omap5430-timer";
 615                         reg = <0x48088000 0x80>;
 616                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 617                         ti,hwmods = "timer11";
 618                         ti,timer-pwm;
 619                 };
 620
 621                 timer13: timer@48828000 {
 622                         compatible = "ti,omap5430-timer";
 623                         reg = <0x48828000 0x80>;
 624                         interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
 625                         ti,hwmods = "timer13";
 626                         status = "disabled";
 627                 };
 628
 629                 timer14: timer@4882a000 {
 630                         compatible = "ti,omap5430-timer";
 631                         reg = <0x4882a000 0x80>;
 632                         interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
 633                         ti,hwmods = "timer14";
 634                         status = "disabled";
 635                 };
 636
 637                 timer15: timer@4882c000 {
 638                         compatible = "ti,omap5430-timer";
 639                         reg = <0x4882c000 0x80>;
 640                         interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
 641                         ti,hwmods = "timer15";
 642                         status = "disabled";
 643                 };
 644
 645                 timer16: timer@4882e000 {
 646                         compatible = "ti,omap5430-timer";
 647                         reg = <0x4882e000 0x80>;
 648                         interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
 649                         ti,hwmods = "timer16";
 650                         status = "disabled";
 651                 };
 652
 653                 wdt2: wdt@4ae14000 {
 654                         compatible = "ti,omap4-wdt";
 655                         reg = <0x4ae14000 0x80>;
 656                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 657                         ti,hwmods = "wd_timer2";
 658                 };
 659
 660                 hwspinlock: spinlock@4a0f6000 {
 661                         compatible = "ti,omap4-hwspinlock";
 662                         reg = <0x4a0f6000 0x1000>;
 663                         ti,hwmods = "spinlock";
 664                         #hwlock-cells = <1>;
 665                 };
 666
 667                 dmm@4e000000 {
 668                         compatible = "ti,omap5-dmm";
 669                         reg = <0x4e000000 0x800>;
 670                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 671                         ti,hwmods = "dmm";
 672                 };
 673
 674                 i2c1: i2c@48070000 {
 675                         compatible = "ti,omap4-i2c";
 676                         reg = <0x48070000 0x100>;
 677                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 678                         #address-cells = <1>;
 679                         #size-cells = <0>;
 680                         ti,hwmods = "i2c1";
 681                         status = "disabled";
 682                 };
 683
 684                 i2c2: i2c@48072000 {
 685                         compatible = "ti,omap4-i2c";
 686                         reg = <0x48072000 0x100>;
 687                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 688                         #address-cells = <1>;
 689                         #size-cells = <0>;
 690                         ti,hwmods = "i2c2";
 691                         status = "disabled";
 692                 };
 693
 694                 i2c3: i2c@48060000 {
 695                         compatible = "ti,omap4-i2c";
 696                         reg = <0x48060000 0x100>;
 697                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 698                         #address-cells = <1>;
 699                         #size-cells = <0>;
 700                         ti,hwmods = "i2c3";
 701                         status = "disabled";
 702                 };
 703
 704                 i2c4: i2c@4807a000 {
 705                         compatible = "ti,omap4-i2c";
 706                         reg = <0x4807a000 0x100>;
 707                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 708                         #address-cells = <1>;
 709                         #size-cells = <0>;
 710                         ti,hwmods = "i2c4";
 711                         status = "disabled";
 712                 };
 713
 714                 i2c5: i2c@4807c000 {
 715                         compatible = "ti,omap4-i2c";
 716                         reg = <0x4807c000 0x100>;
 717                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 718                         #address-cells = <1>;
 719                         #size-cells = <0>;
 720                         ti,hwmods = "i2c5";
 721                         status = "disabled";
 722                 };
 723
 724                 mmc1: mmc@4809c000 {
 725                         compatible = "ti,omap4-hsmmc";
 726                         reg = <0x4809c000 0x400>;
 727                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 728                         ti,hwmods = "mmc1";
 729                         ti,dual-volt;
 730                         ti,needs-special-reset;
 731                         dmas = <&sdma 61>, <&sdma 62>;
 732                         dma-names = "tx", "rx";
 733                         status = "disabled";
 734                         pbias-supply = <&pbias_mmc_reg>;
 735                 };
 736
 737                 mmc2: mmc@480b4000 {
 738                         compatible = "ti,omap4-hsmmc";
 739                         reg = <0x480b4000 0x400>;
 740                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 741                         ti,hwmods = "mmc2";
 742                         ti,needs-special-reset;
 743                         dmas = <&sdma 47>, <&sdma 48>;
 744                         dma-names = "tx", "rx";
 745                         status = "disabled";
 746                 };
 747
 748                 mmc3: mmc@480ad000 {
 749                         compatible = "ti,omap4-hsmmc";
 750                         reg = <0x480ad000 0x400>;
 751                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 752                         ti,hwmods = "mmc3";
 753                         ti,needs-special-reset;
 754                         dmas = <&sdma 77>, <&sdma 78>;
 755                         dma-names = "tx", "rx";
 756                         status = "disabled";
 757                 };
 758
 759                 mmc4: mmc@480d1000 {
 760                         compatible = "ti,omap4-hsmmc";
 761                         reg = <0x480d1000 0x400>;
 762                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 763                         ti,hwmods = "mmc4";
 764                         ti,needs-special-reset;
 765                         dmas = <&sdma 57>, <&sdma 58>;
 766                         dma-names = "tx", "rx";
 767                         status = "disabled";
 768                 };
 769
 770                 abb_mpu: regulator-abb-mpu {
 771                         compatible = "ti,abb-v3";
 772                         regulator-name = "abb_mpu";
 773                         #address-cells = <0>;
 774                         #size-cells = <0>;
 775                         clocks = <&sys_clkin1>;
 776                         ti,settling-time = <50>;
 777                         ti,clock-cycles = <16>;
 778
 779                         reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
 780                               <0x4ae06014 0x4>, <0x4a003b20 0x8>,
 781                               <0x4ae0c158 0x4>;
 782                         reg-names = "setup-address", "control-address",
 783                                     "int-address", "efuse-address",
 784                                     "ldo-address";
 785                         ti,tranxdone-status-mask = <0x80>;
 786                         /* LDOVBBMPU_FBB_MUX_CTRL */
 787                         ti,ldovbb-override-mask = <0x400>;
 788                         /* LDOVBBMPU_FBB_VSET_OUT */
 789                         ti,ldovbb-vset-mask = <0x1F>;
 790
 791                         /*
 792                          * NOTE: only FBB mode used but actual vset will
 793                          * determine final biasing
 794                          */
 795                         ti,abb_info = <
 796                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
 797                         1060000         0       0x0     0 0x02000000 0x01F00000
 798                         1160000         0       0x4     0 0x02000000 0x01F00000
 799                         1210000         0       0x8     0 0x02000000 0x01F00000
 800                         >;
 801                 };
 802
 803                 abb_ivahd: regulator-abb-ivahd {
 804                         compatible = "ti,abb-v3";
 805                         regulator-name = "abb_ivahd";
 806                         #address-cells = <0>;
 807                         #size-cells = <0>;
 808                         clocks = <&sys_clkin1>;
 809                         ti,settling-time = <50>;
 810                         ti,clock-cycles = <16>;
 811
 812                         reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
 813                               <0x4ae06010 0x4>, <0x4a0025cc 0x8>,
 814                               <0x4a002470 0x4>;
 815                         reg-names = "setup-address", "control-address",
 816                                     "int-address", "efuse-address",
 817                                     "ldo-address";
 818                         ti,tranxdone-status-mask = <0x40000000>;
 819                         /* LDOVBBIVA_FBB_MUX_CTRL */
 820                         ti,ldovbb-override-mask = <0x400>;
 821                         /* LDOVBBIVA_FBB_VSET_OUT */
 822                         ti,ldovbb-vset-mask = <0x1F>;
 823
 824                         /*
 825                          * NOTE: only FBB mode used but actual vset will
 826                          * determine final biasing
 827                          */
 828                         ti,abb_info = <
 829                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
 830                         1055000         0       0x0     0 0x02000000 0x01F00000
 831                         1150000         0       0x4     0 0x02000000 0x01F00000
 832                         1250000         0       0x8     0 0x02000000 0x01F00000
 833                         >;
 834                 };
 835
 836                 abb_dspeve: regulator-abb-dspeve {
 837                         compatible = "ti,abb-v3";
 838                         regulator-name = "abb_dspeve";
 839                         #address-cells = <0>;
 840                         #size-cells = <0>;
 841                         clocks = <&sys_clkin1>;
 842                         ti,settling-time = <50>;
 843                         ti,clock-cycles = <16>;
 844
 845                         reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
 846                               <0x4ae06010 0x4>, <0x4a0025e0 0x8>,
 847                               <0x4a00246c 0x4>;
 848                         reg-names = "setup-address", "control-address",
 849                                     "int-address", "efuse-address",
 850                                     "ldo-address";
 851                         ti,tranxdone-status-mask = <0x20000000>;
 852                         /* LDOVBBDSPEVE_FBB_MUX_CTRL */
 853                         ti,ldovbb-override-mask = <0x400>;
 854                         /* LDOVBBDSPEVE_FBB_VSET_OUT */
 855                         ti,ldovbb-vset-mask = <0x1F>;
 856
 857                         /*
 858                          * NOTE: only FBB mode used but actual vset will
 859                          * determine final biasing
 860                          */
 861                         ti,abb_info = <
 862                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
 863                         1055000         0       0x0     0 0x02000000 0x01F00000
 864                         1150000         0       0x4     0 0x02000000 0x01F00000
 865                         1250000         0       0x8     0 0x02000000 0x01F00000
 866                         >;
 867                 };
 868
 869                 abb_gpu: regulator-abb-gpu {
 870                         compatible = "ti,abb-v3";
 871                         regulator-name = "abb_gpu";
 872                         #address-cells = <0>;
 873                         #size-cells = <0>;
 874                         clocks = <&sys_clkin1>;
 875                         ti,settling-time = <50>;
 876                         ti,clock-cycles = <16>;
 877
 878                         reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
 879                               <0x4ae06010 0x4>, <0x4a003b08 0x8>,
 880                               <0x4ae0c154 0x4>;
 881                         reg-names = "setup-address", "control-address",
 882                                     "int-address", "efuse-address",
 883                                     "ldo-address";
 884                         ti,tranxdone-status-mask = <0x10000000>;
 885                         /* LDOVBBGPU_FBB_MUX_CTRL */
 886                         ti,ldovbb-override-mask = <0x400>;
 887                         /* LDOVBBGPU_FBB_VSET_OUT */
 888                         ti,ldovbb-vset-mask = <0x1F>;
 889
 890                         /*
 891                          * NOTE: only FBB mode used but actual vset will
 892                          * determine final biasing
 893                          */
 894                         ti,abb_info = <
 895                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
 896                         1090000         0       0x0     0 0x02000000 0x01F00000
 897                         1210000         0       0x4     0 0x02000000 0x01F00000
 898                         1280000         0       0x8     0 0x02000000 0x01F00000
 899                         >;
 900                 };
 901
 902                 mcspi1: spi@48098000 {
 903                         compatible = "ti,omap4-mcspi";
 904                         reg = <0x48098000 0x200>;
 905                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 906                         #address-cells = <1>;
 907                         #size-cells = <0>;
 908                         ti,hwmods = "mcspi1";
 909                         ti,spi-num-cs = <4>;
 910                         dmas = <&sdma 35>,
 911                                <&sdma 36>,
 912                                <&sdma 37>,
 913                                <&sdma 38>,
 914                                <&sdma 39>,
 915                                <&sdma 40>,
 916                                <&sdma 41>,
 917                                <&sdma 42>;
 918                         dma-names = "tx0", "rx0", "tx1", "rx1",
 919                                     "tx2", "rx2", "tx3", "rx3";
 920                         status = "disabled";
 921                 };
 922
 923                 mcspi2: spi@4809a000 {
 924                         compatible = "ti,omap4-mcspi";
 925                         reg = <0x4809a000 0x200>;
 926                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 927                         #address-cells = <1>;
 928                         #size-cells = <0>;
 929                         ti,hwmods = "mcspi2";
 930                         ti,spi-num-cs = <2>;
 931                         dmas = <&sdma 43>,
 932                                <&sdma 44>,
 933                                <&sdma 45>,
 934                                <&sdma 46>;
 935                         dma-names = "tx0", "rx0", "tx1", "rx1";
 936                         status = "disabled";
 937                 };
 938
 939                 mcspi3: spi@480b8000 {
 940                         compatible = "ti,omap4-mcspi";
 941                         reg = <0x480b8000 0x200>;
 942                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 943                         #address-cells = <1>;
 944                         #size-cells = <0>;
 945                         ti,hwmods = "mcspi3";
 946                         ti,spi-num-cs = <2>;
 947                         dmas = <&sdma 15>, <&sdma 16>;
 948                         dma-names = "tx0", "rx0";
 949                         status = "disabled";
 950                 };
 951
 952                 mcspi4: spi@480ba000 {
 953                         compatible = "ti,omap4-mcspi";
 954                         reg = <0x480ba000 0x200>;
 955                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 956                         #address-cells = <1>;
 957                         #size-cells = <0>;
 958                         ti,hwmods = "mcspi4";
 959                         ti,spi-num-cs = <1>;
 960                         dmas = <&sdma 70>, <&sdma 71>;
 961                         dma-names = "tx0", "rx0";
 962                         status = "disabled";
 963                 };
 964
 965                 qspi: qspi@4b300000 {
 966                         compatible = "ti,dra7xxx-qspi";
 967                         reg = <0x4b300000 0x100>;
 968                         reg-names = "qspi_base";
 969                         #address-cells = <1>;
 970                         #size-cells = <0>;
 971                         ti,hwmods = "qspi";
 972                         clocks = <&qspi_gfclk_div>;
 973                         clock-names = "fck";
 974                         num-cs = <4>;
 975                         interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
 976                         status = "disabled";
 977                 };
 978
 979                 omap_control_sata: control-phy@4a002374 {
 980                         compatible = "ti,control-phy-pipe3";
 981                         reg = <0x4a002374 0x4>;
 982                         reg-names = "power";
 983                         clocks = <&sys_clkin1>;
 984                         clock-names = "sysclk";
 985                 };
 986
 987                 /* OCP2SCP3 */
 988                 ocp2scp@4a090000 {
 989                         compatible = "ti,omap-ocp2scp";
 990                         #address-cells = <1>;
 991                         #size-cells = <1>;
 992                         ranges;
 993                         reg = <0x4a090000 0x20>;
 994                         ti,hwmods = "ocp2scp3";
 995                         sata_phy: phy@4A096000 {
 996                                 compatible = "ti,phy-pipe3-sata";
 997                                 reg = <0x4A096000 0x80>, /* phy_rx */
 998                                       <0x4A096400 0x64>, /* phy_tx */
 999                                       <0x4A096800 0x40>; /* pll_ctrl */
1000                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1001                                 ctrl-module = <&omap_control_sata>;
1002                                 clocks = <&sys_clkin1>;
1003                                 clock-names = "sysclk";
1004                                 #phy-cells = <0>;
1005                         };
1006
1007                         pcie1_phy: pciephy@4a094000 {
1008                                 compatible = "ti,phy-pipe3-pcie";
1009                                 reg = <0x4a094000 0x80>, /* phy_rx */
1010                                       <0x4a094400 0x64>; /* phy_tx */
1011                                 reg-names = "phy_rx", "phy_tx";
1012                                 ctrl-module = <&omap_control_pcie1phy>;
1013                                 clocks = <&dpll_pcie_ref_ck>,
1014                                          <&dpll_pcie_ref_m2ldo_ck>,
1015                                          <&optfclk_pciephy1_32khz>,
1016                                          <&optfclk_pciephy1_clk>,
1017                                          <&optfclk_pciephy1_div_clk>,
1018                                          <&optfclk_pciephy_div>;
1019                                 clock-names = "dpll_ref", "dpll_ref_m2",
1020                                               "wkupclk", "refclk",
1021                                               "div-clk", "phy-div";
1022                                 #phy-cells = <0>;
1023                                 id = <1>;
1024                                 ti,hwmods = "pcie1-phy";
1025                         };
1026
1027                         pcie2_phy: pciephy@4a095000 {
1028                                 compatible = "ti,phy-pipe3-pcie";
1029                                 reg = <0x4a095000 0x80>, /* phy_rx */
1030                                       <0x4a095400 0x64>; /* phy_tx */
1031                                 reg-names = "phy_rx", "phy_tx";
1032                                 ctrl-module = <&omap_control_pcie2phy>;
1033                                 clocks = <&dpll_pcie_ref_ck>,
1034                                          <&dpll_pcie_ref_m2ldo_ck>,
1035                                          <&optfclk_pciephy2_32khz>,
1036                                          <&optfclk_pciephy2_clk>,
1037                                          <&optfclk_pciephy2_div_clk>,
1038                                          <&optfclk_pciephy_div>;
1039                                 clock-names = "dpll_ref", "dpll_ref_m2",
1040                                               "wkupclk", "refclk",
1041                                               "div-clk", "phy-div";
1042                                 #phy-cells = <0>;
1043                                 ti,hwmods = "pcie2-phy";
1044                                 id = <2>;
1045                                 status = "disabled";
1046                         };
1047                 };
1048
1049                 sata: sata@4a141100 {
1050                         compatible = "snps,dwc-ahci";
1051                         reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
1052                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1053                         phys = <&sata_phy>;
1054                         phy-names = "sata-phy";
1055                         clocks = <&sata_ref_clk>;
1056                         ti,hwmods = "sata";
1057                 };
1058
1059                 omap_control_pcie1phy: control-phy@0x4a003c40 {
1060                         compatible = "ti,control-phy-pcie";
1061                         reg = <0x4a003c40 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
1062                         reg-names = "power", "control_sma", "pcie_pcs";
1063                         clocks = <&sys_clkin1>;
1064                         clock-names = "sysclk";
1065                 };
1066
1067                 omap_control_pcie2phy: control-pcie@0x4a003c44 {
1068                         compatible = "ti,control-phy-pcie";
1069                         reg = <0x4a003c44 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
1070                         reg-names = "power", "control_sma", "pcie_pcs";
1071                         clocks = <&sys_clkin1>;
1072                         clock-names = "sysclk";
1073                         status = "disabled";
1074                 };
1075
1076                 omap_control_usb2phy1: control-phy@4a002300 {
1077                         compatible = "ti,control-phy-usb2";
1078                         reg = <0x4a002300 0x4>;
1079                         reg-names = "power";
1080                 };
1081
1082                 omap_control_usb3phy1: control-phy@4a002370 {
1083                         compatible = "ti,control-phy-pipe3";
1084                         reg = <0x4a002370 0x4>;
1085                         reg-names = "power";
1086                 };
1087
1088                 omap_control_usb2phy2: control-phy@0x4a002e74 {
1089                         compatible = "ti,control-phy-usb2-dra7";
1090                         reg = <0x4a002e74 0x4>;
1091                         reg-names = "power";
1092                 };
1093
1094                 /* OCP2SCP1 */
1095                 ocp2scp@4a080000 {
1096                         compatible = "ti,omap-ocp2scp";
1097                         #address-cells = <1>;
1098                         #size-cells = <1>;
1099                         ranges;
1100                         reg = <0x4a080000 0x20>;
1101                         ti,hwmods = "ocp2scp1";
1102
1103                         usb2_phy1: phy@4a084000 {
1104                                 compatible = "ti,omap-usb2";
1105                                 reg = <0x4a084000 0x400>;
1106                                 ctrl-module = <&omap_control_usb2phy1>;
1107                                 clocks = <&usb_phy1_always_on_clk32k>,
1108                                          <&usb_otg_ss1_refclk960m>;
1109                                 clock-names =   "wkupclk",
1110                                                 "refclk";
1111                                 #phy-cells = <0>;
1112                         };
1113
1114                         usb2_phy2: phy@4a085000 {
1115                                 compatible = "ti,omap-usb2";
1116                                 reg = <0x4a085000 0x400>;
1117                                 ctrl-module = <&omap_control_usb2phy2>;
1118                                 clocks = <&usb_phy2_always_on_clk32k>,
1119                                          <&usb_otg_ss2_refclk960m>;
1120                                 clock-names =   "wkupclk",
1121                                                 "refclk";
1122                                 #phy-cells = <0>;
1123                         };
1124
1125                         usb3_phy1: phy@4a084400 {
1126                                 compatible = "ti,omap-usb3";
1127                                 reg = <0x4a084400 0x80>,
1128                                       <0x4a084800 0x64>,
1129                                       <0x4a084c00 0x40>;
1130                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1131                                 ctrl-module = <&omap_control_usb3phy1>;
1132                                 clocks = <&usb_phy3_always_on_clk32k>,
1133                                          <&sys_clkin1>,
1134                                          <&usb_otg_ss1_refclk960m>;
1135                                 clock-names =   "wkupclk",
1136                                                 "sysclk",
1137                                                 "refclk";
1138                                 #phy-cells = <0>;
1139                         };
1140                 };
1141
1142                 omap_dwc3_1@48880000 {
1143                         compatible = "ti,dwc3";
1144                         ti,hwmods = "usb_otg_ss1";
1145                         reg = <0x48880000 0x10000>;
1146                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1147                         #address-cells = <1>;
1148                         #size-cells = <1>;
1149                         utmi-mode = <2>;
1150                         ranges;
1151                         usb1: usb@48890000 {
1152                                 compatible = "snps,dwc3";
1153                                 reg = <0x48890000 0x17000>;
1154                                 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1155                                 phys = <&usb2_phy1>, <&usb3_phy1>;
1156                                 phy-names = "usb2-phy", "usb3-phy";
1157                                 tx-fifo-resize;
1158                                 maximum-speed = "super-speed";
1159                                 dr_mode = "otg";
1160                         };
1161                 };
1162
1163                 omap_dwc3_2@488c0000 {
1164                         compatible = "ti,dwc3";
1165                         ti,hwmods = "usb_otg_ss2";
1166                         reg = <0x488c0000 0x10000>;
1167                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1168                         #address-cells = <1>;
1169                         #size-cells = <1>;
1170                         utmi-mode = <2>;
1171                         ranges;
1172                         usb2: usb@488d0000 {
1173                                 compatible = "snps,dwc3";
1174                                 reg = <0x488d0000 0x17000>;
1175                                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1176                                 phys = <&usb2_phy2>;
1177                                 phy-names = "usb2-phy";
1178                                 tx-fifo-resize;
1179                                 maximum-speed = "high-speed";
1180                                 dr_mode = "otg";
1181                         };
1182                 };
1183
1184                 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
1185                 omap_dwc3_3@48900000 {
1186                         compatible = "ti,dwc3";
1187                         ti,hwmods = "usb_otg_ss3";
1188                         reg = <0x48900000 0x10000>;
1189                         interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1190                         #address-cells = <1>;
1191                         #size-cells = <1>;
1192                         utmi-mode = <2>;
1193                         ranges;
1194                         status = "disabled";
1195                         usb3: usb@48910000 {
1196                                 compatible = "snps,dwc3";
1197                                 reg = <0x48910000 0x17000>;
1198                                 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1199                                 tx-fifo-resize;
1200                                 maximum-speed = "high-speed";
1201                                 dr_mode = "otg";
1202                         };
1203                 };
1204
1205                 omap_dwc3_4@48940000 {
1206                         compatible = "ti,dwc3";
1207                         ti,hwmods = "usb_otg_ss4";
1208                         reg = <0x48940000 0x10000>;
1209                         interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
1210                         #address-cells = <1>;
1211                         #size-cells = <1>;
1212                         utmi-mode = <2>;
1213                         ranges;
1214                         status = "disabled";
1215                         usb4: usb@48950000 {
1216                                 compatible = "snps,dwc3";
1217                                 reg = <0x48950000 0x17000>;
1218                                 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
1219                                 tx-fifo-resize;
1220                                 maximum-speed = "high-speed";
1221                                 dr_mode = "otg";
1222                         };
1223                 };
1224
1225                 elm: elm@48078000 {
1226                         compatible = "ti,am3352-elm";
1227                         reg = <0x48078000 0xfc0>;      /* device IO registers */
1228                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1229                         ti,hwmods = "elm";
1230                         status = "disabled";
1231                 };
1232
1233                 gpmc: gpmc@50000000 {
1234                         compatible = "ti,am3352-gpmc";
1235                         ti,hwmods = "gpmc";
1236                         reg = <0x50000000 0x37c>;      /* device IO registers */
1237                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1238                         gpmc,num-cs = <8>;
1239                         gpmc,num-waitpins = <2>;
1240                         #address-cells = <2>;
1241                         #size-cells = <1>;
1242                         status = "disabled";
1243                 };
1244
1245                 atl: atl@4843c000 {
1246                         compatible = "ti,dra7-atl";
1247                         reg = <0x4843c000 0x3ff>;
1248                         ti,hwmods = "atl";
1249                         ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
1250                                              <&atl_clkin2_ck>, <&atl_clkin3_ck>;
1251                         clocks = <&atl_gfclk_mux>;
1252                         clock-names = "fck";
1253                         status = "disabled";
1254                 };
1255
1256                 crossbar_mpu: crossbar@4a020000 {
1257                         compatible = "ti,irq-crossbar";
1258                         reg = <0x4a002a48 0x130>;
1259                         ti,max-irqs = <160>;
1260                         ti,max-crossbar-sources = <MAX_SOURCES>;
1261                         ti,reg-size = <2>;
1262                         ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
1263                         ti,irqs-skip = <10 133 139 140>;
1264                         ti,irqs-safe-map = <0>;
1265                 };
1266         };
1267 };
1268
1269 /include/ "dra7xx-clocks.dtsi"