arch/arm/boot/dts/dra7-evm.dts

   1 /*
   2  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8 /dts-v1/;
   9
  10 #include "dra74x.dtsi"
  11 #include <dt-bindings/gpio/gpio.h>
  12
  13 / {
  14         model = "TI DRA742";
  15         compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
  16
  17         memory {
  18                 device_type = "memory";
  19                 reg = <0x80000000 0x60000000>; /* 1536 MB */
  20         };
  21
  22         mmc2_3v3: fixedregulator-mmc2 {
  23                 compatible = "regulator-fixed";
  24                 regulator-name = "mmc2_3v3";
  25                 regulator-min-microvolt = <3300000>;
  26                 regulator-max-microvolt = <3300000>;
  27         };
  28
  29         vtt_fixed: fixedregulator-vtt {
  30                 compatible = "regulator-fixed";
  31                 regulator-name = "vtt_fixed";
  32                 regulator-min-microvolt = <1350000>;
  33                 regulator-max-microvolt = <1350000>;
  34                 regulator-always-on;
  35                 regulator-boot-on;
  36                 enable-active-high;
  37                 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
  38         };
  39 };
  40
  41 &dra7_pmx_core {
  42         pinctrl-names = "default";
  43         pinctrl-0 = <&vtt_pin>;
  44
  45         vtt_pin: pinmux_vtt_pin {
  46                 pinctrl-single,pins = <
  47                         0x3b4 (PIN_OUTPUT | MUX_MODE14) /* spi1_cs1.gpio7_11 */
  48                 >;
  49         };
  50
  51         i2c1_pins: pinmux_i2c1_pins {
  52                 pinctrl-single,pins = <
  53                         0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda */
  54                         0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl */
  55                 >;
  56         };
  57
  58         i2c2_pins: pinmux_i2c2_pins {
  59                 pinctrl-single,pins = <
  60                         0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda */
  61                         0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl */
  62                 >;
  63         };
  64
  65         i2c3_pins: pinmux_i2c3_pins {
  66                 pinctrl-single,pins = <
  67                         0x288 (PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */
  68                         0x28c (PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */
  69                 >;
  70         };
  71
  72         mcspi1_pins: pinmux_mcspi1_pins {
  73                 pinctrl-single,pins = <
  74                         0x3a4 (PIN_INPUT | MUX_MODE0) /* spi1_sclk */
  75                         0x3a8 (PIN_INPUT | MUX_MODE0) /* spi1_d1 */
  76                         0x3ac (PIN_INPUT | MUX_MODE0) /* spi1_d0 */
  77                         0x3b0 (PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */
  78                         0x3b8 (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */
  79                         0x3bc (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */
  80                 >;
  81         };
  82
  83         mcspi2_pins: pinmux_mcspi2_pins {
  84                 pinctrl-single,pins = <
  85                         0x3c0 (PIN_INPUT | MUX_MODE0) /* spi2_sclk */
  86                         0x3c4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
  87                         0x3c8 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
  88                         0x3cc (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */
  89                 >;
  90         };
  91
  92         uart1_pins: pinmux_uart1_pins {
  93                 pinctrl-single,pins = <
  94                         0x3e0 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */
  95                         0x3e4 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */
  96                         0x3e8 (PIN_INPUT | MUX_MODE3) /* uart1_ctsn */
  97                         0x3ec (PIN_INPUT | MUX_MODE3) /* uart1_rtsn */
  98                 >;
  99         };
 100
 101         uart2_pins: pinmux_uart2_pins {
 102                 pinctrl-single,pins = <
 103                         0x3f0 (PIN_INPUT | MUX_MODE0) /* uart2_rxd */
 104                         0x3f4 (PIN_INPUT | MUX_MODE0) /* uart2_txd */
 105                         0x3f8 (PIN_INPUT | MUX_MODE0) /* uart2_ctsn */
 106                         0x3fc (PIN_INPUT | MUX_MODE0) /* uart2_rtsn */
 107                 >;
 108         };
 109
 110         uart3_pins: pinmux_uart3_pins {
 111                 pinctrl-single,pins = <
 112                         0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */
 113                         0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
 114                 >;
 115         };
 116
 117         qspi1_pins: pinmux_qspi1_pins {
 118                 pinctrl-single,pins = <
 119                         0x4c (PIN_INPUT | MUX_MODE1)  /* gpmc_a3.qspi1_cs2 */
 120                         0x50 (PIN_INPUT | MUX_MODE1)  /* gpmc_a4.qspi1_cs3 */
 121                         0x74 (PIN_INPUT | MUX_MODE1)  /* gpmc_a13.qspi1_rtclk */
 122                         0x78 (PIN_INPUT | MUX_MODE1)  /* gpmc_a14.qspi1_d3 */
 123                         0x7c (PIN_INPUT | MUX_MODE1)  /* gpmc_a15.qspi1_d2 */
 124                         0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
 125                         0x84 (PIN_INPUT | MUX_MODE1)  /* gpmc_a17.qspi1_d0 */
 126                         0x88 (PIN_INPUT | MUX_MODE1)  /* qpmc_a18.qspi1_sclk */
 127                         0xb8 (PIN_INPUT_PULLUP | MUX_MODE1)  /* gpmc_cs2.qspi1_cs0 */
 128                         0xbc (PIN_INPUT_PULLUP | MUX_MODE1)  /* gpmc_cs3.qspi1_cs1 */
 129                 >;
 130         };
 131
 132         usb1_pins: pinmux_usb1_pins {
 133                 pinctrl-single,pins = <
 134                         0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
 135                 >;
 136         };
 137
 138         usb2_pins: pinmux_usb2_pins {
 139                 pinctrl-single,pins = <
 140                         0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
 141                 >;
 142         };
 143
 144         nand_flash_x16: nand_flash_x16 {
 145                 /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
 146                  * So NAND flash requires following switch settings:
 147                  * SW5.9 (GPMC_WPN) = LOW
 148                  * SW5.1 (NAND_BOOTn) = HIGH */
 149                 pinctrl-single,pins = <
 150                         0x0     (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad0     */
 151                         0x4     (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad1     */
 152                         0x8     (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad2     */
 153                         0xc     (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad3     */
 154                         0x10    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad4     */
 155                         0x14    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad5     */
 156                         0x18    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad6     */
 157                         0x1c    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad7     */
 158                         0x20    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad8     */
 159                         0x24    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad9     */
 160                         0x28    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad10    */
 161                         0x2c    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad11    */
 162                         0x30    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad12    */
 163                         0x34    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad13    */
 164                         0x38    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad14    */
 165                         0x3c    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad15    */
 166                         0xd8    (PIN_INPUT_PULLUP  | MUX_MODE0) /* gpmc_wait0   */
 167                         0xcc    (PIN_OUTPUT | MUX_MODE0)        /* gpmc_wen     */
 168                         0xb4    (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0    */
 169                         0xc4    (PIN_OUTPUT | MUX_MODE0)        /* gpmc_advn_ale */
 170                         0xc8    (PIN_OUTPUT | MUX_MODE0)        /* gpmc_oen_ren  */
 171                         0xd0    (PIN_OUTPUT | MUX_MODE0)        /* gpmc_be0n_cle */
 172                 >;
 173         };
 174 };
 175
 176 &i2c1 {
 177         status = "okay";
 178         pinctrl-names = "default";
 179         pinctrl-0 = <&i2c1_pins>;
 180         clock-frequency = <400000>;
 181
 182         tps659038: tps659038@58 {
 183                 compatible = "ti,tps659038";
 184                 reg = <0x58>;
 185
 186                 tps659038_pmic {
 187                         compatible = "ti,tps659038-pmic";
 188
 189                         regulators {
 190                                 smps123_reg: smps123 {
 191                                         /* VDD_MPU */
 192                                         regulator-name = "smps123";
 193                                         regulator-min-microvolt = < 850000>;
 194                                         regulator-max-microvolt = <1250000>;
 195                                         regulator-always-on;
 196                                         regulator-boot-on;
 197                                 };
 198
 199                                 smps45_reg: smps45 {
 200                                         /* VDD_DSPEVE */
 201                                         regulator-name = "smps45";
 202                                         regulator-min-microvolt = < 850000>;
 203                                         regulator-max-microvolt = <1150000>;
 204                                         regulator-boot-on;
 205                                 };
 206
 207                                 smps6_reg: smps6 {
 208                                         /* VDD_GPU - over VDD_SMPS6 */
 209                                         regulator-name = "smps6";
 210                                         regulator-min-microvolt = <850000>;
 211                                         regulator-max-microvolt = <12500000>;
 212                                         regulator-boot-on;
 213                                 };
 214
 215                                 smps7_reg: smps7 {
 216                                         /* CORE_VDD */
 217                                         regulator-name = "smps7";
 218                                         regulator-min-microvolt = <850000>;
 219                                         regulator-max-microvolt = <1030000>;
 220                                         regulator-always-on;
 221                                         regulator-boot-on;
 222                                 };
 223
 224                                 smps8_reg: smps8 {
 225                                         /* VDD_IVAHD */
 226                                         regulator-name = "smps8";
 227                                         regulator-min-microvolt = < 850000>;
 228                                         regulator-max-microvolt = <1250000>;
 229                                         regulator-boot-on;
 230                                 };
 231
 232                                 smps9_reg: smps9 {
 233                                         /* VDDS1V8 */
 234                                         regulator-name = "smps9";
 235                                         regulator-min-microvolt = <1800000>;
 236                                         regulator-max-microvolt = <1800000>;
 237                                         regulator-always-on;
 238                                         regulator-boot-on;
 239                                 };
 240
 241                                 ldo1_reg: ldo1 {
 242                                         /* LDO1_OUT --> SDIO  */
 243                                         regulator-name = "ldo1";
 244                                         regulator-min-microvolt = <1800000>;
 245                                         regulator-max-microvolt = <3300000>;
 246                                         regulator-boot-on;
 247                                 };
 248
 249                                 ldo2_reg: ldo2 {
 250                                         /* VDD_RTCIO */
 251                                         /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
 252                                         regulator-name = "ldo2";
 253                                         regulator-min-microvolt = <3300000>;
 254                                         regulator-max-microvolt = <3300000>;
 255                                         regulator-boot-on;
 256                                 };
 257
 258                                 ldo3_reg: ldo3 {
 259                                         /* VDDA_1V8_PHY */
 260                                         regulator-name = "ldo3";
 261                                         regulator-min-microvolt = <1800000>;
 262                                         regulator-max-microvolt = <1800000>;
 263                                         regulator-always-on;
 264                                         regulator-boot-on;
 265                                 };
 266
 267                                 ldo9_reg: ldo9 {
 268                                         /* VDD_RTC */
 269                                         regulator-name = "ldo9";
 270                                         regulator-min-microvolt = <1050000>;
 271                                         regulator-max-microvolt = <1050000>;
 272                                         regulator-boot-on;
 273                                 };
 274
 275                                 ldoln_reg: ldoln {
 276                                         /* VDDA_1V8_PLL */
 277                                         regulator-name = "ldoln";
 278                                         regulator-min-microvolt = <1800000>;
 279                                         regulator-max-microvolt = <1800000>;
 280                                         regulator-always-on;
 281                                         regulator-boot-on;
 282                                 };
 283
 284                                 ldousb_reg: ldousb {
 285                                         /* VDDA_3V_USB: VDDA_USBHS33 */
 286                                         regulator-name = "ldousb";
 287                                         regulator-min-microvolt = <3300000>;
 288                                         regulator-max-microvolt = <3300000>;
 289                                         regulator-boot-on;
 290                                 };
 291                         };
 292                 };
 293         };
 294 };
 295
 296 &i2c2 {
 297         status = "okay";
 298         pinctrl-names = "default";
 299         pinctrl-0 = <&i2c2_pins>;
 300         clock-frequency = <400000>;
 301 };
 302
 303 &i2c3 {
 304         status = "okay";
 305         pinctrl-names = "default";
 306         pinctrl-0 = <&i2c3_pins>;
 307         clock-frequency = <400000>;
 308 };
 309
 310 &mcspi1 {
 311         status = "okay";
 312         pinctrl-names = "default";
 313         pinctrl-0 = <&mcspi1_pins>;
 314 };
 315
 316 &mcspi2 {
 317         status = "okay";
 318         pinctrl-names = "default";
 319         pinctrl-0 = <&mcspi2_pins>;
 320 };
 321
 322 &uart1 {
 323         status = "okay";
 324         pinctrl-names = "default";
 325         pinctrl-0 = <&uart1_pins>;
 326         interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
 327                               <&dra7_pmx_core 0x3e0>;
 328 };
 329
 330 &uart2 {
 331         status = "okay";
 332         pinctrl-names = "default";
 333         pinctrl-0 = <&uart2_pins>;
 334 };
 335
 336 &uart3 {
 337         status = "okay";
 338         pinctrl-names = "default";
 339         pinctrl-0 = <&uart3_pins>;
 340 };
 341
 342 &mmc1 {
 343         status = "okay";
 344         vmmc-supply = <&ldo1_reg>;
 345         bus-width = <4>;
 346 };
 347
 348 &mmc2 {
 349         status = "okay";
 350         vmmc-supply = <&mmc2_3v3>;
 351         bus-width = <8>;
 352 };
 353
 354 &cpu0 {
 355         cpu0-supply = <&smps123_reg>;
 356 };
 357
 358 &qspi {
 359         status = "okay";
 360         pinctrl-names = "default";
 361         pinctrl-0 = <&qspi1_pins>;
 362
 363         spi-max-frequency = <48000000>;
 364         m25p80@0 {
 365                 compatible = "s25fl256s1";
 366                 spi-max-frequency = <48000000>;
 367                 reg = <0>;
 368                 spi-tx-bus-width = <1>;
 369                 spi-rx-bus-width = <4>;
 370                 spi-cpol;
 371                 spi-cpha;
 372                 #address-cells = <1>;
 373                 #size-cells = <1>;
 374
 375                 /* MTD partition table.
 376                  * The ROM checks the first four physical blocks
 377                  * for a valid file to boot and the flash here is
 378                  * 64KiB block size.
 379                  */
 380                 partition@0 {
 381                         label = "QSPI.SPL";
 382                         reg = <0x00000000 0x000010000>;
 383                 };
 384                 partition@1 {
 385                         label = "QSPI.SPL.backup1";
 386                         reg = <0x00010000 0x00010000>;
 387                 };
 388                 partition@2 {
 389                         label = "QSPI.SPL.backup2";
 390                         reg = <0x00020000 0x00010000>;
 391                 };
 392                 partition@3 {
 393                         label = "QSPI.SPL.backup3";
 394                         reg = <0x00030000 0x00010000>;
 395                 };
 396                 partition@4 {
 397                         label = "QSPI.u-boot";
 398                         reg = <0x00040000 0x00100000>;
 399                 };
 400                 partition@5 {
 401                         label = "QSPI.u-boot-spl-os";
 402                         reg = <0x00140000 0x00010000>;
 403                 };
 404                 partition@6 {
 405                         label = "QSPI.u-boot-env";
 406                         reg = <0x00150000 0x00010000>;
 407                 };
 408                 partition@7 {
 409                         label = "QSPI.u-boot-env.backup1";
 410                         reg = <0x00160000 0x0010000>;
 411                 };
 412                 partition@8 {
 413                         label = "QSPI.kernel";
 414                         reg = <0x00170000 0x0800000>;
 415                 };
 416                 partition@9 {
 417                         label = "QSPI.file-system";
 418                         reg = <0x00970000 0x01690000>;
 419                 };
 420         };
 421 };
 422
 423 &usb1 {
 424         dr_mode = "peripheral";
 425         pinctrl-names = "default";
 426         pinctrl-0 = <&usb1_pins>;
 427 };
 428
 429 &usb2 {
 430         dr_mode = "host";
 431         pinctrl-names = "default";
 432         pinctrl-0 = <&usb2_pins>;
 433 };
 434
 435 &elm {
 436         status = "okay";
 437 };
 438
 439 &gpmc {
 440         status = "okay";
 441         pinctrl-names = "default";
 442         pinctrl-0 = <&nand_flash_x16>;
 443         ranges = <0 0 0 0x01000000>;    /* minimum GPMC partition = 16MB */
 444         nand@0,0 {
 445                 reg = <0 0 4>;          /* device IO registers */
 446                 ti,nand-ecc-opt = "bch8";
 447                 ti,elm-id = <&elm>;
 448                 nand-bus-width = <16>;
 449                 gpmc,device-width = <2>;
 450                 gpmc,sync-clk-ps = <0>;
 451                 gpmc,cs-on-ns = <0>;
 452                 gpmc,cs-rd-off-ns = <80>;
 453                 gpmc,cs-wr-off-ns = <80>;
 454                 gpmc,adv-on-ns = <0>;
 455                 gpmc,adv-rd-off-ns = <60>;
 456                 gpmc,adv-wr-off-ns = <60>;
 457                 gpmc,we-on-ns = <10>;
 458                 gpmc,we-off-ns = <50>;
 459                 gpmc,oe-on-ns = <4>;
 460                 gpmc,oe-off-ns = <40>;
 461                 gpmc,access-ns = <40>;
 462                 gpmc,wr-access-ns = <80>;
 463                 gpmc,rd-cycle-ns = <80>;
 464                 gpmc,wr-cycle-ns = <80>;
 465                 gpmc,bus-turnaround-ns = <0>;
 466                 gpmc,cycle2cycle-delay-ns = <0>;
 467                 gpmc,clk-activation-ns = <0>;
 468                 gpmc,wait-monitoring-ns = <0>;
 469                 gpmc,wr-data-mux-bus-ns = <0>;
 470                 /* MTD partition table */
 471                 /* All SPL-* partitions are sized to minimal length
 472                  * which can be independently programmable. For
 473                  * NAND flash this is equal to size of erase-block */
 474                 #address-cells = <1>;
 475                 #size-cells = <1>;
 476                 partition@0 {
 477                         label = "NAND.SPL";
 478                         reg = <0x00000000 0x000020000>;
 479                 };
 480                 partition@1 {
 481                         label = "NAND.SPL.backup1";
 482                         reg = <0x00020000 0x00020000>;
 483                 };
 484                 partition@2 {
 485                         label = "NAND.SPL.backup2";
 486                         reg = <0x00040000 0x00020000>;
 487                 };
 488                 partition@3 {
 489                         label = "NAND.SPL.backup3";
 490                         reg = <0x00060000 0x00020000>;
 491                 };
 492                 partition@4 {
 493                         label = "NAND.u-boot-spl-os";
 494                         reg = <0x00080000 0x00040000>;
 495                 };
 496                 partition@5 {
 497                         label = "NAND.u-boot";
 498                         reg = <0x000c0000 0x00100000>;
 499                 };
 500                 partition@6 {
 501                         label = "NAND.u-boot-env";
 502                         reg = <0x001c0000 0x00020000>;
 503                 };
 504                 partition@7 {
 505                         label = "NAND.u-boot-env.backup1";
 506                         reg = <0x001e0000 0x00020000>;
 507                 };
 508                 partition@8 {
 509                         label = "NAND.kernel";
 510                         reg = <0x00200000 0x00800000>;
 511                 };
 512                 partition@9 {
 513                         label = "NAND.file-system";
 514                         reg = <0x00a00000 0x0f600000>;
 515                 };
 516         };
 517 };
 518
 519 &usb2_phy1 {
 520         phy-supply = <&ldousb_reg>;
 521 };
 522
 523 &usb2_phy2 {
 524         phy-supply = <&ldousb_reg>;
 525 };
 526
 527 &gpio7 {
 528         ti,no-reset-on-init;
 529         ti,no-idle-on-init;
 530 };