arch/arm/boot/dts/berlin2cd.dtsi

   1 /*
   2  * Device Tree Include file for Marvell Armada 1500-mini (Berlin BG2CD) SoC
   3  *
   4  * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
   5  *
   6  * based on GPL'ed 2.6 kernel sources
   7  *  (c) Marvell International Ltd.
   8  *
   9  * This file is licensed under the terms of the GNU General Public
  10  * License version 2.  This program is licensed "as is" without any
  11  * warranty of any kind, whether express or implied.
  12  */
  13
  14 #include "skeleton.dtsi"
  15 #include <dt-bindings/clock/berlin2.h>
  16 #include <dt-bindings/interrupt-controller/arm-gic.h>
  17
  18 / {
  19         model = "Marvell Armada 1500-mini (BG2CD) SoC";
  20         compatible = "marvell,berlin2cd", "marvell,berlin";
  21
  22         cpus {
  23                 #address-cells = <1>;
  24                 #size-cells = <0>;
  25
  26                 cpu@0 {
  27                         compatible = "arm,cortex-a9";
  28                         device_type = "cpu";
  29                         next-level-cache = <&l2>;
  30                         reg = <0>;
  31                 };
  32         };
  33
  34         refclk: oscillator {
  35                 compatible = "fixed-clock";
  36                 #clock-cells = <0>;
  37                 clock-frequency = <25000000>;
  38         };
  39
  40         soc {
  41                 compatible = "simple-bus";
  42                 #address-cells = <1>;
  43                 #size-cells = <1>;
  44                 interrupt-parent = <&gic>;
  45
  46                 ranges = <0 0xf7000000 0x1000000>;
  47
  48                 l2: l2-cache-controller@ac0000 {
  49                         compatible = "arm,pl310-cache";
  50                         reg = <0xac0000 0x1000>;
  51                         cache-unified;
  52                         cache-level = <2>;
  53                 };
  54
  55                 gic: interrupt-controller@ad1000 {
  56                         compatible = "arm,cortex-a9-gic";
  57                         reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
  58                         interrupt-controller;
  59                         #interrupt-cells = <3>;
  60                 };
  61
  62                 local-timer@ad0600 {
  63                         compatible = "arm,cortex-a9-twd-timer";
  64                         reg = <0xad0600 0x20>;
  65                         interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
  66                         clocks = <&chip CLKID_TWD>;
  67                 };
  68
  69                 apb@e80000 {
  70                         compatible = "simple-bus";
  71                         #address-cells = <1>;
  72                         #size-cells = <1>;
  73
  74                         ranges = <0 0xe80000 0x10000>;
  75                         interrupt-parent = <&aic>;
  76
  77                         gpio0: gpio@0400 {
  78                                 compatible = "snps,dw-apb-gpio";
  79                                 reg = <0x0400 0x400>;
  80                                 #address-cells = <1>;
  81                                 #size-cells = <0>;
  82
  83                                 porta: gpio-port@0 {
  84                                         compatible = "snps,dw-apb-gpio-port";
  85                                         gpio-controller;
  86                                         #gpio-cells = <2>;
  87                                         snps,nr-gpios = <8>;
  88                                         reg = <0>;
  89                                         interrupt-controller;
  90                                         #interrupt-cells = <2>;
  91                                         interrupts = <0>;
  92                                 };
  93                         };
  94
  95                         gpio1: gpio@0800 {
  96                                 compatible = "snps,dw-apb-gpio";
  97                                 reg = <0x0800 0x400>;
  98                                 #address-cells = <1>;
  99                                 #size-cells = <0>;
 100
 101                                 portb: gpio-port@1 {
 102                                         compatible = "snps,dw-apb-gpio-port";
 103                                         gpio-controller;
 104                                         #gpio-cells = <2>;
 105                                         snps,nr-gpios = <8>;
 106                                         reg = <0>;
 107                                         interrupt-controller;
 108                                         #interrupt-cells = <2>;
 109                                         interrupts = <1>;
 110                                 };
 111                         };
 112
 113                         gpio2: gpio@0c00 {
 114                                 compatible = "snps,dw-apb-gpio";
 115                                 reg = <0x0c00 0x400>;
 116                                 #address-cells = <1>;
 117                                 #size-cells = <0>;
 118
 119                                 portc: gpio-port@2 {
 120                                         compatible = "snps,dw-apb-gpio-port";
 121                                         gpio-controller;
 122                                         #gpio-cells = <2>;
 123                                         snps,nr-gpios = <8>;
 124                                         reg = <0>;
 125                                         interrupt-controller;
 126                                         #interrupt-cells = <2>;
 127                                         interrupts = <2>;
 128                                 };
 129                         };
 130
 131                         gpio3: gpio@1000 {
 132                                 compatible = "snps,dw-apb-gpio";
 133                                 reg = <0x1000 0x400>;
 134                                 #address-cells = <1>;
 135                                 #size-cells = <0>;
 136
 137                                 portd: gpio-port@3 {
 138                                         compatible = "snps,dw-apb-gpio-port";
 139                                         gpio-controller;
 140                                         #gpio-cells = <2>;
 141                                         snps,nr-gpios = <8>;
 142                                         reg = <0>;
 143                                         interrupt-controller;
 144                                         #interrupt-cells = <2>;
 145                                         interrupts = <3>;
 146                                 };
 147                         };
 148
 149                         timer0: timer@2c00 {
 150                                 compatible = "snps,dw-apb-timer";
 151                                 reg = <0x2c00 0x14>;
 152                                 interrupts = <8>;
 153                                 clocks = <&chip CLKID_CFG>;
 154                                 clock-names = "timer";
 155                                 status = "okay";
 156                         };
 157
 158                         timer1: timer@2c14 {
 159                                 compatible = "snps,dw-apb-timer";
 160                                 reg = <0x2c14 0x14>;
 161                                 interrupts = <9>;
 162                                 clocks = <&chip CLKID_CFG>;
 163                                 clock-names = "timer";
 164                                 status = "okay";
 165                         };
 166
 167                         timer2: timer@2c28 {
 168                                 compatible = "snps,dw-apb-timer";
 169                                 reg = <0x2c28 0x14>;
 170                                 interrupts = <10>;
 171                                 clocks = <&chip CLKID_CFG>;
 172                                 clock-names = "timer";
 173                                 status = "disabled";
 174                         };
 175
 176                         timer3: timer@2c3c {
 177                                 compatible = "snps,dw-apb-timer";
 178                                 reg = <0x2c3c 0x14>;
 179                                 interrupts = <11>;
 180                                 clocks = <&chip CLKID_CFG>;
 181                                 clock-names = "timer";
 182                                 status = "disabled";
 183                         };
 184
 185                         timer4: timer@2c50 {
 186                                 compatible = "snps,dw-apb-timer";
 187                                 reg = <0x2c50 0x14>;
 188                                 interrupts = <12>;
 189                                 clocks = <&chip CLKID_CFG>;
 190                                 clock-names = "timer";
 191                                 status = "disabled";
 192                         };
 193
 194                         timer5: timer@2c64 {
 195                                 compatible = "snps,dw-apb-timer";
 196                                 reg = <0x2c64 0x14>;
 197                                 interrupts = <13>;
 198                                 clocks = <&chip CLKID_CFG>;
 199                                 clock-names = "timer";
 200                                 status = "disabled";
 201                         };
 202
 203                         timer6: timer@2c78 {
 204                                 compatible = "snps,dw-apb-timer";
 205                                 reg = <0x2c78 0x14>;
 206                                 interrupts = <14>;
 207                                 clocks = <&chip CLKID_CFG>;
 208                                 clock-names = "timer";
 209                                 status = "disabled";
 210                         };
 211
 212                         timer7: timer@2c8c {
 213                                 compatible = "snps,dw-apb-timer";
 214                                 reg = <0x2c8c 0x14>;
 215                                 interrupts = <15>;
 216                                 clocks = <&chip CLKID_CFG>;
 217                                 clock-names = "timer";
 218                                 status = "disabled";
 219                         };
 220
 221                         aic: interrupt-controller@3000 {
 222                                 compatible = "snps,dw-apb-ictl";
 223                                 reg = <0x3000 0xc00>;
 224                                 interrupt-controller;
 225                                 #interrupt-cells = <1>;
 226                                 interrupt-parent = <&gic>;
 227                                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 228                         };
 229                 };
 230
 231                 chip: chip-control@ea0000 {
 232                         compatible = "marvell,berlin2cd-chip-ctrl";
 233                         #clock-cells = <1>;
 234                         reg = <0xea0000 0x400>;
 235                         clocks = <&refclk>;
 236                         clock-names = "refclk";
 237
 238                         uart0_pmux: uart0-pmux {
 239                                 groups = "G6";
 240                                 function = "uart0";
 241                         };
 242                 };
 243
 244                 apb@fc0000 {
 245                         compatible = "simple-bus";
 246                         #address-cells = <1>;
 247                         #size-cells = <1>;
 248
 249                         ranges = <0 0xfc0000 0x10000>;
 250                         interrupt-parent = <&sic>;
 251
 252                         sm_gpio1: gpio@5000 {
 253                                 compatible = "snps,dw-apb-gpio";
 254                                 reg = <0x5000 0x400>;
 255                                 #address-cells = <1>;
 256                                 #size-cells = <0>;
 257
 258                                 portf: gpio-port@5 {
 259                                         compatible = "snps,dw-apb-gpio-port";
 260                                         gpio-controller;
 261                                         #gpio-cells = <2>;
 262                                         snps,nr-gpios = <8>;
 263                                         reg = <0>;
 264                                 };
 265                         };
 266
 267                         sm_gpio0: gpio@c000 {
 268                                 compatible = "snps,dw-apb-gpio";
 269                                 reg = <0xc000 0x400>;
 270                                 #address-cells = <1>;
 271                                 #size-cells = <0>;
 272
 273                                 porte: gpio-port@4 {
 274                                         compatible = "snps,dw-apb-gpio-port";
 275                                         gpio-controller;
 276                                         #gpio-cells = <2>;
 277                                         snps,nr-gpios = <8>;
 278                                         reg = <0>;
 279                                 };
 280                         };
 281
 282                         uart0: serial@9000 {
 283                                 compatible = "snps,dw-apb-uart";
 284                                 reg = <0x9000 0x100>;
 285                                 reg-shift = <2>;
 286                                 reg-io-width = <1>;
 287                                 interrupts = <8>;
 288                                 clocks = <&refclk>;
 289                                 pinctrl-0 = <&uart0_pmux>;
 290                                 pinctrl-names = "default";
 291                                 status = "disabled";
 292                         };
 293
 294                         uart1: serial@a000 {
 295                                 compatible = "snps,dw-apb-uart";
 296                                 reg = <0xa000 0x100>;
 297                                 reg-shift = <2>;
 298                                 reg-io-width = <1>;
 299                                 interrupts = <9>;
 300                                 clocks = <&refclk>;
 301                                 status = "disabled";
 302                         };
 303
 304                         sysctrl: system-controller@d000 {
 305                                 compatible = "marvell,berlin2cd-system-ctrl";
 306                                 reg = <0xd000 0x100>;
 307                         };
 308
 309                         sic: interrupt-controller@e000 {
 310                                 compatible = "snps,dw-apb-ictl";
 311                                 reg = <0xe000 0x400>;
 312                                 interrupt-controller;
 313                                 #interrupt-cells = <1>;
 314                                 interrupt-parent = <&gic>;
 315                                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 316                         };
 317                 };
 318         };
 319 };