arch/arm/boot/dts/berlin2.dtsi

   1 /*
   2  * Device Tree Include file for Marvell Armada 1500 (Berlin BG2) SoC
   3  *
   4  * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
   5  *
   6  * based on GPL'ed 2.6 kernel sources
   7  *  (c) Marvell International Ltd.
   8  *
   9  * This file is dual-licensed: you can use it either under the terms
  10  * of the GPL or the X11 license, at your option. Note that this dual
  11  * licensing only applies to this file, and not this project as a
  12  * whole.
  13  *
  14  *  a) This file is licensed under the terms of the GNU General Public
  15  *     License version 2. This program is licensed "as is" without any
  16  *     warranty of any kind, whether express or implied.
  17  *
  18  * Or, alternatively,
  19  *
  20  *  b) Permission is hereby granted, free of charge, to any person
  21  *     obtaining a copy of this software and associated documentation
  22  *     files (the "Software"), to deal in the Software without
  23  *     restriction, including without limitation the rights to use,
  24  *     copy, modify, merge, publish, distribute, sublicense, and/or
  25  *     sell copies of the Software, and to permit persons to whom the
  26  *     Software is furnished to do so, subject to the following
  27  *     conditions:
  28  *
  29  *     The above copyright notice and this permission notice shall be
  30  *     included in all copies or substantial portions of the Software.
  31  *
  32  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  33  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  34  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  35  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  36  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  37  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  38  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  39  *     OTHER DEALINGS IN THE SOFTWARE.
  40  */
  41
  42 #include "skeleton.dtsi"
  43 #include <dt-bindings/clock/berlin2.h>
  44 #include <dt-bindings/interrupt-controller/arm-gic.h>
  45
  46 / {
  47         model = "Marvell Armada 1500 (BG2) SoC";
  48         compatible = "marvell,berlin2", "marvell,berlin";
  49
  50         cpus {
  51                 #address-cells = <1>;
  52                 #size-cells = <0>;
  53                 enable-method = "marvell,berlin-smp";
  54
  55                 cpu@0 {
  56                         compatible = "marvell,pj4b";
  57                         device_type = "cpu";
  58                         next-level-cache = <&l2>;
  59                         reg = <0>;
  60                 };
  61
  62                 cpu@1 {
  63                         compatible = "marvell,pj4b";
  64                         device_type = "cpu";
  65                         next-level-cache = <&l2>;
  66                         reg = <1>;
  67                 };
  68         };
  69
  70         refclk: oscillator {
  71                 compatible = "fixed-clock";
  72                 #clock-cells = <0>;
  73                 clock-frequency = <25000000>;
  74         };
  75
  76         soc {
  77                 compatible = "simple-bus";
  78                 #address-cells = <1>;
  79                 #size-cells = <1>;
  80                 interrupt-parent = <&gic>;
  81
  82                 ranges = <0 0xf7000000 0x1000000>;
  83
  84                 sdhci0: sdhci@ab0000 {
  85                         compatible = "mrvl,pxav3-mmc";
  86                         reg = <0xab0000 0x200>;
  87                         clocks = <&chip_clk CLKID_SDIO0XIN>, <&chip_clk CLKID_SDIO0>;
  88                         clock-names = "io", "core";
  89                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
  90                         status = "disabled";
  91                 };
  92
  93                 sdhci1: sdhci@ab0800 {
  94                         compatible = "mrvl,pxav3-mmc";
  95                         reg = <0xab0800 0x200>;
  96                         clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO1>;
  97                         clock-names = "io", "core";
  98                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
  99                         status = "disabled";
 100                 };
 101
 102                 sdhci2: sdhci@ab1000 {
 103                         compatible = "mrvl,pxav3-mmc";
 104                         reg = <0xab1000 0x200>;
 105                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 106                         clocks = <&chip_clk CLKID_NFC_ECC>, <&chip_clk CLKID_NFC>;
 107                         clock-names = "io", "core";
 108                         pinctrl-0 = <&emmc_pmux>;
 109                         pinctrl-names = "default";
 110                         status = "disabled";
 111                 };
 112
 113                 l2: l2-cache-controller@ac0000 {
 114                         compatible = "marvell,tauros3-cache", "arm,pl310-cache";
 115                         reg = <0xac0000 0x1000>;
 116                         cache-unified;
 117                         cache-level = <2>;
 118                 };
 119
 120                 scu: snoop-control-unit@ad0000 {
 121                         compatible = "arm,cortex-a9-scu";
 122                         reg = <0xad0000 0x58>;
 123                 };
 124
 125                 gic: interrupt-controller@ad1000 {
 126                         compatible = "arm,cortex-a9-gic";
 127                         reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
 128                         interrupt-controller;
 129                         #interrupt-cells = <3>;
 130                 };
 131
 132                 local-timer@ad0600 {
 133                         compatible = "arm,cortex-a9-twd-timer";
 134                         reg = <0xad0600 0x20>;
 135                         interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 136                         clocks = <&chip_clk CLKID_TWD>;
 137                 };
 138
 139                 eth1: ethernet@b90000 {
 140                         compatible = "marvell,pxa168-eth";
 141                         reg = <0xb90000 0x10000>;
 142                         clocks = <&chip_clk CLKID_GETH1>;
 143                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 144                         /* set by bootloader */
 145                         local-mac-address = [00 00 00 00 00 00];
 146                         #address-cells = <1>;
 147                         #size-cells = <0>;
 148                         phy-connection-type = "mii";
 149                         phy-handle = <&ethphy1>;
 150                         status = "disabled";
 151
 152                         ethphy1: ethernet-phy@0 {
 153                                 reg = <0>;
 154                         };
 155                 };
 156
 157                 cpu-ctrl@dd0000 {
 158                         compatible = "marvell,berlin-cpu-ctrl";
 159                         reg = <0xdd0000 0x10000>;
 160                 };
 161
 162                 eth0: ethernet@e50000 {
 163                         compatible = "marvell,pxa168-eth";
 164                         reg = <0xe50000 0x10000>;
 165                         clocks = <&chip_clk CLKID_GETH0>;
 166                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 167                         /* set by bootloader */
 168                         local-mac-address = [00 00 00 00 00 00];
 169                         #address-cells = <1>;
 170                         #size-cells = <0>;
 171                         phy-connection-type = "mii";
 172                         phy-handle = <&ethphy0>;
 173                         status = "disabled";
 174
 175                         ethphy0: ethernet-phy@0 {
 176                                 reg = <0>;
 177                         };
 178                 };
 179
 180                 apb@e80000 {
 181                         compatible = "simple-bus";
 182                         #address-cells = <1>;
 183                         #size-cells = <1>;
 184
 185                         ranges = <0 0xe80000 0x10000>;
 186                         interrupt-parent = <&aic>;
 187
 188                         gpio0: gpio@0400 {
 189                                 compatible = "snps,dw-apb-gpio";
 190                                 reg = <0x0400 0x400>;
 191                                 #address-cells = <1>;
 192                                 #size-cells = <0>;
 193
 194                                 porta: gpio-port@0 {
 195                                         compatible = "snps,dw-apb-gpio-port";
 196                                         gpio-controller;
 197                                         #gpio-cells = <2>;
 198                                         snps,nr-gpios = <8>;
 199                                         reg = <0>;
 200                                         interrupt-controller;
 201                                         #interrupt-cells = <2>;
 202                                         interrupts = <0>;
 203                                 };
 204                         };
 205
 206                         gpio1: gpio@0800 {
 207                                 compatible = "snps,dw-apb-gpio";
 208                                 reg = <0x0800 0x400>;
 209                                 #address-cells = <1>;
 210                                 #size-cells = <0>;
 211
 212                                 portb: gpio-port@1 {
 213                                         compatible = "snps,dw-apb-gpio-port";
 214                                         gpio-controller;
 215                                         #gpio-cells = <2>;
 216                                         snps,nr-gpios = <8>;
 217                                         reg = <0>;
 218                                         interrupt-controller;
 219                                         #interrupt-cells = <2>;
 220                                         interrupts = <1>;
 221                                 };
 222                         };
 223
 224                         gpio2: gpio@0c00 {
 225                                 compatible = "snps,dw-apb-gpio";
 226                                 reg = <0x0c00 0x400>;
 227                                 #address-cells = <1>;
 228                                 #size-cells = <0>;
 229
 230                                 portc: gpio-port@2 {
 231                                         compatible = "snps,dw-apb-gpio-port";
 232                                         gpio-controller;
 233                                         #gpio-cells = <2>;
 234                                         snps,nr-gpios = <8>;
 235                                         reg = <0>;
 236                                         interrupt-controller;
 237                                         #interrupt-cells = <2>;
 238                                         interrupts = <2>;
 239                                 };
 240                         };
 241
 242                         gpio3: gpio@1000 {
 243                                 compatible = "snps,dw-apb-gpio";
 244                                 reg = <0x1000 0x400>;
 245                                 #address-cells = <1>;
 246                                 #size-cells = <0>;
 247
 248                                 portd: gpio-port@3 {
 249                                         compatible = "snps,dw-apb-gpio-port";
 250                                         gpio-controller;
 251                                         #gpio-cells = <2>;
 252                                         snps,nr-gpios = <8>;
 253                                         reg = <0>;
 254                                         interrupt-controller;
 255                                         #interrupt-cells = <2>;
 256                                         interrupts = <3>;
 257                                 };
 258                         };
 259
 260                         timer0: timer@2c00 {
 261                                 compatible = "snps,dw-apb-timer";
 262                                 reg = <0x2c00 0x14>;
 263                                 interrupts = <8>;
 264                                 clocks = <&chip_clk CLKID_CFG>;
 265                                 clock-names = "timer";
 266                                 status = "okay";
 267                         };
 268
 269                         timer1: timer@2c14 {
 270                                 compatible = "snps,dw-apb-timer";
 271                                 reg = <0x2c14 0x14>;
 272                                 interrupts = <9>;
 273                                 clocks = <&chip_clk CLKID_CFG>;
 274                                 clock-names = "timer";
 275                                 status = "okay";
 276                         };
 277
 278                         timer2: timer@2c28 {
 279                                 compatible = "snps,dw-apb-timer";
 280                                 reg = <0x2c28 0x14>;
 281                                 interrupts = <10>;
 282                                 clocks = <&chip_clk CLKID_CFG>;
 283                                 clock-names = "timer";
 284                                 status = "disabled";
 285                         };
 286
 287                         timer3: timer@2c3c {
 288                                 compatible = "snps,dw-apb-timer";
 289                                 reg = <0x2c3c 0x14>;
 290                                 interrupts = <11>;
 291                                 clocks = <&chip_clk CLKID_CFG>;
 292                                 clock-names = "timer";
 293                                 status = "disabled";
 294                         };
 295
 296                         timer4: timer@2c50 {
 297                                 compatible = "snps,dw-apb-timer";
 298                                 reg = <0x2c50 0x14>;
 299                                 interrupts = <12>;
 300                                 clocks = <&chip_clk CLKID_CFG>;
 301                                 clock-names = "timer";
 302                                 status = "disabled";
 303                         };
 304
 305                         timer5: timer@2c64 {
 306                                 compatible = "snps,dw-apb-timer";
 307                                 reg = <0x2c64 0x14>;
 308                                 interrupts = <13>;
 309                                 clocks = <&chip_clk CLKID_CFG>;
 310                                 clock-names = "timer";
 311                                 status = "disabled";
 312                         };
 313
 314                         timer6: timer@2c78 {
 315                                 compatible = "snps,dw-apb-timer";
 316                                 reg = <0x2c78 0x14>;
 317                                 interrupts = <14>;
 318                                 clocks = <&chip_clk CLKID_CFG>;
 319                                 clock-names = "timer";
 320                                 status = "disabled";
 321                         };
 322
 323                         timer7: timer@2c8c {
 324                                 compatible = "snps,dw-apb-timer";
 325                                 reg = <0x2c8c 0x14>;
 326                                 interrupts = <15>;
 327                                 clocks = <&chip_clk CLKID_CFG>;
 328                                 clock-names = "timer";
 329                                 status = "disabled";
 330                         };
 331
 332                         aic: interrupt-controller@3000 {
 333                                 compatible = "snps,dw-apb-ictl";
 334                                 reg = <0x3000 0xc00>;
 335                                 interrupt-controller;
 336                                 #interrupt-cells = <1>;
 337                                 interrupt-parent = <&gic>;
 338                                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 339                         };
 340                 };
 341
 342                 ahci: sata@e90000 {
 343                         compatible = "marvell,berlin2-ahci", "generic-ahci";
 344                         reg = <0xe90000 0x1000>;
 345                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 346                         clocks = <&chip_clk CLKID_SATA>;
 347                         #address-cells = <1>;
 348                         #size-cells = <0>;
 349
 350                         sata0: sata-port@0 {
 351                                 reg = <0>;
 352                                 phys = <&sata_phy 0>;
 353                                 status = "disabled";
 354                         };
 355
 356                         sata1: sata-port@1 {
 357                                 reg = <1>;
 358                                 phys = <&sata_phy 1>;
 359                                 status = "disabled";
 360                         };
 361                 };
 362
 363                 sata_phy: phy@e900a0 {
 364                         compatible = "marvell,berlin2-sata-phy";
 365                         reg = <0xe900a0 0x200>;
 366                         clocks = <&chip_clk CLKID_SATA>;
 367                         #address-cells = <1>;
 368                         #size-cells = <0>;
 369                         #phy-cells = <1>;
 370                         status = "disabled";
 371
 372                         sata-phy@0 {
 373                                 reg = <0>;
 374                         };
 375
 376                         sata-phy@1 {
 377                                 reg = <1>;
 378                         };
 379                 };
 380
 381                 chip: chip-control@ea0000 {
 382                         compatible = "simple-mfd", "syscon";
 383                         reg = <0xea0000 0x400>;
 384
 385                         chip_clk: clock {
 386                                 compatible = "marvell,berlin2-clk";
 387                                 #clock-cells = <1>;
 388                                 clocks = <&refclk>;
 389                                 clock-names = "refclk";
 390                         };
 391
 392                         soc_pinctrl: pin-controller {
 393                                 compatible = "marvell,berlin2-soc-pinctrl";
 394
 395                                 emmc_pmux: emmc-pmux {
 396                                         groups = "G26";
 397                                         function = "emmc";
 398                                 };
 399                         };
 400
 401                         chip_rst: reset {
 402                                 compatible = "marvell,berlin2-reset";
 403                                 #reset-cells = <2>;
 404                         };
 405                 };
 406
 407                 apb@fc0000 {
 408                         compatible = "simple-bus";
 409                         #address-cells = <1>;
 410                         #size-cells = <1>;
 411
 412                         ranges = <0 0xfc0000 0x10000>;
 413                         interrupt-parent = <&sic>;
 414
 415                         sm_gpio1: gpio@5000 {
 416                                 compatible = "snps,dw-apb-gpio";
 417                                 reg = <0x5000 0x400>;
 418                                 #address-cells = <1>;
 419                                 #size-cells = <0>;
 420
 421                                 portf: gpio-port@5 {
 422                                         compatible = "snps,dw-apb-gpio-port";
 423                                         gpio-controller;
 424                                         #gpio-cells = <2>;
 425                                         snps,nr-gpios = <8>;
 426                                         reg = <0>;
 427                                 };
 428                         };
 429
 430                         sm_gpio0: gpio@c000 {
 431                                 compatible = "snps,dw-apb-gpio";
 432                                 reg = <0xc000 0x400>;
 433                                 #address-cells = <1>;
 434                                 #size-cells = <0>;
 435
 436                                 porte: gpio-port@4 {
 437                                         compatible = "snps,dw-apb-gpio-port";
 438                                         gpio-controller;
 439                                         #gpio-cells = <2>;
 440                                         snps,nr-gpios = <8>;
 441                                         reg = <0>;
 442                                         interrupt-controller;
 443                                         #interrupt-cells = <2>;
 444                                         interrupts = <11>;
 445                                 };
 446                         };
 447
 448                         uart0: serial@9000 {
 449                                 compatible = "snps,dw-apb-uart";
 450                                 reg = <0x9000 0x100>;
 451                                 reg-shift = <2>;
 452                                 reg-io-width = <1>;
 453                                 interrupts = <8>;
 454                                 clocks = <&refclk>;
 455                                 pinctrl-0 = <&uart0_pmux>;
 456                                 pinctrl-names = "default";
 457                                 status = "disabled";
 458                         };
 459
 460                         uart1: serial@a000 {
 461                                 compatible = "snps,dw-apb-uart";
 462                                 reg = <0xa000 0x100>;
 463                                 reg-shift = <2>;
 464                                 reg-io-width = <1>;
 465                                 interrupts = <9>;
 466                                 clocks = <&refclk>;
 467                                 pinctrl-0 = <&uart1_pmux>;
 468                                 pinctrl-names = "default";
 469                                 status = "disabled";
 470                         };
 471
 472                         uart2: serial@b000 {
 473                                 compatible = "snps,dw-apb-uart";
 474                                 reg = <0xb000 0x100>;
 475                                 reg-shift = <2>;
 476                                 reg-io-width = <1>;
 477                                 interrupts = <10>;
 478                                 clocks = <&refclk>;
 479                                 pinctrl-0 = <&uart2_pmux>;
 480                                 pinctrl-names = "default";
 481                                 status = "disabled";
 482                         };
 483
 484                         sysctrl: system-controller@d000 {
 485                                 compatible = "simple-mfd", "syscon";
 486                                 reg = <0xd000 0x100>;
 487
 488                                 sys_pinctrl: pin-controller {
 489                                         compatible = "marvell,berlin2-system-pinctrl";
 490                                         uart0_pmux: uart0-pmux {
 491                                                 groups = "GSM4";
 492                                                 function = "uart0";
 493                                         };
 494
 495                                         uart1_pmux: uart1-pmux {
 496                                                 groups = "GSM5";
 497                                                 function = "uart1";
 498                                         };
 499                                         uart2_pmux: uart2-pmux {
 500                                                 groups = "GSM3";
 501                                                 function = "uart2";
 502                                         };
 503                                 };
 504                         };
 505
 506                         sic: interrupt-controller@e000 {
 507                                 compatible = "snps,dw-apb-ictl";
 508                                 reg = <0xe000 0x400>;
 509                                 interrupt-controller;
 510                                 #interrupt-cells = <1>;
 511                                 interrupt-parent = <&gic>;
 512                                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 513                         };
 514                 };
 515         };
 516 };