arch/arm/boot/dts/berlin2.dtsi

   1 /*
   2  * Device Tree Include file for Marvell Armada 1500 (Berlin BG2) SoC
   3  *
   4  * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
   5  *
   6  * based on GPL'ed 2.6 kernel sources
   7  *  (c) Marvell International Ltd.
   8  *
   9  * This file is licensed under the terms of the GNU General Public
  10  * License version 2.  This program is licensed "as is" without any
  11  * warranty of any kind, whether express or implied.
  12  */
  13
  14 #include "skeleton.dtsi"
  15 #include <dt-bindings/clock/berlin2.h>
  16 #include <dt-bindings/interrupt-controller/arm-gic.h>
  17
  18 / {
  19         model = "Marvell Armada 1500 (BG2) SoC";
  20         compatible = "marvell,berlin2", "marvell,berlin";
  21
  22         cpus {
  23                 #address-cells = <1>;
  24                 #size-cells = <0>;
  25
  26                 cpu@0 {
  27                         compatible = "marvell,pj4b";
  28                         device_type = "cpu";
  29                         next-level-cache = <&l2>;
  30                         reg = <0>;
  31                 };
  32
  33                 cpu@1 {
  34                         compatible = "marvell,pj4b";
  35                         device_type = "cpu";
  36                         next-level-cache = <&l2>;
  37                         reg = <1>;
  38                 };
  39         };
  40
  41         refclk: oscillator {
  42                 compatible = "fixed-clock";
  43                 #clock-cells = <0>;
  44                 clock-frequency = <25000000>;
  45         };
  46
  47         soc {
  48                 compatible = "simple-bus";
  49                 #address-cells = <1>;
  50                 #size-cells = <1>;
  51                 interrupt-parent = <&gic>;
  52
  53                 ranges = <0 0xf7000000 0x1000000>;
  54
  55                 l2: l2-cache-controller@ac0000 {
  56                         compatible = "marvell,tauros3-cache", "arm,pl310-cache";
  57                         reg = <0xac0000 0x1000>;
  58                         cache-unified;
  59                         cache-level = <2>;
  60                 };
  61
  62                 scu: snoop-control-unit@ad0000 {
  63                         compatible = "arm,cortex-a9-scu";
  64                         reg = <0xad0000 0x58>;
  65                 };
  66
  67                 gic: interrupt-controller@ad1000 {
  68                         compatible = "arm,cortex-a9-gic";
  69                         reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
  70                         interrupt-controller;
  71                         #interrupt-cells = <3>;
  72                 };
  73
  74                 local-timer@ad0600 {
  75                         compatible = "arm,cortex-a9-twd-timer";
  76                         reg = <0xad0600 0x20>;
  77                         interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
  78                         clocks = <&chip CLKID_TWD>;
  79                 };
  80
  81                 apb@e80000 {
  82                         compatible = "simple-bus";
  83                         #address-cells = <1>;
  84                         #size-cells = <1>;
  85
  86                         ranges = <0 0xe80000 0x10000>;
  87                         interrupt-parent = <&aic>;
  88
  89                         gpio0: gpio@0400 {
  90                                 compatible = "snps,dw-apb-gpio";
  91                                 reg = <0x0400 0x400>;
  92                                 #address-cells = <1>;
  93                                 #size-cells = <0>;
  94
  95                                 porta: gpio-port@0 {
  96                                         compatible = "snps,dw-apb-gpio-port";
  97                                         gpio-controller;
  98                                         #gpio-cells = <2>;
  99                                         snps,nr-gpios = <8>;
 100                                         reg = <0>;
 101                                         interrupt-controller;
 102                                         #interrupt-cells = <2>;
 103                                         interrupts = <0>;
 104                                 };
 105                         };
 106
 107                         gpio1: gpio@0800 {
 108                                 compatible = "snps,dw-apb-gpio";
 109                                 reg = <0x0800 0x400>;
 110                                 #address-cells = <1>;
 111                                 #size-cells = <0>;
 112
 113                                 portb: gpio-port@1 {
 114                                         compatible = "snps,dw-apb-gpio-port";
 115                                         gpio-controller;
 116                                         #gpio-cells = <2>;
 117                                         snps,nr-gpios = <8>;
 118                                         reg = <0>;
 119                                         interrupt-controller;
 120                                         #interrupt-cells = <2>;
 121                                         interrupts = <1>;
 122                                 };
 123                         };
 124
 125                         gpio2: gpio@0c00 {
 126                                 compatible = "snps,dw-apb-gpio";
 127                                 reg = <0x0c00 0x400>;
 128                                 #address-cells = <1>;
 129                                 #size-cells = <0>;
 130
 131                                 portc: gpio-port@2 {
 132                                         compatible = "snps,dw-apb-gpio-port";
 133                                         gpio-controller;
 134                                         #gpio-cells = <2>;
 135                                         snps,nr-gpios = <8>;
 136                                         reg = <0>;
 137                                         interrupt-controller;
 138                                         #interrupt-cells = <2>;
 139                                         interrupts = <2>;
 140                                 };
 141                         };
 142
 143                         gpio3: gpio@1000 {
 144                                 compatible = "snps,dw-apb-gpio";
 145                                 reg = <0x1000 0x400>;
 146                                 #address-cells = <1>;
 147                                 #size-cells = <0>;
 148
 149                                 portd: gpio-port@3 {
 150                                         compatible = "snps,dw-apb-gpio-port";
 151                                         gpio-controller;
 152                                         #gpio-cells = <2>;
 153                                         snps,nr-gpios = <8>;
 154                                         reg = <0>;
 155                                         interrupt-controller;
 156                                         #interrupt-cells = <2>;
 157                                         interrupts = <3>;
 158                                 };
 159                         };
 160
 161                         timer0: timer@2c00 {
 162                                 compatible = "snps,dw-apb-timer";
 163                                 reg = <0x2c00 0x14>;
 164                                 interrupts = <8>;
 165                                 clocks = <&chip CLKID_CFG>;
 166                                 clock-names = "timer";
 167                                 status = "okay";
 168                         };
 169
 170                         timer1: timer@2c14 {
 171                                 compatible = "snps,dw-apb-timer";
 172                                 reg = <0x2c14 0x14>;
 173                                 interrupts = <9>;
 174                                 clocks = <&chip CLKID_CFG>;
 175                                 clock-names = "timer";
 176                                 status = "okay";
 177                         };
 178
 179                         timer2: timer@2c28 {
 180                                 compatible = "snps,dw-apb-timer";
 181                                 reg = <0x2c28 0x14>;
 182                                 interrupts = <10>;
 183                                 clocks = <&chip CLKID_CFG>;
 184                                 clock-names = "timer";
 185                                 status = "disabled";
 186                         };
 187
 188                         timer3: timer@2c3c {
 189                                 compatible = "snps,dw-apb-timer";
 190                                 reg = <0x2c3c 0x14>;
 191                                 interrupts = <11>;
 192                                 clocks = <&chip CLKID_CFG>;
 193                                 clock-names = "timer";
 194                                 status = "disabled";
 195                         };
 196
 197                         timer4: timer@2c50 {
 198                                 compatible = "snps,dw-apb-timer";
 199                                 reg = <0x2c50 0x14>;
 200                                 interrupts = <12>;
 201                                 clocks = <&chip CLKID_CFG>;
 202                                 clock-names = "timer";
 203                                 status = "disabled";
 204                         };
 205
 206                         timer5: timer@2c64 {
 207                                 compatible = "snps,dw-apb-timer";
 208                                 reg = <0x2c64 0x14>;
 209                                 interrupts = <13>;
 210                                 clocks = <&chip CLKID_CFG>;
 211                                 clock-names = "timer";
 212                                 status = "disabled";
 213                         };
 214
 215                         timer6: timer@2c78 {
 216                                 compatible = "snps,dw-apb-timer";
 217                                 reg = <0x2c78 0x14>;
 218                                 interrupts = <14>;
 219                                 clocks = <&chip CLKID_CFG>;
 220                                 clock-names = "timer";
 221                                 status = "disabled";
 222                         };
 223
 224                         timer7: timer@2c8c {
 225                                 compatible = "snps,dw-apb-timer";
 226                                 reg = <0x2c8c 0x14>;
 227                                 interrupts = <15>;
 228                                 clocks = <&chip CLKID_CFG>;
 229                                 clock-names = "timer";
 230                                 status = "disabled";
 231                         };
 232
 233                         aic: interrupt-controller@3000 {
 234                                 compatible = "snps,dw-apb-ictl";
 235                                 reg = <0x3000 0xc00>;
 236                                 interrupt-controller;
 237                                 #interrupt-cells = <1>;
 238                                 interrupt-parent = <&gic>;
 239                                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 240                         };
 241                 };
 242
 243                 chip: chip-control@ea0000 {
 244                         compatible = "marvell,berlin2-chip-ctrl";
 245                         #clock-cells = <1>;
 246                         reg = <0xea0000 0x400>;
 247                         clocks = <&refclk>;
 248                         clock-names = "refclk";
 249                 };
 250
 251                 apb@fc0000 {
 252                         compatible = "simple-bus";
 253                         #address-cells = <1>;
 254                         #size-cells = <1>;
 255
 256                         ranges = <0 0xfc0000 0x10000>;
 257                         interrupt-parent = <&sic>;
 258
 259                         sm_gpio1: gpio@5000 {
 260                                 compatible = "snps,dw-apb-gpio";
 261                                 reg = <0x5000 0x400>;
 262                                 #address-cells = <1>;
 263                                 #size-cells = <0>;
 264
 265                                 portf: gpio-port@5 {
 266                                         compatible = "snps,dw-apb-gpio-port";
 267                                         gpio-controller;
 268                                         #gpio-cells = <2>;
 269                                         snps,nr-gpios = <8>;
 270                                         reg = <0>;
 271                                 };
 272                         };
 273
 274                         sm_gpio0: gpio@c000 {
 275                                 compatible = "snps,dw-apb-gpio";
 276                                 reg = <0xc000 0x400>;
 277                                 #address-cells = <1>;
 278                                 #size-cells = <0>;
 279
 280                                 porte: gpio-port@4 {
 281                                         compatible = "snps,dw-apb-gpio-port";
 282                                         gpio-controller;
 283                                         #gpio-cells = <2>;
 284                                         snps,nr-gpios = <8>;
 285                                         reg = <0>;
 286                                         interrupt-controller;
 287                                         #interrupt-cells = <2>;
 288                                         interrupts = <11>;
 289                                 };
 290                         };
 291
 292                         uart0: serial@9000 {
 293                                 compatible = "snps,dw-apb-uart";
 294                                 reg = <0x9000 0x100>;
 295                                 reg-shift = <2>;
 296                                 reg-io-width = <1>;
 297                                 interrupts = <8>;
 298                                 clocks = <&refclk>;
 299                                 pinctrl-0 = <&uart0_pmux>;
 300                                 pinctrl-names = "default";
 301                                 status = "disabled";
 302                         };
 303
 304                         uart1: serial@a000 {
 305                                 compatible = "snps,dw-apb-uart";
 306                                 reg = <0xa000 0x100>;
 307                                 reg-shift = <2>;
 308                                 reg-io-width = <1>;
 309                                 interrupts = <9>;
 310                                 clocks = <&refclk>;
 311                                 pinctrl-0 = <&uart1_pmux>;
 312                                 pinctrl-names = "default";
 313                                 status = "disabled";
 314                         };
 315
 316                         uart2: serial@b000 {
 317                                 compatible = "snps,dw-apb-uart";
 318                                 reg = <0xb000 0x100>;
 319                                 reg-shift = <2>;
 320                                 reg-io-width = <1>;
 321                                 interrupts = <10>;
 322                                 clocks = <&refclk>;
 323                                 pinctrl-0 = <&uart2_pmux>;
 324                                 pinctrl-names = "default";
 325                                 status = "disabled";
 326                         };
 327
 328                         sysctrl: system-controller@d000 {
 329                                 compatible = "marvell,berlin2-system-ctrl";
 330                                 reg = <0xd000 0x100>;
 331
 332                                 uart0_pmux: uart0-pmux {
 333                                         groups = "GSM4";
 334                                         function = "uart0";
 335                                 };
 336
 337                                 uart1_pmux: uart1-pmux {
 338                                         groups = "GSM5";
 339                                         function = "uart1";
 340                                 };
 341
 342                                 uart2_pmux: uart2-pmux {
 343                                         groups = "GSM3";
 344                                         function = "uart2";
 345                                 };
 346                         };
 347
 348                         sic: interrupt-controller@e000 {
 349                                 compatible = "snps,dw-apb-ictl";
 350                                 reg = <0xe000 0x400>;
 351                                 interrupt-controller;
 352                                 #interrupt-cells = <1>;
 353                                 interrupt-parent = <&gic>;
 354                                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 355                         };
 356                 };
 357         };
 358 };