arch/arm/boot/dts/berlin2.dtsi

   1 /*
   2  * Device Tree Include file for Marvell Armada 1500 (Berlin BG2) SoC
   3  *
   4  * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
   5  *
   6  * based on GPL'ed 2.6 kernel sources
   7  *  (c) Marvell International Ltd.
   8  *
   9  * This file is licensed under the terms of the GNU General Public
  10  * License version 2.  This program is licensed "as is" without any
  11  * warranty of any kind, whether express or implied.
  12  */
  13
  14 #include "skeleton.dtsi"
  15 #include <dt-bindings/interrupt-controller/arm-gic.h>
  16
  17 / {
  18         model = "Marvell Armada 1500 (BG2) SoC";
  19         compatible = "marvell,berlin2", "marvell,berlin";
  20
  21         cpus {
  22                 #address-cells = <1>;
  23                 #size-cells = <0>;
  24
  25                 cpu@0 {
  26                         compatible = "marvell,pj4b";
  27                         device_type = "cpu";
  28                         next-level-cache = <&l2>;
  29                         reg = <0>;
  30                 };
  31
  32                 cpu@1 {
  33                         compatible = "marvell,pj4b";
  34                         device_type = "cpu";
  35                         next-level-cache = <&l2>;
  36                         reg = <1>;
  37                 };
  38         };
  39
  40         clocks {
  41                 smclk: sysmgr-clock {
  42                         compatible = "fixed-clock";
  43                         #clock-cells = <0>;
  44                         clock-frequency = <25000000>;
  45                 };
  46
  47                 cfgclk: cfg-clock {
  48                         compatible = "fixed-clock";
  49                         #clock-cells = <0>;
  50                         clock-frequency = <100000000>;
  51                 };
  52
  53                 sysclk: system-clock {
  54                         compatible = "fixed-clock";
  55                         #clock-cells = <0>;
  56                         clock-frequency = <400000000>;
  57                 };
  58         };
  59
  60         soc {
  61                 compatible = "simple-bus";
  62                 #address-cells = <1>;
  63                 #size-cells = <1>;
  64                 interrupt-parent = <&gic>;
  65
  66                 ranges = <0 0xf7000000 0x1000000>;
  67
  68                 l2: l2-cache-controller@ac0000 {
  69                         compatible = "marvell,tauros3-cache", "arm,pl310-cache";
  70                         reg = <0xac0000 0x1000>;
  71                         cache-unified;
  72                         cache-level = <2>;
  73                 };
  74
  75                 gic: interrupt-controller@ad1000 {
  76                         compatible = "arm,cortex-a9-gic";
  77                         reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
  78                         interrupt-controller;
  79                         #interrupt-cells = <3>;
  80                 };
  81
  82                 local-timer@ad0600 {
  83                         compatible = "arm,cortex-a9-twd-timer";
  84                         reg = <0xad0600 0x20>;
  85                         interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
  86                         clocks = <&sysclk>;
  87                 };
  88
  89                 apb@e80000 {
  90                         compatible = "simple-bus";
  91                         #address-cells = <1>;
  92                         #size-cells = <1>;
  93
  94                         ranges = <0 0xe80000 0x10000>;
  95                         interrupt-parent = <&aic>;
  96
  97                         timer0: timer@2c00 {
  98                                 compatible = "snps,dw-apb-timer";
  99                                 reg = <0x2c00 0x14>;
 100                                 interrupts = <8>;
 101                                 clocks = <&cfgclk>;
 102                                 clock-names = "timer";
 103                                 status = "okay";
 104                         };
 105
 106                         timer1: timer@2c14 {
 107                                 compatible = "snps,dw-apb-timer";
 108                                 reg = <0x2c14 0x14>;
 109                                 interrupts = <9>;
 110                                 clocks = <&cfgclk>;
 111                                 clock-names = "timer";
 112                                 status = "okay";
 113                         };
 114
 115                         timer2: timer@2c28 {
 116                                 compatible = "snps,dw-apb-timer";
 117                                 reg = <0x2c28 0x14>;
 118                                 interrupts = <10>;
 119                                 clocks = <&cfgclk>;
 120                                 clock-names = "timer";
 121                                 status = "disabled";
 122                         };
 123
 124                         timer3: timer@2c3c {
 125                                 compatible = "snps,dw-apb-timer";
 126                                 reg = <0x2c3c 0x14>;
 127                                 interrupts = <11>;
 128                                 clocks = <&cfgclk>;
 129                                 clock-names = "timer";
 130                                 status = "disabled";
 131                         };
 132
 133                         timer4: timer@2c50 {
 134                                 compatible = "snps,dw-apb-timer";
 135                                 reg = <0x2c50 0x14>;
 136                                 interrupts = <12>;
 137                                 clocks = <&cfgclk>;
 138                                 clock-names = "timer";
 139                                 status = "disabled";
 140                         };
 141
 142                         timer5: timer@2c64 {
 143                                 compatible = "snps,dw-apb-timer";
 144                                 reg = <0x2c64 0x14>;
 145                                 interrupts = <13>;
 146                                 clocks = <&cfgclk>;
 147                                 clock-names = "timer";
 148                                 status = "disabled";
 149                         };
 150
 151                         timer6: timer@2c78 {
 152                                 compatible = "snps,dw-apb-timer";
 153                                 reg = <0x2c78 0x14>;
 154                                 interrupts = <14>;
 155                                 clocks = <&cfgclk>;
 156                                 clock-names = "timer";
 157                                 status = "disabled";
 158                         };
 159
 160                         timer7: timer@2c8c {
 161                                 compatible = "snps,dw-apb-timer";
 162                                 reg = <0x2c8c 0x14>;
 163                                 interrupts = <15>;
 164                                 clocks = <&cfgclk>;
 165                                 clock-names = "timer";
 166                                 status = "disabled";
 167                         };
 168
 169                         aic: interrupt-controller@3000 {
 170                                 compatible = "snps,dw-apb-ictl";
 171                                 reg = <0x3000 0xc00>;
 172                                 interrupt-controller;
 173                                 #interrupt-cells = <1>;
 174                                 interrupt-parent = <&gic>;
 175                                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 176                         };
 177                 };
 178
 179                 apb@fc0000 {
 180                         compatible = "simple-bus";
 181                         #address-cells = <1>;
 182                         #size-cells = <1>;
 183
 184                         ranges = <0 0xfc0000 0x10000>;
 185                         interrupt-parent = <&sic>;
 186
 187                         uart0: serial@9000 {
 188                                 compatible = "snps,dw-apb-uart";
 189                                 reg = <0x9000 0x100>;
 190                                 reg-shift = <2>;
 191                                 reg-io-width = <1>;
 192                                 interrupts = <8>;
 193                                 clocks = <&smclk>;
 194                                 status = "disabled";
 195                         };
 196
 197                         uart1: serial@a000 {
 198                                 compatible = "snps,dw-apb-uart";
 199                                 reg = <0xa000 0x100>;
 200                                 reg-shift = <2>;
 201                                 reg-io-width = <1>;
 202                                 interrupts = <9>;
 203                                 clocks = <&smclk>;
 204                                 status = "disabled";
 205                         };
 206
 207                         uart2: serial@b000 {
 208                                 compatible = "snps,dw-apb-uart";
 209                                 reg = <0xb000 0x100>;
 210                                 reg-shift = <2>;
 211                                 reg-io-width = <1>;
 212                                 interrupts = <10>;
 213                                 clocks = <&smclk>;
 214                                 status = "disabled";
 215                         };
 216
 217                         sic: interrupt-controller@e000 {
 218                                 compatible = "snps,dw-apb-ictl";
 219                                 reg = <0xe000 0x400>;
 220                                 interrupt-controller;
 221                                 #interrupt-cells = <1>;
 222                                 interrupt-parent = <&gic>;
 223                                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 224                         };
 225                 };
 226         };
 227 };