arch/arm/boot/dts/bcm283x.dtsi

   1 #include <dt-bindings/pinctrl/bcm2835.h>
   2 #include <dt-bindings/clock/bcm2835.h>
   3 #include <dt-bindings/clock/bcm2835-aux.h>
   4 #include <dt-bindings/gpio/gpio.h>
   5
   6 /* This include file covers the common peripherals and configuration between
   7  * bcm2835 and bcm2836 implementations, leaving the CPU configuration to
   8  * bcm2835.dtsi and bcm2836.dtsi.
   9  */
  10
  11 / {
  12         compatible = "brcm,bcm2835";
  13         model = "BCM2835";
  14         interrupt-parent = <&intc>;
  15         #address-cells = <1>;
  16         #size-cells = <1>;
  17
  18         chosen {
  19                 bootargs = "earlyprintk console=ttyAMA0";
  20         };
  21
  22         soc {
  23                 compatible = "simple-bus";
  24                 #address-cells = <1>;
  25                 #size-cells = <1>;
  26
  27                 timer@7e003000 {
  28                         compatible = "brcm,bcm2835-system-timer";
  29                         reg = <0x7e003000 0x1000>;
  30                         interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
  31                         /* This could be a reference to BCM2835_CLOCK_TIMER,
  32                          * but we don't have the driver using the common clock
  33                          * support yet.
  34                          */
  35                         clock-frequency = <1000000>;
  36                 };
  37
  38                 dma: dma@7e007000 {
  39                         compatible = "brcm,bcm2835-dma";
  40                         reg = <0x7e007000 0xf00>;
  41                         interrupts = <1 16>,
  42                                      <1 17>,
  43                                      <1 18>,
  44                                      <1 19>,
  45                                      <1 20>,
  46                                      <1 21>,
  47                                      <1 22>,
  48                                      <1 23>,
  49                                      <1 24>,
  50                                      <1 25>,
  51                                      <1 26>,
  52                                      /* dma channel 11-14 share one irq */
  53                                      <1 27>,
  54                                      <1 27>,
  55                                      <1 27>,
  56                                      <1 27>,
  57                                      /* unused shared irq for all channels */
  58                                      <1 28>;
  59                         interrupt-names = "dma0",
  60                                           "dma1",
  61                                           "dma2",
  62                                           "dma3",
  63                                           "dma4",
  64                                           "dma5",
  65                                           "dma6",
  66                                           "dma7",
  67                                           "dma8",
  68                                           "dma9",
  69                                           "dma10",
  70                                           "dma11",
  71                                           "dma12",
  72                                           "dma13",
  73                                           "dma14",
  74                                           "dma-shared-all";
  75                         #dma-cells = <1>;
  76                         brcm,dma-channel-mask = <0x7f35>;
  77                 };
  78
  79                 intc: interrupt-controller@7e00b200 {
  80                         compatible = "brcm,bcm2835-armctrl-ic";
  81                         reg = <0x7e00b200 0x200>;
  82                         interrupt-controller;
  83                         #interrupt-cells = <2>;
  84                 };
  85
  86                 watchdog@7e100000 {
  87                         compatible = "brcm,bcm2835-pm-wdt";
  88                         reg = <0x7e100000 0x28>;
  89                 };
  90
  91                 clocks: cprman@7e101000 {
  92                         compatible = "brcm,bcm2835-cprman";
  93                         #clock-cells = <1>;
  94                         reg = <0x7e101000 0x2000>;
  95
  96                         /* CPRMAN derives everything from the platform's
  97                          * oscillator.
  98                          */
  99                         clocks = <&clk_osc>;
 100                 };
 101
 102                 rng@7e104000 {
 103                         compatible = "brcm,bcm2835-rng";
 104                         reg = <0x7e104000 0x10>;
 105                 };
 106
 107                 mailbox: mailbox@7e00b880 {
 108                         compatible = "brcm,bcm2835-mbox";
 109                         reg = <0x7e00b880 0x40>;
 110                         interrupts = <0 1>;
 111                         #mbox-cells = <0>;
 112                 };
 113
 114                 gpio: gpio@7e200000 {
 115                         compatible = "brcm,bcm2835-gpio";
 116                         reg = <0x7e200000 0xb4>;
 117                         /*
 118                          * The GPIO IP block is designed for 3 banks of GPIOs.
 119                          * Each bank has a GPIO interrupt for itself.
 120                          * There is an overall "any bank" interrupt.
 121                          * In order, these are GIC interrupts 17, 18, 19, 20.
 122                          * Since the BCM2835 only has 2 banks, the 2nd bank
 123                          * interrupt output appears to be mirrored onto the
 124                          * 3rd bank's interrupt signal.
 125                          * So, a bank0 interrupt shows up on 17, 20, and
 126                          * a bank1 interrupt shows up on 18, 19, 20!
 127                          */
 128                         interrupts = <2 17>, <2 18>, <2 19>, <2 20>;
 129
 130                         gpio-controller;
 131                         #gpio-cells = <2>;
 132
 133                         interrupt-controller;
 134                         #interrupt-cells = <2>;
 135
 136                         /* Defines pin muxing groups according to
 137                          * BCM2835-ARM-Peripherals.pdf page 102.
 138                          *
 139                          * While each pin can have its mux selected
 140                          * for various functions individually, some
 141                          * groups only make sense to switch to a
 142                          * particular function together.
 143                          */
 144                         dpi_gpio0: dpi_gpio0 {
 145                                 brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11
 146                                              12 13 14 15 16 17 18 19
 147                                              20 21 22 23 24 25 26 27>;
 148                                 brcm,function = <BCM2835_FSEL_ALT2>;
 149                         };
 150                         emmc_gpio22: emmc_gpio22 {
 151                                 brcm,pins = <22 23 24 25 26 27>;
 152                                 brcm,function = <BCM2835_FSEL_ALT3>;
 153                         };
 154                         emmc_gpio34: emmc_gpio34 {
 155                                 brcm,pins = <34 35 36 37 38 39>;
 156                                 brcm,function = <BCM2835_FSEL_ALT3>;
 157                                 brcm,pull = <BCM2835_PUD_OFF
 158                                              BCM2835_PUD_UP
 159                                              BCM2835_PUD_UP
 160                                              BCM2835_PUD_UP
 161                                              BCM2835_PUD_UP
 162                                              BCM2835_PUD_UP>;
 163                         };
 164                         emmc_gpio48: emmc_gpio48 {
 165                                 brcm,pins = <48 49 50 51 52 53>;
 166                                 brcm,function = <BCM2835_FSEL_ALT3>;
 167                         };
 168
 169                         gpclk0_gpio4: gpclk0_gpio4 {
 170                                 brcm,pins = <4>;
 171                                 brcm,function = <BCM2835_FSEL_ALT0>;
 172                         };
 173                         gpclk1_gpio5: gpclk1_gpio5 {
 174                                 brcm,pins = <5>;
 175                                 brcm,function = <BCM2835_FSEL_ALT0>;
 176                         };
 177                         gpclk1_gpio42: gpclk1_gpio42 {
 178                                 brcm,pins = <42>;
 179                                 brcm,function = <BCM2835_FSEL_ALT0>;
 180                         };
 181                         gpclk1_gpio44: gpclk1_gpio44 {
 182                                 brcm,pins = <44>;
 183                                 brcm,function = <BCM2835_FSEL_ALT0>;
 184                         };
 185                         gpclk2_gpio6: gpclk2_gpio6 {
 186                                 brcm,pins = <6>;
 187                                 brcm,function = <BCM2835_FSEL_ALT0>;
 188                         };
 189                         gpclk2_gpio43: gpclk2_gpio43 {
 190                                 brcm,pins = <43>;
 191                                 brcm,function = <BCM2835_FSEL_ALT0>;
 192                         };
 193
 194                         i2c0_gpio0: i2c0_gpio0 {
 195                                 brcm,pins = <0 1>;
 196                                 brcm,function = <BCM2835_FSEL_ALT0>;
 197                         };
 198                         i2c0_gpio32: i2c0_gpio32 {
 199                                 brcm,pins = <32 34>;
 200                                 brcm,function = <BCM2835_FSEL_ALT0>;
 201                         };
 202                         i2c0_gpio44: i2c0_gpio44 {
 203                                 brcm,pins = <44 45>;
 204                                 brcm,function = <BCM2835_FSEL_ALT1>;
 205                         };
 206                         i2c1_gpio2: i2c1_gpio2 {
 207                                 brcm,pins = <2 3>;
 208                                 brcm,function = <BCM2835_FSEL_ALT0>;
 209                         };
 210                         i2c1_gpio44: i2c1_gpio44 {
 211                                 brcm,pins = <44 45>;
 212                                 brcm,function = <BCM2835_FSEL_ALT2>;
 213                         };
 214                         i2c_slave_gpio18: i2c_slave_gpio18 {
 215                                 brcm,pins = <18 19 20 21>;
 216                                 brcm,function = <BCM2835_FSEL_ALT3>;
 217                         };
 218
 219                         jtag_gpio4: jtag_gpio4 {
 220                                 brcm,pins = <4 5 6 12 13>;
 221                                 brcm,function = <BCM2835_FSEL_ALT4>;
 222                         };
 223                         jtag_gpio22: jtag_gpio22 {
 224                                 brcm,pins = <22 23 24 25 26 27>;
 225                                 brcm,function = <BCM2835_FSEL_ALT4>;
 226                         };
 227
 228                         pcm_gpio18: pcm_gpio18 {
 229                                 brcm,pins = <18 19 20 21>;
 230                                 brcm,function = <BCM2835_FSEL_ALT0>;
 231                         };
 232                         pcm_gpio28: pcm_gpio28 {
 233                                 brcm,pins = <28 29 30 31>;
 234                                 brcm,function = <BCM2835_FSEL_ALT2>;
 235                         };
 236
 237                         pwm0_gpio12: pwm0_gpio12 {
 238                                 brcm,pins = <12>;
 239                                 brcm,function = <BCM2835_FSEL_ALT0>;
 240                         };
 241                         pwm0_gpio18: pwm0_gpio18 {
 242                                 brcm,pins = <18>;
 243                                 brcm,function = <BCM2835_FSEL_ALT5>;
 244                         };
 245                         pwm0_gpio40: pwm0_gpio40 {
 246                                 brcm,pins = <40>;
 247                                 brcm,function = <BCM2835_FSEL_ALT0>;
 248                         };
 249                         pwm1_gpio13: pwm1_gpio13 {
 250                                 brcm,pins = <13>;
 251                                 brcm,function = <BCM2835_FSEL_ALT0>;
 252                         };
 253                         pwm1_gpio19: pwm1_gpio19 {
 254                                 brcm,pins = <19>;
 255                                 brcm,function = <BCM2835_FSEL_ALT5>;
 256                         };
 257                         pwm1_gpio41: pwm1_gpio41 {
 258                                 brcm,pins = <41>;
 259                                 brcm,function = <BCM2835_FSEL_ALT0>;
 260                         };
 261                         pwm1_gpio45: pwm1_gpio45 {
 262                                 brcm,pins = <45>;
 263                                 brcm,function = <BCM2835_FSEL_ALT0>;
 264                         };
 265
 266                         sdhost_gpio48: sdhost_gpio48 {
 267                                 brcm,pins = <48 49 50 51 52 53>;
 268                                 brcm,function = <BCM2835_FSEL_ALT0>;
 269                         };
 270
 271                         spi0_gpio7: spi0_gpio7 {
 272                                 brcm,pins = <7 8 9 10 11>;
 273                                 brcm,function = <BCM2835_FSEL_ALT0>;
 274                         };
 275                         spi0_gpio35: spi0_gpio35 {
 276                                 brcm,pins = <35 36 37 38 39>;
 277                                 brcm,function = <BCM2835_FSEL_ALT0>;
 278                         };
 279                         spi1_gpio16: spi1_gpio16 {
 280                                 brcm,pins = <16 17 18 19 20 21>;
 281                                 brcm,function = <BCM2835_FSEL_ALT4>;
 282                         };
 283                         spi2_gpio40: spi2_gpio40 {
 284                                 brcm,pins = <40 41 42 43 44 45>;
 285                                 brcm,function = <BCM2835_FSEL_ALT4>;
 286                         };
 287
 288                         uart0_gpio14: uart0_gpio14 {
 289                                 brcm,pins = <14 15>;
 290                                 brcm,function = <BCM2835_FSEL_ALT0>;
 291                         };
 292                         /* Separate from the uart0_gpio14 group
 293                          * because it conflicts with spi1_gpio16, and
 294                          * people often run uart0 on the two pins
 295                          * without flow contrl.
 296                          */
 297                         uart0_ctsrts_gpio16: uart0_ctsrts_gpio16 {
 298                                 brcm,pins = <16 17>;
 299                                 brcm,function = <BCM2835_FSEL_ALT3>;
 300                         };
 301                         uart0_gpio30: uart0_gpio30 {
 302                                 brcm,pins = <30 31>;
 303                                 brcm,function = <BCM2835_FSEL_ALT3>;
 304                         };
 305                         uart0_ctsrts_gpio32: uart0_ctsrts_gpio32 {
 306                                 brcm,pins = <32 33>;
 307                                 brcm,function = <BCM2835_FSEL_ALT3>;
 308                         };
 309
 310                         uart1_gpio14: uart1_gpio14 {
 311                                 brcm,pins = <14 15>;
 312                                 brcm,function = <BCM2835_FSEL_ALT5>;
 313                         };
 314                         uart1_ctsrts_gpio16: uart1_ctsrts_gpio16 {
 315                                 brcm,pins = <16 17>;
 316                                 brcm,function = <BCM2835_FSEL_ALT5>;
 317                         };
 318                         uart1_gpio32: uart1_gpio32 {
 319                                 brcm,pins = <32 33>;
 320                                 brcm,function = <BCM2835_FSEL_ALT5>;
 321                         };
 322                         uart1_ctsrts_gpio30: uart1_ctsrts_gpio30 {
 323                                 brcm,pins = <30 31>;
 324                                 brcm,function = <BCM2835_FSEL_ALT5>;
 325                         };
 326                         uart1_gpio36: uart1_gpio36 {
 327                                 brcm,pins = <36 37 38 39>;
 328                                 brcm,function = <BCM2835_FSEL_ALT2>;
 329                         };
 330                         uart1_gpio40: uart1_gpio40 {
 331                                 brcm,pins = <40 41>;
 332                                 brcm,function = <BCM2835_FSEL_ALT5>;
 333                         };
 334                         uart1_ctsrts_gpio42: uart1_ctsrts_gpio42 {
 335                                 brcm,pins = <42 43>;
 336                                 brcm,function = <BCM2835_FSEL_ALT5>;
 337                         };
 338                 };
 339
 340                 uart0: serial@7e201000 {
 341                         compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
 342                         reg = <0x7e201000 0x1000>;
 343                         interrupts = <2 25>;
 344                         clocks = <&clocks BCM2835_CLOCK_UART>,
 345                                  <&clocks BCM2835_CLOCK_VPU>;
 346                         clock-names = "uartclk", "apb_pclk";
 347                         arm,primecell-periphid = <0x00241011>;
 348                 };
 349
 350                 i2s: i2s@7e203000 {
 351                         compatible = "brcm,bcm2835-i2s";
 352                         reg = <0x7e203000 0x20>,
 353                               <0x7e101098 0x02>;
 354
 355                         dmas = <&dma 2>,
 356                                <&dma 3>;
 357                         dma-names = "tx", "rx";
 358                         status = "disabled";
 359                 };
 360
 361                 spi: spi@7e204000 {
 362                         compatible = "brcm,bcm2835-spi";
 363                         reg = <0x7e204000 0x1000>;
 364                         interrupts = <2 22>;
 365                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 366                         #address-cells = <1>;
 367                         #size-cells = <0>;
 368                         status = "disabled";
 369                 };
 370
 371                 i2c0: i2c@7e205000 {
 372                         compatible = "brcm,bcm2835-i2c";
 373                         reg = <0x7e205000 0x1000>;
 374                         interrupts = <2 21>;
 375                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 376                         #address-cells = <1>;
 377                         #size-cells = <0>;
 378                         status = "disabled";
 379                 };
 380
 381                 pixelvalve@7e206000 {
 382                         compatible = "brcm,bcm2835-pixelvalve0";
 383                         reg = <0x7e206000 0x100>;
 384                         interrupts = <2 13>; /* pwa0 */
 385                 };
 386
 387                 pixelvalve@7e207000 {
 388                         compatible = "brcm,bcm2835-pixelvalve1";
 389                         reg = <0x7e207000 0x100>;
 390                         interrupts = <2 14>; /* pwa1 */
 391                 };
 392
 393                 thermal: thermal@7e212000 {
 394                         compatible = "brcm,bcm2835-thermal";
 395                         reg = <0x7e212000 0x8>;
 396                         clocks = <&clocks BCM2835_CLOCK_TSENS>;
 397                         status = "disabled";
 398                 };
 399
 400                 aux: aux@0x7e215000 {
 401                         compatible = "brcm,bcm2835-aux";
 402                         #clock-cells = <1>;
 403                         reg = <0x7e215000 0x8>;
 404                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 405                 };
 406
 407                 uart1: serial@7e215040 {
 408                         compatible = "brcm,bcm2835-aux-uart";
 409                         reg = <0x7e215040 0x40>;
 410                         interrupts = <1 29>;
 411                         clocks = <&aux BCM2835_AUX_CLOCK_UART>;
 412                         status = "disabled";
 413                 };
 414
 415                 spi1: spi@7e215080 {
 416                         compatible = "brcm,bcm2835-aux-spi";
 417                         reg = <0x7e215080 0x40>;
 418                         interrupts = <1 29>;
 419                         clocks = <&aux BCM2835_AUX_CLOCK_SPI1>;
 420                         #address-cells = <1>;
 421                         #size-cells = <0>;
 422                         status = "disabled";
 423                 };
 424
 425                 spi2: spi@7e2150c0 {
 426                         compatible = "brcm,bcm2835-aux-spi";
 427                         reg = <0x7e2150c0 0x40>;
 428                         interrupts = <1 29>;
 429                         clocks = <&aux BCM2835_AUX_CLOCK_SPI2>;
 430                         #address-cells = <1>;
 431                         #size-cells = <0>;
 432                         status = "disabled";
 433                 };
 434
 435                 pwm: pwm@7e20c000 {
 436                         compatible = "brcm,bcm2835-pwm";
 437                         reg = <0x7e20c000 0x28>;
 438                         clocks = <&clocks BCM2835_CLOCK_PWM>;
 439                         assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
 440                         assigned-clock-rates = <10000000>;
 441                         #pwm-cells = <2>;
 442                         status = "disabled";
 443                 };
 444
 445                 sdhci: sdhci@7e300000 {
 446                         compatible = "brcm,bcm2835-sdhci";
 447                         reg = <0x7e300000 0x100>;
 448                         interrupts = <2 30>;
 449                         clocks = <&clocks BCM2835_CLOCK_EMMC>;
 450                         status = "disabled";
 451                 };
 452
 453                 hvs@7e400000 {
 454                         compatible = "brcm,bcm2835-hvs";
 455                         reg = <0x7e400000 0x6000>;
 456                         interrupts = <2 1>;
 457                 };
 458
 459                 i2c1: i2c@7e804000 {
 460                         compatible = "brcm,bcm2835-i2c";
 461                         reg = <0x7e804000 0x1000>;
 462                         interrupts = <2 21>;
 463                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 464                         #address-cells = <1>;
 465                         #size-cells = <0>;
 466                         status = "disabled";
 467                 };
 468
 469                 i2c2: i2c@7e805000 {
 470                         compatible = "brcm,bcm2835-i2c";
 471                         reg = <0x7e805000 0x1000>;
 472                         interrupts = <2 21>;
 473                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 474                         #address-cells = <1>;
 475                         #size-cells = <0>;
 476                         status = "disabled";
 477                 };
 478
 479                 pixelvalve@7e807000 {
 480                         compatible = "brcm,bcm2835-pixelvalve2";
 481                         reg = <0x7e807000 0x100>;
 482                         interrupts = <2 10>; /* pixelvalve */
 483                 };
 484
 485                 hdmi: hdmi@7e902000 {
 486                         compatible = "brcm,bcm2835-hdmi";
 487                         reg = <0x7e902000 0x600>,
 488                               <0x7e808000 0x100>;
 489                         interrupts = <2 8>, <2 9>;
 490                         ddc = <&i2c2>;
 491                         clocks = <&clocks BCM2835_PLLH_PIX>,
 492                                  <&clocks BCM2835_CLOCK_HSM>;
 493                         clock-names = "pixel", "hdmi";
 494                         status = "disabled";
 495                 };
 496
 497                 usb: usb@7e980000 {
 498                         compatible = "brcm,bcm2835-usb";
 499                         reg = <0x7e980000 0x10000>;
 500                         interrupts = <1 9>;
 501                         #address-cells = <1>;
 502                         #size-cells = <0>;
 503                         clocks = <&clk_usb>;
 504                         clock-names = "otg";
 505                 };
 506
 507                 v3d: v3d@7ec00000 {
 508                         compatible = "brcm,bcm2835-v3d";
 509                         reg = <0x7ec00000 0x1000>;
 510                         interrupts = <1 10>;
 511                 };
 512
 513                 vc4: gpu {
 514                         compatible = "brcm,bcm2835-vc4";
 515                 };
 516         };
 517
 518         clocks {
 519                 compatible = "simple-bus";
 520                 #address-cells = <1>;
 521                 #size-cells = <0>;
 522
 523                 /* The oscillator is the root of the clock tree. */
 524                 clk_osc: clock@3 {
 525                         compatible = "fixed-clock";
 526                         reg = <3>;
 527                         #clock-cells = <0>;
 528                         clock-output-names = "osc";
 529                         clock-frequency = <19200000>;
 530                 };
 531
 532                 clk_usb: clock@4 {
 533                         compatible = "fixed-clock";
 534                         reg = <4>;
 535                         #clock-cells = <0>;
 536                         clock-output-names = "otg";
 537                         clock-frequency = <480000000>;
 538                 };
 539         };
 540 };