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21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
35 #include <dt-bindings/clock/bcm-nsp.h>
37 #include "skeleton.dtsi"
40 compatible = "brcm,nsp";
41 model = "Broadcom Northstar Plus SoC";
42 interrupt-parent = <&gic>;
50 compatible = "arm,cortex-a9";
51 next-level-cache = <&L2>;
57 compatible = "arm,cortex-a9";
58 next-level-cache = <&L2>;
59 enable-method = "brcm,bcm-nsp-smp";
60 secondary-boot-reg = <0xffff0fec>;
66 compatible = "arm,cortex-a9-pmu";
67 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH
68 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
69 interrupt-affinity = <&cpu0>, <&cpu1>;
73 compatible = "simple-bus";
74 ranges = <0x00000000 0x19000000 0x00023000>;
78 a9pll: arm_clk@00000 {
80 compatible = "brcm,nsp-armpll";
82 reg = <0x00000 0x1000>;
86 compatible = "arm,cortex-a9-global-timer";
87 reg = <0x20200 0x100>;
88 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
89 clocks = <&periph_clk>;
93 compatible = "arm,cortex-a9-twd-timer";
95 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
96 IRQ_TYPE_LEVEL_HIGH)>;
97 clocks = <&periph_clk>;
101 compatible = "arm,cortex-a9-twd-wdt";
102 reg = <0x20620 0x20>;
103 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
104 IRQ_TYPE_LEVEL_HIGH)>;
105 clocks = <&periph_clk>;
108 gic: interrupt-controller@21000 {
109 compatible = "arm,cortex-a9-gic";
110 #interrupt-cells = <3>;
111 #address-cells = <0>;
112 interrupt-controller;
113 reg = <0x21000 0x1000>,
118 compatible = "arm,pl310-cache";
119 reg = <0x22000 0x1000>;
126 #address-cells = <1>;
132 compatible = "fixed-clock";
133 clock-frequency = <25000000>;
138 compatible = "fixed-factor-clock";
139 clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
144 iprocslow: iprocslow {
146 compatible = "fixed-factor-clock";
147 clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
152 periph_clk: periph_clk {
154 compatible = "fixed-factor-clock";
162 compatible = "simple-bus";
163 ranges = <0x00000000 0x18000000 0x0011ba08>;
164 #address-cells = <1>;
168 compatible = "brcm,nsp-gpio-a";
174 interrupt-controller;
175 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
176 gpio-ranges = <&pinctrl 0 0 32>;
180 compatible = "ns16550a";
181 reg = <0x0300 0x100>;
182 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
188 compatible = "ns16550a";
189 reg = <0x0400 0x100>;
190 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
196 compatible = "arm,pl330", "arm,primecell";
197 reg = <0x20000 0x1000>;
198 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
201 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
202 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
203 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
204 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
205 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
206 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
207 clocks = <&iprocslow>;
208 clock-names = "apb_pclk";
212 amac0: ethernet@22000 {
213 compatible = "brcm,nsp-amac";
214 reg = <0x022000 0x1000>,
216 reg-names = "amac_base", "idm_base";
217 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
221 amac1: ethernet@23000 {
222 compatible = "brcm,nsp-amac";
223 reg = <0x023000 0x1000>,
225 reg-names = "amac_base", "idm_base";
226 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
231 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
232 reg = <0x026000 0x600>,
235 reg-names = "nand", "iproc-idm", "iproc-ext";
236 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
238 #address-cells = <1>;
245 compatible = "brcm,bcm-nsp-rng";
246 reg = <0x33000 0x14>;
249 ccbtimer0: timer@34000 {
250 compatible = "arm,sp804";
251 reg = <0x34000 0x1000>;
252 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
253 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
254 clocks = <&iprocslow>;
255 clock-names = "apb_pclk";
258 ccbtimer1: timer@35000 {
259 compatible = "arm,sp804";
260 reg = <0x35000 0x1000>;
261 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
262 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
263 clocks = <&iprocslow>;
264 clock-names = "apb_pclk";
268 compatible = "brcm,nsp-srab";
269 reg = <0x36000 0x1000>;
270 #address-cells = <1>;
275 /* ports are defined in board DTS */
279 compatible = "brcm,iproc-i2c";
280 reg = <0x38000 0x50>;
281 #address-cells = <1>;
283 interrupts = <GIC_SPI 89 IRQ_TYPE_NONE>;
284 clock-frequency = <100000>;
288 compatible = "arm,sp805", "arm,primecell";
289 reg = <0x39000 0x1000>;
290 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
291 clocks = <&iprocslow>, <&iprocslow>;
292 clock-names = "wdogclk", "apb_pclk";
295 lcpll0: lcpll0@3f100 {
297 compatible = "brcm,nsp-lcpll0";
298 reg = <0x3f100 0x14>;
300 clock-output-names = "lcpll0", "pcie_phy", "sdio",
304 genpll: genpll@3f140 {
306 compatible = "brcm,nsp-genpll";
307 reg = <0x3f140 0x24>;
309 clock-output-names = "genpll", "phy", "ethernetclk",
310 "usbclk", "iprocfast", "sata1",
314 pinctrl: pinctrl@3f1c0 {
315 compatible = "brcm,nsp-pinmux";
316 reg = <0x3f1c0 0x04>,
321 sata_phy: sata_phy@40100 {
322 compatible = "brcm,iproc-nsp-sata-phy";
323 reg = <0x40100 0x340>;
325 #address-cells = <1>;
328 sata_phy0: sata-phy@0 {
334 sata_phy1: sata-phy@1 {
342 compatible = "brcm,bcm-nsp-ahci";
343 reg-names = "ahci", "top-ctrl";
344 reg = <0x41000 0x1000>, <0x40020 0x1c>;
345 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
346 #address-cells = <1>;
353 phy-names = "sata-phy";
359 phy-names = "sata-phy";
364 pcie0: pcie@18012000 {
365 compatible = "brcm,iproc-pcie";
366 reg = <0x18012000 0x1000>;
368 #interrupt-cells = <1>;
369 interrupt-map-mask = <0 0 0 0>;
370 interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_NONE>;
372 linux,pci-domain = <0>;
374 bus-range = <0x00 0xff>;
376 #address-cells = <3>;
380 /* Note: The HW does not support I/O resources. So,
381 * only the memory resource range is being specified.
383 ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>;
387 msi-parent = <&msi0>;
389 compatible = "brcm,iproc-msi";
391 interrupt-parent = <&gic>;
392 interrupts = <GIC_SPI 127 IRQ_TYPE_NONE>,
393 <GIC_SPI 128 IRQ_TYPE_NONE>,
394 <GIC_SPI 129 IRQ_TYPE_NONE>,
395 <GIC_SPI 130 IRQ_TYPE_NONE>;
400 pcie1: pcie@18013000 {
401 compatible = "brcm,iproc-pcie";
402 reg = <0x18013000 0x1000>;
404 #interrupt-cells = <1>;
405 interrupt-map-mask = <0 0 0 0>;
406 interrupt-map = <0 0 0 0 &gic GIC_SPI 137 IRQ_TYPE_NONE>;
408 linux,pci-domain = <1>;
410 bus-range = <0x00 0xff>;
412 #address-cells = <3>;
416 /* Note: The HW does not support I/O resources. So,
417 * only the memory resource range is being specified.
419 ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>;
423 msi-parent = <&msi1>;
425 compatible = "brcm,iproc-msi";
427 interrupt-parent = <&gic>;
428 interrupts = <GIC_SPI 133 IRQ_TYPE_NONE>,
429 <GIC_SPI 134 IRQ_TYPE_NONE>,
430 <GIC_SPI 135 IRQ_TYPE_NONE>,
431 <GIC_SPI 136 IRQ_TYPE_NONE>;
436 pcie2: pcie@18014000 {
437 compatible = "brcm,iproc-pcie";
438 reg = <0x18014000 0x1000>;
440 #interrupt-cells = <1>;
441 interrupt-map-mask = <0 0 0 0>;
442 interrupt-map = <0 0 0 0 &gic GIC_SPI 143 IRQ_TYPE_NONE>;
444 linux,pci-domain = <2>;
446 bus-range = <0x00 0xff>;
448 #address-cells = <3>;
452 /* Note: The HW does not support I/O resources. So,
453 * only the memory resource range is being specified.
455 ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>;
459 msi-parent = <&msi2>;
461 compatible = "brcm,iproc-msi";
463 interrupt-parent = <&gic>;
464 interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>,
465 <GIC_SPI 140 IRQ_TYPE_NONE>,
466 <GIC_SPI 141 IRQ_TYPE_NONE>,
467 <GIC_SPI 142 IRQ_TYPE_NONE>;