4 * Copyright(c) 2015 Broadcom Corporation. All rights reserved.
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7 * modification, are permitted provided that the following conditions
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14 * the documentation and/or other materials provided with the
16 * * Neither the name of Broadcom Corporation nor the names of its
17 * contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
35 #include <dt-bindings/clock/bcm-nsp.h>
37 #include "skeleton.dtsi"
40 compatible = "brcm,nsp";
41 model = "Broadcom Northstar Plus SoC";
42 interrupt-parent = <&gic>;
50 compatible = "arm,cortex-a9";
51 next-level-cache = <&L2>;
57 compatible = "arm,cortex-a9";
58 next-level-cache = <&L2>;
59 enable-method = "brcm,bcm-nsp-smp";
60 secondary-boot-reg = <0xffff0fec>;
66 compatible = "arm,cortex-a9-pmu";
67 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH
68 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
69 interrupt-affinity = <&cpu0>, <&cpu1>;
73 compatible = "simple-bus";
74 ranges = <0x00000000 0x19000000 0x00023000>;
80 compatible = "brcm,nsp-armpll";
82 reg = <0x00000 0x1000>;
86 compatible = "arm,cortex-a9-global-timer";
87 reg = <0x20200 0x100>;
88 interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
89 clocks = <&periph_clk>;
93 compatible = "arm,cortex-a9-twd-timer";
95 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
96 IRQ_TYPE_EDGE_RISING)>;
97 clocks = <&periph_clk>;
101 compatible = "arm,cortex-a9-twd-wdt";
102 reg = <0x20620 0x20>;
103 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
104 IRQ_TYPE_LEVEL_HIGH)>;
105 clocks = <&periph_clk>;
108 gic: interrupt-controller@21000 {
109 compatible = "arm,cortex-a9-gic";
110 #interrupt-cells = <3>;
111 #address-cells = <0>;
112 interrupt-controller;
113 reg = <0x21000 0x1000>,
118 compatible = "arm,pl310-cache";
119 reg = <0x22000 0x1000>;
126 #address-cells = <1>;
132 compatible = "fixed-clock";
133 clock-frequency = <25000000>;
138 compatible = "fixed-factor-clock";
139 clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
144 iprocslow: iprocslow {
146 compatible = "fixed-factor-clock";
147 clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
152 periph_clk: periph_clk {
154 compatible = "fixed-factor-clock";
162 compatible = "simple-bus";
163 ranges = <0x00000000 0x18000000 0x0011c40c>;
164 #address-cells = <1>;
168 compatible = "brcm,nsp-gpio-a";
174 interrupt-controller;
175 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
176 gpio-ranges = <&pinctrl 0 0 32>;
180 compatible = "ns16550a";
181 reg = <0x0300 0x100>;
182 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
188 compatible = "ns16550a";
189 reg = <0x0400 0x100>;
190 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
196 compatible = "arm,pl330", "arm,primecell";
197 reg = <0x20000 0x1000>;
198 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
201 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
202 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
203 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
204 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
205 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
206 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
207 clocks = <&iprocslow>;
208 clock-names = "apb_pclk";
213 compatible = "brcm,sdhci-iproc-cygnus";
214 reg = <0x21000 0x100>;
215 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
217 clocks = <&lcpll0 BCM_NSP_LCPLL0_SDIO_CLK>;
222 amac0: ethernet@22000 {
223 compatible = "brcm,nsp-amac";
224 reg = <0x022000 0x1000>,
226 reg-names = "amac_base", "idm_base";
227 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
232 amac1: ethernet@23000 {
233 compatible = "brcm,nsp-amac";
234 reg = <0x023000 0x1000>,
236 reg-names = "amac_base", "idm_base";
237 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
242 amac2: ethernet@24000 {
243 compatible = "brcm,nsp-amac";
244 reg = <0x024000 0x1000>,
246 reg-names = "amac_base", "idm_base";
247 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
252 mailbox: mailbox@25000 {
253 compatible = "brcm,iproc-fa2-mbox";
254 reg = <0x25000 0x445>;
255 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
257 brcm,rx-status-len = <32>;
263 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
264 reg = <0x026000 0x600>,
267 reg-names = "nand", "iproc-idm", "iproc-ext";
268 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
270 #address-cells = <1>;
277 compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi";
278 reg = <0x027200 0x184>,
282 reg-names = "mspi", "bspi", "intr_regs",
284 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
287 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
288 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
289 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
290 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
291 interrupt-names = "spi_lr_fullness_reached",
292 "spi_lr_session_aborted",
294 "spi_lr_session_done",
298 clocks = <&iprocmed>;
299 clock-names = "iprocmed";
301 #address-cells = <1>;
306 compatible = "generic-xhci";
307 reg = <0x29000 0x1000>;
308 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
310 phy-names = "usb3-phy";
316 compatible = "generic-ehci";
317 reg = <0x2a000 0x100>;
318 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
324 compatible = "generic-ohci";
325 reg = <0x2b000 0x100>;
326 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
332 compatible = "brcm,spum-nsp-crypto";
333 reg = <0x2f000 0x900>;
334 mboxes = <&mailbox 0>;
338 compatible = "brcm,iproc-nsp-gpio", "brcm,iproc-gpio";
339 reg = <0x30000 0x50>;
343 interrupt-controller;
344 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
348 compatible = "brcm,iproc-pwm";
349 reg = <0x31000 0x28>;
356 compatible = "brcm,bcm-nsp-rng";
357 reg = <0x33000 0x14>;
360 ccbtimer0: timer@34000 {
361 compatible = "arm,sp804";
362 reg = <0x34000 0x1000>;
363 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
364 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
365 clocks = <&iprocslow>;
366 clock-names = "apb_pclk";
369 ccbtimer1: timer@35000 {
370 compatible = "arm,sp804";
371 reg = <0x35000 0x1000>;
372 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
373 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
374 clocks = <&iprocslow>;
375 clock-names = "apb_pclk";
379 compatible = "brcm,nsp-srab";
380 reg = <0x36000 0x1000>,
383 reg-names = "srab", "mux_config", "sgmii";
384 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
385 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
386 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
387 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
388 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
389 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
390 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
391 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
392 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
393 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
394 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
395 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
396 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
397 interrupt-names = "link_state_p0",
407 "imp_sleep_timer_p5",
408 "imp_sleep_timer_p7",
409 "imp_sleep_timer_p8";
410 #address-cells = <1>;
415 /* ports are defined in board DTS */
419 compatible = "brcm,iproc-i2c";
420 reg = <0x38000 0x50>;
421 #address-cells = <1>;
423 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
424 clock-frequency = <100000>;
430 compatible = "arm,sp805", "arm,primecell";
431 reg = <0x39000 0x1000>;
432 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
433 clocks = <&iprocslow>, <&iprocslow>;
434 clock-names = "wdogclk", "apb_pclk";
437 lcpll0: lcpll0@3f100 {
439 compatible = "brcm,nsp-lcpll0";
440 reg = <0x3f100 0x14>;
442 clock-output-names = "lcpll0", "pcie_phy", "sdio",
446 genpll: genpll@3f140 {
448 compatible = "brcm,nsp-genpll";
449 reg = <0x3f140 0x24>;
451 clock-output-names = "genpll", "phy", "ethernetclk",
452 "usbclk", "iprocfast", "sata1",
456 pinctrl: pinctrl@3f1c0 {
457 compatible = "brcm,nsp-pinmux";
458 reg = <0x3f1c0 0x04>,
463 thermal: thermal@3f2c0 {
464 compatible = "brcm,ns-thermal";
465 reg = <0x3f2c0 0x10>;
466 #thermal-sensor-cells = <0>;
469 sata_phy: sata_phy@40100 {
470 compatible = "brcm,iproc-nsp-sata-phy";
471 reg = <0x40100 0x340>;
473 #address-cells = <1>;
476 sata_phy0: sata-phy@0 {
482 sata_phy1: sata-phy@1 {
490 compatible = "brcm,bcm-nsp-ahci";
491 reg-names = "ahci", "top-ctrl";
492 reg = <0x41000 0x1000>, <0x40020 0x1c>;
493 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
494 #address-cells = <1>;
502 phy-names = "sata-phy";
508 phy-names = "sata-phy";
512 usb3_phy: usb3-phy@104000 {
513 compatible = "brcm,ns-bx-usb3-phy";
514 reg = <0x104000 0x1000>,
516 reg-names = "dmp", "ccb-mii";
522 pcie0: pcie@18012000 {
523 compatible = "brcm,iproc-pcie";
524 reg = <0x18012000 0x1000>;
526 #interrupt-cells = <1>;
527 interrupt-map-mask = <0 0 0 0>;
528 interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
530 linux,pci-domain = <0>;
532 bus-range = <0x00 0xff>;
534 #address-cells = <3>;
538 /* Note: The HW does not support I/O resources. So,
539 * only the memory resource range is being specified.
541 ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>;
546 msi-parent = <&msi0>;
547 msi0: msi-controller {
548 compatible = "brcm,iproc-msi";
550 interrupt-parent = <&gic>;
551 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
552 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
553 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
554 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
559 pcie1: pcie@18013000 {
560 compatible = "brcm,iproc-pcie";
561 reg = <0x18013000 0x1000>;
563 #interrupt-cells = <1>;
564 interrupt-map-mask = <0 0 0 0>;
565 interrupt-map = <0 0 0 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
567 linux,pci-domain = <1>;
569 bus-range = <0x00 0xff>;
571 #address-cells = <3>;
575 /* Note: The HW does not support I/O resources. So,
576 * only the memory resource range is being specified.
578 ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>;
583 msi-parent = <&msi1>;
584 msi1: msi-controller {
585 compatible = "brcm,iproc-msi";
587 interrupt-parent = <&gic>;
588 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
589 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
590 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
591 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
596 pcie2: pcie@18014000 {
597 compatible = "brcm,iproc-pcie";
598 reg = <0x18014000 0x1000>;
600 #interrupt-cells = <1>;
601 interrupt-map-mask = <0 0 0 0>;
602 interrupt-map = <0 0 0 0 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
604 linux,pci-domain = <2>;
606 bus-range = <0x00 0xff>;
608 #address-cells = <3>;
612 /* Note: The HW does not support I/O resources. So,
613 * only the memory resource range is being specified.
615 ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>;
620 msi-parent = <&msi2>;
621 msi2: msi-controller {
622 compatible = "brcm,iproc-msi";
624 interrupt-parent = <&gic>;
625 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
626 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
627 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
628 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
635 polling-delay-passive = <0>;
636 polling-delay = <1000>;
637 coefficients = <(-556) 418000>;
638 thermal-sensors = <&thermal>;
642 temperature = <125000>;