arch/arm/boot/dts/aspeed-g5.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 #include <dt-bindings/clock/aspeed-clock.h>
   3
   4 / {
   5         model = "Aspeed BMC";
   6         compatible = "aspeed,ast2500";
   7         #address-cells = <1>;
   8         #size-cells = <1>;
   9         interrupt-parent = <&vic>;
  10
  11         aliases {
  12                 i2c0 = &i2c0;
  13                 i2c1 = &i2c1;
  14                 i2c2 = &i2c2;
  15                 i2c3 = &i2c3;
  16                 i2c4 = &i2c4;
  17                 i2c5 = &i2c5;
  18                 i2c6 = &i2c6;
  19                 i2c7 = &i2c7;
  20                 i2c8 = &i2c8;
  21                 i2c9 = &i2c9;
  22                 i2c10 = &i2c10;
  23                 i2c11 = &i2c11;
  24                 i2c12 = &i2c12;
  25                 i2c13 = &i2c13;
  26                 serial0 = &uart1;
  27                 serial1 = &uart2;
  28                 serial2 = &uart3;
  29                 serial3 = &uart4;
  30                 serial4 = &uart5;
  31                 serial5 = &vuart;
  32         };
  33
  34         cpus {
  35                 #address-cells = <1>;
  36                 #size-cells = <0>;
  37
  38                 cpu@0 {
  39                         compatible = "arm,arm1176jzf-s";
  40                         device_type = "cpu";
  41                         reg = <0>;
  42                 };
  43         };
  44
  45         memory@80000000 {
  46                 device_type = "memory";
  47                 reg = <0x80000000 0>;
  48         };
  49
  50         ahb {
  51                 compatible = "simple-bus";
  52                 #address-cells = <1>;
  53                 #size-cells = <1>;
  54                 ranges;
  55
  56                 fmc: flash-controller@1e620000 {
  57                         reg = < 0x1e620000 0xc4
  58                                 0x20000000 0x10000000 >;
  59                         #address-cells = <1>;
  60                         #size-cells = <0>;
  61                         compatible = "aspeed,ast2500-fmc";
  62                         clocks = <&syscon ASPEED_CLK_AHB>;
  63                         status = "disabled";
  64                         interrupts = <19>;
  65                         flash@0 {
  66                                 reg = < 0 >;
  67                                 compatible = "jedec,spi-nor";
  68                                 status = "disabled";
  69                         };
  70                         flash@1 {
  71                                 reg = < 1 >;
  72                                 compatible = "jedec,spi-nor";
  73                                 status = "disabled";
  74                         };
  75                         flash@2 {
  76                                 reg = < 2 >;
  77                                 compatible = "jedec,spi-nor";
  78                                 status = "disabled";
  79                         };
  80                 };
  81
  82                 spi1: flash-controller@1e630000 {
  83                         reg = < 0x1e630000 0xc4
  84                                 0x30000000 0x08000000 >;
  85                         #address-cells = <1>;
  86                         #size-cells = <0>;
  87                         compatible = "aspeed,ast2500-spi";
  88                         clocks = <&syscon ASPEED_CLK_AHB>;
  89                         status = "disabled";
  90                         flash@0 {
  91                                 reg = < 0 >;
  92                                 compatible = "jedec,spi-nor";
  93                                 status = "disabled";
  94                         };
  95                         flash@1 {
  96                                 reg = < 1 >;
  97                                 compatible = "jedec,spi-nor";
  98                                 status = "disabled";
  99                         };
 100                 };
 101
 102                 spi2: flash-controller@1e631000 {
 103                         reg = < 0x1e631000 0xc4
 104                                 0x38000000 0x08000000 >;
 105                         #address-cells = <1>;
 106                         #size-cells = <0>;
 107                         compatible = "aspeed,ast2500-spi";
 108                         clocks = <&syscon ASPEED_CLK_AHB>;
 109                         status = "disabled";
 110                         flash@0 {
 111                                 reg = < 0 >;
 112                                 compatible = "jedec,spi-nor";
 113                                 status = "disabled";
 114                         };
 115                         flash@1 {
 116                                 reg = < 1 >;
 117                                 compatible = "jedec,spi-nor";
 118                                 status = "disabled";
 119                         };
 120                 };
 121
 122                 vic: interrupt-controller@1e6c0080 {
 123                         compatible = "aspeed,ast2400-vic";
 124                         interrupt-controller;
 125                         #interrupt-cells = <1>;
 126                         valid-sources = <0xfefff7ff 0x0807ffff>;
 127                         reg = <0x1e6c0080 0x80>;
 128                 };
 129
 130                 mac0: ethernet@1e660000 {
 131                         compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
 132                         reg = <0x1e660000 0x180>;
 133                         interrupts = <2>;
 134                         clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
 135                         status = "disabled";
 136                 };
 137
 138                 mac1: ethernet@1e680000 {
 139                         compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
 140                         reg = <0x1e680000 0x180>;
 141                         interrupts = <3>;
 142                         clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
 143                         status = "disabled";
 144                 };
 145
 146                 apb {
 147                         compatible = "simple-bus";
 148                         #address-cells = <1>;
 149                         #size-cells = <1>;
 150                         ranges;
 151
 152                         syscon: syscon@1e6e2000 {
 153                                 compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd";
 154                                 reg = <0x1e6e2000 0x1a8>;
 155                                 #address-cells = <1>;
 156                                 #size-cells = <0>;
 157                                 #clock-cells = <1>;
 158                                 #reset-cells = <1>;
 159
 160                                 pinctrl: pinctrl {
 161                                         compatible = "aspeed,g5-pinctrl";
 162                                         aspeed,external-nodes = <&gfx &lhc>;
 163
 164                                 };
 165                         };
 166
 167                         gfx: display@1e6e6000 {
 168                                 compatible = "aspeed,ast2500-gfx", "syscon";
 169                                 reg = <0x1e6e6000 0x1000>;
 170                                 reg-io-width = <4>;
 171                         };
 172
 173                         adc: adc@1e6e9000 {
 174                                 compatible = "aspeed,ast2500-adc";
 175                                 reg = <0x1e6e9000 0xb0>;
 176                                 clocks = <&syscon ASPEED_CLK_APB>;
 177                                 resets = <&syscon ASPEED_RESET_ADC>;
 178                                 #io-channel-cells = <1>;
 179                                 status = "disabled";
 180                         };
 181
 182                         sram@1e720000 {
 183                                 compatible = "mmio-sram";
 184                                 reg = <0x1e720000 0x9000>;      // 36K
 185                         };
 186
 187                         gpio: gpio@1e780000 {
 188                                 #gpio-cells = <2>;
 189                                 gpio-controller;
 190                                 compatible = "aspeed,ast2500-gpio";
 191                                 reg = <0x1e780000 0x1000>;
 192                                 interrupts = <20>;
 193                                 gpio-ranges = <&pinctrl 0 0 220>;
 194                                 clocks = <&syscon ASPEED_CLK_APB>;
 195                                 interrupt-controller;
 196                         };
 197
 198                         timer: timer@1e782000 {
 199                                 /* This timer is a Faraday FTTMR010 derivative */
 200                                 compatible = "aspeed,ast2400-timer";
 201                                 reg = <0x1e782000 0x90>;
 202                                 interrupts = <16 17 18 35 36 37 38 39>;
 203                                 clocks = <&syscon ASPEED_CLK_APB>;
 204                                 clock-names = "PCLK";
 205                         };
 206
 207                         uart1: serial@1e783000 {
 208                                 compatible = "ns16550a";
 209                                 reg = <0x1e783000 0x20>;
 210                                 reg-shift = <2>;
 211                                 interrupts = <9>;
 212                                 clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
 213                                 no-loopback-test;
 214                                 status = "disabled";
 215                         };
 216
 217                         uart5: serial@1e784000 {
 218                                 compatible = "ns16550a";
 219                                 reg = <0x1e784000 0x20>;
 220                                 reg-shift = <2>;
 221                                 interrupts = <10>;
 222                                 clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
 223                                 no-loopback-test;
 224                                 status = "disabled";
 225                         };
 226
 227                         wdt1: watchdog@1e785000 {
 228                                 compatible = "aspeed,ast2500-wdt";
 229                                 reg = <0x1e785000 0x20>;
 230                                 clocks = <&syscon ASPEED_CLK_APB>;
 231                         };
 232
 233                         wdt2: watchdog@1e785020 {
 234                                 compatible = "aspeed,ast2500-wdt";
 235                                 reg = <0x1e785020 0x20>;
 236                                 clocks = <&syscon ASPEED_CLK_APB>;
 237                         };
 238
 239                         wdt3: watchdog@1e785040 {
 240                                 compatible = "aspeed,ast2500-wdt";
 241                                 reg = <0x1e785040 0x20>;
 242                                 clocks = <&syscon ASPEED_CLK_APB>;
 243                                 status = "disabled";
 244                         };
 245
 246                         pwm_tacho: pwm-tacho-controller@1e786000 {
 247                                 compatible = "aspeed,ast2500-pwm-tacho";
 248                                 #address-cells = <1>;
 249                                 #size-cells = <0>;
 250                                 reg = <0x1e786000 0x1000>;
 251                                 clocks = <&syscon ASPEED_CLK_APB>;
 252                                 resets = <&syscon ASPEED_RESET_PWM>;
 253                                 status = "disabled";
 254                         };
 255
 256                         vuart: serial@1e787000 {
 257                                 compatible = "aspeed,ast2500-vuart";
 258                                 reg = <0x1e787000 0x40>;
 259                                 reg-shift = <2>;
 260                                 interrupts = <8>;
 261                                 clocks = <&syscon ASPEED_CLK_APB>;
 262                                 no-loopback-test;
 263                                 status = "disabled";
 264                         };
 265
 266                         lpc: lpc@1e789000 {
 267                                 compatible = "aspeed,ast2500-lpc", "simple-mfd";
 268                                 reg = <0x1e789000 0x1000>;
 269
 270                                 #address-cells = <1>;
 271                                 #size-cells = <1>;
 272                                 ranges = <0 0x1e789000 0x1000>;
 273
 274                                 lpc_bmc: lpc-bmc@0 {
 275                                         compatible = "aspeed,ast2500-lpc-bmc";
 276                                         reg = <0x0 0x80>;
 277                                 };
 278
 279                                 lpc_host: lpc-host@80 {
 280                                         compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon";
 281                                         reg = <0x80 0x1e0>;
 282
 283                                         #address-cells = <1>;
 284                                         #size-cells = <1>;
 285                                         ranges = <0 0x80 0x1e0>;
 286
 287                                         reg-io-width = <4>;
 288
 289                                         lpc_ctrl: lpc-ctrl@0 {
 290                                                 compatible = "aspeed,ast2500-lpc-ctrl";
 291                                                 reg = <0x0 0x80>;
 292                                                 status = "disabled";
 293                                         };
 294
 295                                         lpc_snoop: lpc-snoop@0 {
 296                                                 compatible = "aspeed,ast2500-lpc-snoop";
 297                                                 reg = <0x0 0x80>;
 298                                                 interrupts = <8>;
 299                                                 status = "disabled";
 300                                         };
 301
 302                                         lhc: lhc@20 {
 303                                                 compatible = "aspeed,ast2500-lhc";
 304                                                 reg = <0x20 0x24 0x48 0x8>;
 305                                         };
 306                                 };
 307                         };
 308
 309                         uart2: serial@1e78d000 {
 310                                 compatible = "ns16550a";
 311                                 reg = <0x1e78d000 0x20>;
 312                                 reg-shift = <2>;
 313                                 interrupts = <32>;
 314                                 clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
 315                                 no-loopback-test;
 316                                 status = "disabled";
 317                         };
 318
 319                         uart3: serial@1e78e000 {
 320                                 compatible = "ns16550a";
 321                                 reg = <0x1e78e000 0x20>;
 322                                 reg-shift = <2>;
 323                                 interrupts = <33>;
 324                                 clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
 325                                 no-loopback-test;
 326                                 status = "disabled";
 327                         };
 328
 329                         uart4: serial@1e78f000 {
 330                                 compatible = "ns16550a";
 331                                 reg = <0x1e78f000 0x20>;
 332                                 reg-shift = <2>;
 333                                 interrupts = <34>;
 334                                 clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
 335                                 no-loopback-test;
 336                                 status = "disabled";
 337                         };
 338
 339                         i2c: i2c@1e78a000 {
 340                                 compatible = "simple-bus";
 341                                 #address-cells = <1>;
 342                                 #size-cells = <1>;
 343                                 ranges = <0 0x1e78a000 0x1000>;
 344                         };
 345                 };
 346         };
 347 };
 348
 349 &i2c {
 350         i2c_ic: interrupt-controller@0 {
 351                 #interrupt-cells = <1>;
 352                 compatible = "aspeed,ast2500-i2c-ic";
 353                 reg = <0x0 0x40>;
 354                 interrupts = <12>;
 355                 interrupt-controller;
 356         };
 357
 358         i2c0: i2c-bus@40 {
 359                 #address-cells = <1>;
 360                 #size-cells = <0>;
 361                 #interrupt-cells = <1>;
 362
 363                 reg = <0x40 0x40>;
 364                 compatible = "aspeed,ast2500-i2c-bus";
 365                 clocks = <&syscon ASPEED_CLK_APB>;
 366                 resets = <&syscon ASPEED_RESET_I2C>;
 367                 bus-frequency = <100000>;
 368                 interrupts = <0>;
 369                 interrupt-parent = <&i2c_ic>;
 370                 status = "disabled";
 371                 /* Does not need pinctrl properties */
 372         };
 373
 374         i2c1: i2c-bus@80 {
 375                 #address-cells = <1>;
 376                 #size-cells = <0>;
 377                 #interrupt-cells = <1>;
 378
 379                 reg = <0x80 0x40>;
 380                 compatible = "aspeed,ast2500-i2c-bus";
 381                 clocks = <&syscon ASPEED_CLK_APB>;
 382                 resets = <&syscon ASPEED_RESET_I2C>;
 383                 bus-frequency = <100000>;
 384                 interrupts = <1>;
 385                 interrupt-parent = <&i2c_ic>;
 386                 status = "disabled";
 387                 /* Does not need pinctrl properties */
 388         };
 389
 390         i2c2: i2c-bus@c0 {
 391                 #address-cells = <1>;
 392                 #size-cells = <0>;
 393                 #interrupt-cells = <1>;
 394
 395                 reg = <0xc0 0x40>;
 396                 compatible = "aspeed,ast2500-i2c-bus";
 397                 clocks = <&syscon ASPEED_CLK_APB>;
 398                 resets = <&syscon ASPEED_RESET_I2C>;
 399                 bus-frequency = <100000>;
 400                 interrupts = <2>;
 401                 interrupt-parent = <&i2c_ic>;
 402                 pinctrl-names = "default";
 403                 pinctrl-0 = <&pinctrl_i2c3_default>;
 404                 status = "disabled";
 405         };
 406
 407         i2c3: i2c-bus@100 {
 408                 #address-cells = <1>;
 409                 #size-cells = <0>;
 410                 #interrupt-cells = <1>;
 411
 412                 reg = <0x100 0x40>;
 413                 compatible = "aspeed,ast2500-i2c-bus";
 414                 clocks = <&syscon ASPEED_CLK_APB>;
 415                 resets = <&syscon ASPEED_RESET_I2C>;
 416                 bus-frequency = <100000>;
 417                 interrupts = <3>;
 418                 interrupt-parent = <&i2c_ic>;
 419                 pinctrl-names = "default";
 420                 pinctrl-0 = <&pinctrl_i2c4_default>;
 421                 status = "disabled";
 422         };
 423
 424         i2c4: i2c-bus@140 {
 425                 #address-cells = <1>;
 426                 #size-cells = <0>;
 427                 #interrupt-cells = <1>;
 428
 429                 reg = <0x140 0x40>;
 430                 compatible = "aspeed,ast2500-i2c-bus";
 431                 clocks = <&syscon ASPEED_CLK_APB>;
 432                 resets = <&syscon ASPEED_RESET_I2C>;
 433                 bus-frequency = <100000>;
 434                 interrupts = <4>;
 435                 interrupt-parent = <&i2c_ic>;
 436                 pinctrl-names = "default";
 437                 pinctrl-0 = <&pinctrl_i2c5_default>;
 438                 status = "disabled";
 439         };
 440
 441         i2c5: i2c-bus@180 {
 442                 #address-cells = <1>;
 443                 #size-cells = <0>;
 444                 #interrupt-cells = <1>;
 445
 446                 reg = <0x180 0x40>;
 447                 compatible = "aspeed,ast2500-i2c-bus";
 448                 clocks = <&syscon ASPEED_CLK_APB>;
 449                 resets = <&syscon ASPEED_RESET_I2C>;
 450                 bus-frequency = <100000>;
 451                 interrupts = <5>;
 452                 interrupt-parent = <&i2c_ic>;
 453                 pinctrl-names = "default";
 454                 pinctrl-0 = <&pinctrl_i2c6_default>;
 455                 status = "disabled";
 456         };
 457
 458         i2c6: i2c-bus@1c0 {
 459                 #address-cells = <1>;
 460                 #size-cells = <0>;
 461                 #interrupt-cells = <1>;
 462
 463                 reg = <0x1c0 0x40>;
 464                 compatible = "aspeed,ast2500-i2c-bus";
 465                 clocks = <&syscon ASPEED_CLK_APB>;
 466                 resets = <&syscon ASPEED_RESET_I2C>;
 467                 bus-frequency = <100000>;
 468                 interrupts = <6>;
 469                 interrupt-parent = <&i2c_ic>;
 470                 pinctrl-names = "default";
 471                 pinctrl-0 = <&pinctrl_i2c7_default>;
 472                 status = "disabled";
 473         };
 474
 475         i2c7: i2c-bus@300 {
 476                 #address-cells = <1>;
 477                 #size-cells = <0>;
 478                 #interrupt-cells = <1>;
 479
 480                 reg = <0x300 0x40>;
 481                 compatible = "aspeed,ast2500-i2c-bus";
 482                 clocks = <&syscon ASPEED_CLK_APB>;
 483                 resets = <&syscon ASPEED_RESET_I2C>;
 484                 bus-frequency = <100000>;
 485                 interrupts = <7>;
 486                 interrupt-parent = <&i2c_ic>;
 487                 pinctrl-names = "default";
 488                 pinctrl-0 = <&pinctrl_i2c8_default>;
 489                 status = "disabled";
 490         };
 491
 492         i2c8: i2c-bus@340 {
 493                 #address-cells = <1>;
 494                 #size-cells = <0>;
 495                 #interrupt-cells = <1>;
 496
 497                 reg = <0x340 0x40>;
 498                 compatible = "aspeed,ast2500-i2c-bus";
 499                 clocks = <&syscon ASPEED_CLK_APB>;
 500                 resets = <&syscon ASPEED_RESET_I2C>;
 501                 bus-frequency = <100000>;
 502                 interrupts = <8>;
 503                 interrupt-parent = <&i2c_ic>;
 504                 pinctrl-names = "default";
 505                 pinctrl-0 = <&pinctrl_i2c9_default>;
 506                 status = "disabled";
 507         };
 508
 509         i2c9: i2c-bus@380 {
 510                 #address-cells = <1>;
 511                 #size-cells = <0>;
 512                 #interrupt-cells = <1>;
 513
 514                 reg = <0x380 0x40>;
 515                 compatible = "aspeed,ast2500-i2c-bus";
 516                 clocks = <&syscon ASPEED_CLK_APB>;
 517                 resets = <&syscon ASPEED_RESET_I2C>;
 518                 bus-frequency = <100000>;
 519                 interrupts = <9>;
 520                 interrupt-parent = <&i2c_ic>;
 521                 pinctrl-names = "default";
 522                 pinctrl-0 = <&pinctrl_i2c10_default>;
 523                 status = "disabled";
 524         };
 525
 526         i2c10: i2c-bus@3c0 {
 527                 #address-cells = <1>;
 528                 #size-cells = <0>;
 529                 #interrupt-cells = <1>;
 530
 531                 reg = <0x3c0 0x40>;
 532                 compatible = "aspeed,ast2500-i2c-bus";
 533                 clocks = <&syscon ASPEED_CLK_APB>;
 534                 resets = <&syscon ASPEED_RESET_I2C>;
 535                 bus-frequency = <100000>;
 536                 interrupts = <10>;
 537                 interrupt-parent = <&i2c_ic>;
 538                 pinctrl-names = "default";
 539                 pinctrl-0 = <&pinctrl_i2c11_default>;
 540                 status = "disabled";
 541         };
 542
 543         i2c11: i2c-bus@400 {
 544                 #address-cells = <1>;
 545                 #size-cells = <0>;
 546                 #interrupt-cells = <1>;
 547
 548                 reg = <0x400 0x40>;
 549                 compatible = "aspeed,ast2500-i2c-bus";
 550                 clocks = <&syscon ASPEED_CLK_APB>;
 551                 resets = <&syscon ASPEED_RESET_I2C>;
 552                 bus-frequency = <100000>;
 553                 interrupts = <11>;
 554                 interrupt-parent = <&i2c_ic>;
 555                 pinctrl-names = "default";
 556                 pinctrl-0 = <&pinctrl_i2c12_default>;
 557                 status = "disabled";
 558         };
 559
 560         i2c12: i2c-bus@440 {
 561                 #address-cells = <1>;
 562                 #size-cells = <0>;
 563                 #interrupt-cells = <1>;
 564
 565                 reg = <0x440 0x40>;
 566                 compatible = "aspeed,ast2500-i2c-bus";
 567                 clocks = <&syscon ASPEED_CLK_APB>;
 568                 resets = <&syscon ASPEED_RESET_I2C>;
 569                 bus-frequency = <100000>;
 570                 interrupts = <12>;
 571                 interrupt-parent = <&i2c_ic>;
 572                 pinctrl-names = "default";
 573                 pinctrl-0 = <&pinctrl_i2c13_default>;
 574                 status = "disabled";
 575         };
 576
 577         i2c13: i2c-bus@480 {
 578                 #address-cells = <1>;
 579                 #size-cells = <0>;
 580                 #interrupt-cells = <1>;
 581
 582                 reg = <0x480 0x40>;
 583                 compatible = "aspeed,ast2500-i2c-bus";
 584                 clocks = <&syscon ASPEED_CLK_APB>;
 585                 resets = <&syscon ASPEED_RESET_I2C>;
 586                 bus-frequency = <100000>;
 587                 interrupts = <13>;
 588                 interrupt-parent = <&i2c_ic>;
 589                 pinctrl-names = "default";
 590                 pinctrl-0 = <&pinctrl_i2c14_default>;
 591                 status = "disabled";
 592         };
 593 };
 594
 595 &pinctrl {
 596         pinctrl_acpi_default: acpi_default {
 597                 function = "ACPI";
 598                 groups = "ACPI";
 599         };
 600
 601         pinctrl_adc0_default: adc0_default {
 602                 function = "ADC0";
 603                 groups = "ADC0";
 604         };
 605
 606         pinctrl_adc1_default: adc1_default {
 607                 function = "ADC1";
 608                 groups = "ADC1";
 609         };
 610
 611         pinctrl_adc10_default: adc10_default {
 612                 function = "ADC10";
 613                 groups = "ADC10";
 614         };
 615
 616         pinctrl_adc11_default: adc11_default {
 617                 function = "ADC11";
 618                 groups = "ADC11";
 619         };
 620
 621         pinctrl_adc12_default: adc12_default {
 622                 function = "ADC12";
 623                 groups = "ADC12";
 624         };
 625
 626         pinctrl_adc13_default: adc13_default {
 627                 function = "ADC13";
 628                 groups = "ADC13";
 629         };
 630
 631         pinctrl_adc14_default: adc14_default {
 632                 function = "ADC14";
 633                 groups = "ADC14";
 634         };
 635
 636         pinctrl_adc15_default: adc15_default {
 637                 function = "ADC15";
 638                 groups = "ADC15";
 639         };
 640
 641         pinctrl_adc2_default: adc2_default {
 642                 function = "ADC2";
 643                 groups = "ADC2";
 644         };
 645
 646         pinctrl_adc3_default: adc3_default {
 647                 function = "ADC3";
 648                 groups = "ADC3";
 649         };
 650
 651         pinctrl_adc4_default: adc4_default {
 652                 function = "ADC4";
 653                 groups = "ADC4";
 654         };
 655
 656         pinctrl_adc5_default: adc5_default {
 657                 function = "ADC5";
 658                 groups = "ADC5";
 659         };
 660
 661         pinctrl_adc6_default: adc6_default {
 662                 function = "ADC6";
 663                 groups = "ADC6";
 664         };
 665
 666         pinctrl_adc7_default: adc7_default {
 667                 function = "ADC7";
 668                 groups = "ADC7";
 669         };
 670
 671         pinctrl_adc8_default: adc8_default {
 672                 function = "ADC8";
 673                 groups = "ADC8";
 674         };
 675
 676         pinctrl_adc9_default: adc9_default {
 677                 function = "ADC9";
 678                 groups = "ADC9";
 679         };
 680
 681         pinctrl_bmcint_default: bmcint_default {
 682                 function = "BMCINT";
 683                 groups = "BMCINT";
 684         };
 685
 686         pinctrl_ddcclk_default: ddcclk_default {
 687                 function = "DDCCLK";
 688                 groups = "DDCCLK";
 689         };
 690
 691         pinctrl_ddcdat_default: ddcdat_default {
 692                 function = "DDCDAT";
 693                 groups = "DDCDAT";
 694         };
 695
 696         pinctrl_espi_default: espi_default {
 697                 function = "ESPI";
 698                 groups = "ESPI";
 699         };
 700
 701         pinctrl_fwspics1_default: fwspics1_default {
 702                 function = "FWSPICS1";
 703                 groups = "FWSPICS1";
 704         };
 705
 706         pinctrl_fwspics2_default: fwspics2_default {
 707                 function = "FWSPICS2";
 708                 groups = "FWSPICS2";
 709         };
 710
 711         pinctrl_gpid0_default: gpid0_default {
 712                 function = "GPID0";
 713                 groups = "GPID0";
 714         };
 715
 716         pinctrl_gpid2_default: gpid2_default {
 717                 function = "GPID2";
 718                 groups = "GPID2";
 719         };
 720
 721         pinctrl_gpid4_default: gpid4_default {
 722                 function = "GPID4";
 723                 groups = "GPID4";
 724         };
 725
 726         pinctrl_gpid6_default: gpid6_default {
 727                 function = "GPID6";
 728                 groups = "GPID6";
 729         };
 730
 731         pinctrl_gpie0_default: gpie0_default {
 732                 function = "GPIE0";
 733                 groups = "GPIE0";
 734         };
 735
 736         pinctrl_gpie2_default: gpie2_default {
 737                 function = "GPIE2";
 738                 groups = "GPIE2";
 739         };
 740
 741         pinctrl_gpie4_default: gpie4_default {
 742                 function = "GPIE4";
 743                 groups = "GPIE4";
 744         };
 745
 746         pinctrl_gpie6_default: gpie6_default {
 747                 function = "GPIE6";
 748                 groups = "GPIE6";
 749         };
 750
 751         pinctrl_i2c10_default: i2c10_default {
 752                 function = "I2C10";
 753                 groups = "I2C10";
 754         };
 755
 756         pinctrl_i2c11_default: i2c11_default {
 757                 function = "I2C11";
 758                 groups = "I2C11";
 759         };
 760
 761         pinctrl_i2c12_default: i2c12_default {
 762                 function = "I2C12";
 763                 groups = "I2C12";
 764         };
 765
 766         pinctrl_i2c13_default: i2c13_default {
 767                 function = "I2C13";
 768                 groups = "I2C13";
 769         };
 770
 771         pinctrl_i2c14_default: i2c14_default {
 772                 function = "I2C14";
 773                 groups = "I2C14";
 774         };
 775
 776         pinctrl_i2c3_default: i2c3_default {
 777                 function = "I2C3";
 778                 groups = "I2C3";
 779         };
 780
 781         pinctrl_i2c4_default: i2c4_default {
 782                 function = "I2C4";
 783                 groups = "I2C4";
 784         };
 785
 786         pinctrl_i2c5_default: i2c5_default {
 787                 function = "I2C5";
 788                 groups = "I2C5";
 789         };
 790
 791         pinctrl_i2c6_default: i2c6_default {
 792                 function = "I2C6";
 793                 groups = "I2C6";
 794         };
 795
 796         pinctrl_i2c7_default: i2c7_default {
 797                 function = "I2C7";
 798                 groups = "I2C7";
 799         };
 800
 801         pinctrl_i2c8_default: i2c8_default {
 802                 function = "I2C8";
 803                 groups = "I2C8";
 804         };
 805
 806         pinctrl_i2c9_default: i2c9_default {
 807                 function = "I2C9";
 808                 groups = "I2C9";
 809         };
 810
 811         pinctrl_lad0_default: lad0_default {
 812                 function = "LAD0";
 813                 groups = "LAD0";
 814         };
 815
 816         pinctrl_lad1_default: lad1_default {
 817                 function = "LAD1";
 818                 groups = "LAD1";
 819         };
 820
 821         pinctrl_lad2_default: lad2_default {
 822                 function = "LAD2";
 823                 groups = "LAD2";
 824         };
 825
 826         pinctrl_lad3_default: lad3_default {
 827                 function = "LAD3";
 828                 groups = "LAD3";
 829         };
 830
 831         pinctrl_lclk_default: lclk_default {
 832                 function = "LCLK";
 833                 groups = "LCLK";
 834         };
 835
 836         pinctrl_lframe_default: lframe_default {
 837                 function = "LFRAME";
 838                 groups = "LFRAME";
 839         };
 840
 841         pinctrl_lpchc_default: lpchc_default {
 842                 function = "LPCHC";
 843                 groups = "LPCHC";
 844         };
 845
 846         pinctrl_lpcpd_default: lpcpd_default {
 847                 function = "LPCPD";
 848                 groups = "LPCPD";
 849         };
 850
 851         pinctrl_lpcplus_default: lpcplus_default {
 852                 function = "LPCPLUS";
 853                 groups = "LPCPLUS";
 854         };
 855
 856         pinctrl_lpcpme_default: lpcpme_default {
 857                 function = "LPCPME";
 858                 groups = "LPCPME";
 859         };
 860
 861         pinctrl_lpcrst_default: lpcrst_default {
 862                 function = "LPCRST";
 863                 groups = "LPCRST";
 864         };
 865
 866         pinctrl_lpcsmi_default: lpcsmi_default {
 867                 function = "LPCSMI";
 868                 groups = "LPCSMI";
 869         };
 870
 871         pinctrl_lsirq_default: lsirq_default {
 872                 function = "LSIRQ";
 873                 groups = "LSIRQ";
 874         };
 875
 876         pinctrl_mac1link_default: mac1link_default {
 877                 function = "MAC1LINK";
 878                 groups = "MAC1LINK";
 879         };
 880
 881         pinctrl_mac2link_default: mac2link_default {
 882                 function = "MAC2LINK";
 883                 groups = "MAC2LINK";
 884         };
 885
 886         pinctrl_mdio1_default: mdio1_default {
 887                 function = "MDIO1";
 888                 groups = "MDIO1";
 889         };
 890
 891         pinctrl_mdio2_default: mdio2_default {
 892                 function = "MDIO2";
 893                 groups = "MDIO2";
 894         };
 895
 896         pinctrl_ncts1_default: ncts1_default {
 897                 function = "NCTS1";
 898                 groups = "NCTS1";
 899         };
 900
 901         pinctrl_ncts2_default: ncts2_default {
 902                 function = "NCTS2";
 903                 groups = "NCTS2";
 904         };
 905
 906         pinctrl_ncts3_default: ncts3_default {
 907                 function = "NCTS3";
 908                 groups = "NCTS3";
 909         };
 910
 911         pinctrl_ncts4_default: ncts4_default {
 912                 function = "NCTS4";
 913                 groups = "NCTS4";
 914         };
 915
 916         pinctrl_ndcd1_default: ndcd1_default {
 917                 function = "NDCD1";
 918                 groups = "NDCD1";
 919         };
 920
 921         pinctrl_ndcd2_default: ndcd2_default {
 922                 function = "NDCD2";
 923                 groups = "NDCD2";
 924         };
 925
 926         pinctrl_ndcd3_default: ndcd3_default {
 927                 function = "NDCD3";
 928                 groups = "NDCD3";
 929         };
 930
 931         pinctrl_ndcd4_default: ndcd4_default {
 932                 function = "NDCD4";
 933                 groups = "NDCD4";
 934         };
 935
 936         pinctrl_ndsr1_default: ndsr1_default {
 937                 function = "NDSR1";
 938                 groups = "NDSR1";
 939         };
 940
 941         pinctrl_ndsr2_default: ndsr2_default {
 942                 function = "NDSR2";
 943                 groups = "NDSR2";
 944         };
 945
 946         pinctrl_ndsr3_default: ndsr3_default {
 947                 function = "NDSR3";
 948                 groups = "NDSR3";
 949         };
 950
 951         pinctrl_ndsr4_default: ndsr4_default {
 952                 function = "NDSR4";
 953                 groups = "NDSR4";
 954         };
 955
 956         pinctrl_ndtr1_default: ndtr1_default {
 957                 function = "NDTR1";
 958                 groups = "NDTR1";
 959         };
 960
 961         pinctrl_ndtr2_default: ndtr2_default {
 962                 function = "NDTR2";
 963                 groups = "NDTR2";
 964         };
 965
 966         pinctrl_ndtr3_default: ndtr3_default {
 967                 function = "NDTR3";
 968                 groups = "NDTR3";
 969         };
 970
 971         pinctrl_ndtr4_default: ndtr4_default {
 972                 function = "NDTR4";
 973                 groups = "NDTR4";
 974         };
 975
 976         pinctrl_nri1_default: nri1_default {
 977                 function = "NRI1";
 978                 groups = "NRI1";
 979         };
 980
 981         pinctrl_nri2_default: nri2_default {
 982                 function = "NRI2";
 983                 groups = "NRI2";
 984         };
 985
 986         pinctrl_nri3_default: nri3_default {
 987                 function = "NRI3";
 988                 groups = "NRI3";
 989         };
 990
 991         pinctrl_nri4_default: nri4_default {
 992                 function = "NRI4";
 993                 groups = "NRI4";
 994         };
 995
 996         pinctrl_nrts1_default: nrts1_default {
 997                 function = "NRTS1";
 998                 groups = "NRTS1";
 999         };
1000
1001         pinctrl_nrts2_default: nrts2_default {
1002                 function = "NRTS2";
1003                 groups = "NRTS2";
1004         };
1005
1006         pinctrl_nrts3_default: nrts3_default {
1007                 function = "NRTS3";
1008                 groups = "NRTS3";
1009         };
1010
1011         pinctrl_nrts4_default: nrts4_default {
1012                 function = "NRTS4";
1013                 groups = "NRTS4";
1014         };
1015
1016         pinctrl_oscclk_default: oscclk_default {
1017                 function = "OSCCLK";
1018                 groups = "OSCCLK";
1019         };
1020
1021         pinctrl_pewake_default: pewake_default {
1022                 function = "PEWAKE";
1023                 groups = "PEWAKE";
1024         };
1025
1026         pinctrl_pnor_default: pnor_default {
1027                 function = "PNOR";
1028                 groups = "PNOR";
1029         };
1030
1031         pinctrl_pwm0_default: pwm0_default {
1032                 function = "PWM0";
1033                 groups = "PWM0";
1034         };
1035
1036         pinctrl_pwm1_default: pwm1_default {
1037                 function = "PWM1";
1038                 groups = "PWM1";
1039         };
1040
1041         pinctrl_pwm2_default: pwm2_default {
1042                 function = "PWM2";
1043                 groups = "PWM2";
1044         };
1045
1046         pinctrl_pwm3_default: pwm3_default {
1047                 function = "PWM3";
1048                 groups = "PWM3";
1049         };
1050
1051         pinctrl_pwm4_default: pwm4_default {
1052                 function = "PWM4";
1053                 groups = "PWM4";
1054         };
1055
1056         pinctrl_pwm5_default: pwm5_default {
1057                 function = "PWM5";
1058                 groups = "PWM5";
1059         };
1060
1061         pinctrl_pwm6_default: pwm6_default {
1062                 function = "PWM6";
1063                 groups = "PWM6";
1064         };
1065
1066         pinctrl_pwm7_default: pwm7_default {
1067                 function = "PWM7";
1068                 groups = "PWM7";
1069         };
1070
1071         pinctrl_rgmii1_default: rgmii1_default {
1072                 function = "RGMII1";
1073                 groups = "RGMII1";
1074         };
1075
1076         pinctrl_rgmii2_default: rgmii2_default {
1077                 function = "RGMII2";
1078                 groups = "RGMII2";
1079         };
1080
1081         pinctrl_rmii1_default: rmii1_default {
1082                 function = "RMII1";
1083                 groups = "RMII1";
1084         };
1085
1086         pinctrl_rmii2_default: rmii2_default {
1087                 function = "RMII2";
1088                 groups = "RMII2";
1089         };
1090
1091         pinctrl_rxd1_default: rxd1_default {
1092                 function = "RXD1";
1093                 groups = "RXD1";
1094         };
1095
1096         pinctrl_rxd2_default: rxd2_default {
1097                 function = "RXD2";
1098                 groups = "RXD2";
1099         };
1100
1101         pinctrl_rxd3_default: rxd3_default {
1102                 function = "RXD3";
1103                 groups = "RXD3";
1104         };
1105
1106         pinctrl_rxd4_default: rxd4_default {
1107                 function = "RXD4";
1108                 groups = "RXD4";
1109         };
1110
1111         pinctrl_salt1_default: salt1_default {
1112                 function = "SALT1";
1113                 groups = "SALT1";
1114         };
1115
1116         pinctrl_salt10_default: salt10_default {
1117                 function = "SALT10";
1118                 groups = "SALT10";
1119         };
1120
1121         pinctrl_salt11_default: salt11_default {
1122                 function = "SALT11";
1123                 groups = "SALT11";
1124         };
1125
1126         pinctrl_salt12_default: salt12_default {
1127                 function = "SALT12";
1128                 groups = "SALT12";
1129         };
1130
1131         pinctrl_salt13_default: salt13_default {
1132                 function = "SALT13";
1133                 groups = "SALT13";
1134         };
1135
1136         pinctrl_salt14_default: salt14_default {
1137                 function = "SALT14";
1138                 groups = "SALT14";
1139         };
1140
1141         pinctrl_salt2_default: salt2_default {
1142                 function = "SALT2";
1143                 groups = "SALT2";
1144         };
1145
1146         pinctrl_salt3_default: salt3_default {
1147                 function = "SALT3";
1148                 groups = "SALT3";
1149         };
1150
1151         pinctrl_salt4_default: salt4_default {
1152                 function = "SALT4";
1153                 groups = "SALT4";
1154         };
1155
1156         pinctrl_salt5_default: salt5_default {
1157                 function = "SALT5";
1158                 groups = "SALT5";
1159         };
1160
1161         pinctrl_salt6_default: salt6_default {
1162                 function = "SALT6";
1163                 groups = "SALT6";
1164         };
1165
1166         pinctrl_salt7_default: salt7_default {
1167                 function = "SALT7";
1168                 groups = "SALT7";
1169         };
1170
1171         pinctrl_salt8_default: salt8_default {
1172                 function = "SALT8";
1173                 groups = "SALT8";
1174         };
1175
1176         pinctrl_salt9_default: salt9_default {
1177                 function = "SALT9";
1178                 groups = "SALT9";
1179         };
1180
1181         pinctrl_scl1_default: scl1_default {
1182                 function = "SCL1";
1183                 groups = "SCL1";
1184         };
1185
1186         pinctrl_scl2_default: scl2_default {
1187                 function = "SCL2";
1188                 groups = "SCL2";
1189         };
1190
1191         pinctrl_sd1_default: sd1_default {
1192                 function = "SD1";
1193                 groups = "SD1";
1194         };
1195
1196         pinctrl_sd2_default: sd2_default {
1197                 function = "SD2";
1198                 groups = "SD2";
1199         };
1200
1201         pinctrl_sda1_default: sda1_default {
1202                 function = "SDA1";
1203                 groups = "SDA1";
1204         };
1205
1206         pinctrl_sda2_default: sda2_default {
1207                 function = "SDA2";
1208                 groups = "SDA2";
1209         };
1210
1211         pinctrl_sgps1_default: sgps1_default {
1212                 function = "SGPS1";
1213                 groups = "SGPS1";
1214         };
1215
1216         pinctrl_sgps2_default: sgps2_default {
1217                 function = "SGPS2";
1218                 groups = "SGPS2";
1219         };
1220
1221         pinctrl_sioonctrl_default: sioonctrl_default {
1222                 function = "SIOONCTRL";
1223                 groups = "SIOONCTRL";
1224         };
1225
1226         pinctrl_siopbi_default: siopbi_default {
1227                 function = "SIOPBI";
1228                 groups = "SIOPBI";
1229         };
1230
1231         pinctrl_siopbo_default: siopbo_default {
1232                 function = "SIOPBO";
1233                 groups = "SIOPBO";
1234         };
1235
1236         pinctrl_siopwreq_default: siopwreq_default {
1237                 function = "SIOPWREQ";
1238                 groups = "SIOPWREQ";
1239         };
1240
1241         pinctrl_siopwrgd_default: siopwrgd_default {
1242                 function = "SIOPWRGD";
1243                 groups = "SIOPWRGD";
1244         };
1245
1246         pinctrl_sios3_default: sios3_default {
1247                 function = "SIOS3";
1248                 groups = "SIOS3";
1249         };
1250
1251         pinctrl_sios5_default: sios5_default {
1252                 function = "SIOS5";
1253                 groups = "SIOS5";
1254         };
1255
1256         pinctrl_siosci_default: siosci_default {
1257                 function = "SIOSCI";
1258                 groups = "SIOSCI";
1259         };
1260
1261         pinctrl_spi1_default: spi1_default {
1262                 function = "SPI1";
1263                 groups = "SPI1";
1264         };
1265
1266         pinctrl_spi1cs1_default: spi1cs1_default {
1267                 function = "SPI1CS1";
1268                 groups = "SPI1CS1";
1269         };
1270
1271         pinctrl_spi1debug_default: spi1debug_default {
1272                 function = "SPI1DEBUG";
1273                 groups = "SPI1DEBUG";
1274         };
1275
1276         pinctrl_spi1passthru_default: spi1passthru_default {
1277                 function = "SPI1PASSTHRU";
1278                 groups = "SPI1PASSTHRU";
1279         };
1280
1281         pinctrl_spi2ck_default: spi2ck_default {
1282                 function = "SPI2CK";
1283                 groups = "SPI2CK";
1284         };
1285
1286         pinctrl_spi2cs0_default: spi2cs0_default {
1287                 function = "SPI2CS0";
1288                 groups = "SPI2CS0";
1289         };
1290
1291         pinctrl_spi2cs1_default: spi2cs1_default {
1292                 function = "SPI2CS1";
1293                 groups = "SPI2CS1";
1294         };
1295
1296         pinctrl_spi2miso_default: spi2miso_default {
1297                 function = "SPI2MISO";
1298                 groups = "SPI2MISO";
1299         };
1300
1301         pinctrl_spi2mosi_default: spi2mosi_default {
1302                 function = "SPI2MOSI";
1303                 groups = "SPI2MOSI";
1304         };
1305
1306         pinctrl_timer3_default: timer3_default {
1307                 function = "TIMER3";
1308                 groups = "TIMER3";
1309         };
1310
1311         pinctrl_timer4_default: timer4_default {
1312                 function = "TIMER4";
1313                 groups = "TIMER4";
1314         };
1315
1316         pinctrl_timer5_default: timer5_default {
1317                 function = "TIMER5";
1318                 groups = "TIMER5";
1319         };
1320
1321         pinctrl_timer6_default: timer6_default {
1322                 function = "TIMER6";
1323                 groups = "TIMER6";
1324         };
1325
1326         pinctrl_timer7_default: timer7_default {
1327                 function = "TIMER7";
1328                 groups = "TIMER7";
1329         };
1330
1331         pinctrl_timer8_default: timer8_default {
1332                 function = "TIMER8";
1333                 groups = "TIMER8";
1334         };
1335
1336         pinctrl_txd1_default: txd1_default {
1337                 function = "TXD1";
1338                 groups = "TXD1";
1339         };
1340
1341         pinctrl_txd2_default: txd2_default {
1342                 function = "TXD2";
1343                 groups = "TXD2";
1344         };
1345
1346         pinctrl_txd3_default: txd3_default {
1347                 function = "TXD3";
1348                 groups = "TXD3";
1349         };
1350
1351         pinctrl_txd4_default: txd4_default {
1352                 function = "TXD4";
1353                 groups = "TXD4";
1354         };
1355
1356         pinctrl_uart6_default: uart6_default {
1357                 function = "UART6";
1358                 groups = "UART6";
1359         };
1360
1361         pinctrl_usbcki_default: usbcki_default {
1362                 function = "USBCKI";
1363                 groups = "USBCKI";
1364         };
1365
1366         pinctrl_vgabiosrom_default: vgabiosrom_default {
1367                 function = "VGABIOSROM";
1368                 groups = "VGABIOSROM";
1369         };
1370
1371         pinctrl_vgahs_default: vgahs_default {
1372                 function = "VGAHS";
1373                 groups = "VGAHS";
1374         };
1375
1376         pinctrl_vgavs_default: vgavs_default {
1377                 function = "VGAVS";
1378                 groups = "VGAVS";
1379         };
1380
1381         pinctrl_vpi24_default: vpi24_default {
1382                 function = "VPI24";
1383                 groups = "VPI24";
1384         };
1385
1386         pinctrl_vpo_default: vpo_default {
1387                 function = "VPO";
1388                 groups = "VPO";
1389         };
1390
1391         pinctrl_wdtrst1_default: wdtrst1_default {
1392                 function = "WDTRST1";
1393                 groups = "WDTRST1";
1394         };
1395
1396         pinctrl_wdtrst2_default: wdtrst2_default {
1397                 function = "WDTRST2";
1398                 groups = "WDTRST2";
1399         };
1400 };